From 95b8b66ec6d3cdd9789bc54fd937b548ab501515 Mon Sep 17 00:00:00 2001 From: guozhanxin Date: Wed, 20 May 2026 15:42:15 +0800 Subject: [PATCH 1/2] =?UTF-8?q?fix[tool]zigbuild:=20=E9=80=82=E9=85=8DZig?= =?UTF-8?q?=200.14+=E7=89=88=E6=9C=AC=E7=9A=84=E6=9E=84=E5=BB=BA=E8=84=9A?= =?UTF-8?q?=E6=9C=AC=E5=8F=98=E6=9B=B4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit 新增Zig版本检测逻辑，根据当前Zig版本切换兼容的构建配置： 0.14及以上版本使用新的模块构建API， 低于0.14版本保留原有构建逻辑 --- tools/targets/zigbuild.py | 86 ++++++++++++++++++++++++++++++--------- 1 file changed, 67 insertions(+), 19 deletions(-) diff --git a/tools/targets/zigbuild.py b/tools/targets/zigbuild.py index 8811639d340..26063de36e3 100644 --- a/tools/targets/zigbuild.py +++ b/tools/targets/zigbuild.py @@ -6,11 +6,28 @@ import os import sys import re +import subprocess import utils import rtconfig from utils import _make_path_relative +def get_zig_version(): + try: + result = subprocess.run(['zig', 'version'], capture_output=True, text=True) + version_str = result.stdout.strip() + parts = version_str.split('.') + major = int(parts[0]) + minor = int(parts[1]) if len(parts) > 1 else 0 + return (major, minor) + except Exception: + return (0, 0) + + +ZIG_VERSION = get_zig_version() +IS_ZIG_0_14_PLUS = ZIG_VERSION[0] > 0 or (ZIG_VERSION[0] == 0 and ZIG_VERSION[1] >= 14) + + def GenerateCFiles(env,project): info = utils.ProjectInfo(env) @@ -23,12 +40,23 @@ def GenerateCFiles(env,project): if zig_file: zig_file.write("const std = @import(\"std\");\n\n") - zig_file.write("const target = std.zig.CrossTarget{\n") - zig_file.write(" .cpu_arch = {},\n".format(ARCH)) - zig_file.write(" .cpu_model = .{{ .explicit = &std.Target.{}.cpu.{} }},\n".format(rtconfig.ARCH, rtconfig.CPU.replace('-', '_'))) - zig_file.write(" .os_tag = .freestanding,\n") - zig_file.write(" .abi = .eabi,\n") - zig_file.write("};\n\n") + if IS_ZIG_0_14_PLUS: + zig_file.write("const target = std.Target.Query{\n") + zig_file.write(" .cpu_arch = {},\n".format(ARCH)) + zig_file.write(" .cpu_model = .{{ .explicit = &std.Target.{}.cpu.{} }},\n".format(rtconfig.ARCH, rtconfig.CPU.replace('-', '_'))) + zig_file.write(" .os_tag = .freestanding,\n") + if ARCH == ".thumb": + zig_file.write(" .abi = .eabihf,\n") + else: + zig_file.write(" .abi = .eabi,\n") + zig_file.write("};\n\n") + else: + zig_file.write("const target = std.zig.CrossTarget{\n") + zig_file.write(" .cpu_arch = {},\n".format(ARCH)) + zig_file.write(" .cpu_model = .{{ .explicit = &std.Target.{}.cpu.{} }},\n".format(rtconfig.ARCH, rtconfig.CPU.replace('-', '_'))) + zig_file.write(" .os_tag = .freestanding,\n") + zig_file.write(" .abi = .eabi,\n") + zig_file.write("};\n\n") zig_file.write("const c_includes = [_][]const u8{\n") for i in info['CPPPATH']: @@ -60,20 +88,34 @@ def GenerateCFiles(env,project): zig_file.write("};\n\n") zig_file.write("pub fn build(b: *std.Build) void {\n") - zig_file.write(" const optimize = .ReleaseSafe;\n\n") - - zig_file.write(" const elf = b.addExecutable(.{\n") - zig_file.write(" .name = \"rtthread.elf\",\n") - zig_file.write(" .target = b.resolveTargetQuery(target),\n") - zig_file.write(" .optimize = optimize,\n") - zig_file.write(" .strip = false,\n") - zig_file.write(" });\n\n") - zig_file.write(" elf.entry = .{ .symbol_name = \"Reset_Handler\" };\n\n") + zig_file.write(" const optimize = .ReleaseSmall;\n\n") + + if IS_ZIG_0_14_PLUS: + zig_file.write(" const root_module = b.createModule(.{\n") + zig_file.write(" .root_source_file = null,\n") + zig_file.write(" .target = b.resolveTargetQuery(target),\n") + zig_file.write(" .optimize = optimize,\n") + zig_file.write(" .strip = false,\n") + zig_file.write(" });\n\n") + + zig_file.write(" root_module.addCSourceFiles(.{ .files = &c_sources, .flags = &c_flags });\n") + zig_file.write(" for (c_includes) |include| {\n") + zig_file.write(" root_module.addIncludePath(b.path(include));\n") + zig_file.write(" }\n\n") + + zig_file.write(" const elf = b.addExecutable(.{\n") + zig_file.write(" .name = \"rtthread.elf\",\n") + zig_file.write(" .root_module = root_module,\n") + zig_file.write(" });\n\n") + else: + zig_file.write(" const elf = b.addExecutable(.{\n") + zig_file.write(" .name = \"rtthread.elf\",\n") + zig_file.write(" .target = b.resolveTargetQuery(target),\n") + zig_file.write(" .optimize = optimize,\n") + zig_file.write(" .strip = false,\n") + zig_file.write(" });\n\n") - zig_file.write(" elf.addCSourceFiles(.{ .files = &c_sources, .flags = &c_flags });\n") - zig_file.write(" for (c_includes) |include| {\n") - zig_file.write(" elf.addIncludePath(b.path(include));\n") - zig_file.write(" }\n\n") + zig_file.write(" elf.entry = .{ .symbol_name = \"Reset_Handler\" };\n\n") # find link script in rtconfig.LFLAGS LINK_SCRIPT = re.search(r'-T\s*(\S+)', LFLAGS) @@ -93,6 +135,12 @@ def GenerateCFiles(env,project): return def ZigBuildProject(env,project): + version_str = "{}.{}".format(ZIG_VERSION[0], ZIG_VERSION[1]) + print('Detected Zig version: {}'.format(version_str)) + if IS_ZIG_0_14_PLUS: + print('Using Zig 0.14+ compatible build configuration') + else: + print('Using legacy build configuration') print('Update setting files for build.zig...') GenerateCFiles(env,project) print('Done!') From bc9ba8a385614ab1e4aa7411e10068d237c20a87 Mon Sep 17 00:00:00 2001 From: guozhanxin Date: Fri, 22 May 2026 14:29:58 +0800 Subject: [PATCH 2/2] =?UTF-8?q?[bsp][stm32]=E5=AE=8C=E5=96=84=E6=98=9F?= =?UTF-8?q?=E7=81=AB1=E5=8F=B7=E9=93=BE=E6=8E=A5=E8=84=9A=E6=9C=AC?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- bsp/stm32/stm32f407-rt-spark/board/linker_scripts/link.lds | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/bsp/stm32/stm32f407-rt-spark/board/linker_scripts/link.lds b/bsp/stm32/stm32f407-rt-spark/board/linker_scripts/link.lds index 2d48a9e3478..db56fb32d69 100644 --- a/bsp/stm32/stm32f407-rt-spark/board/linker_scripts/link.lds +++ b/bsp/stm32/stm32f407-rt-spark/board/linker_scripts/link.lds @@ -70,6 +70,7 @@ SECTIONS } > CODE = 0 /* .ARM.exidx is sorted, so has to go in its own output section. */ + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > CODE __exidx_start = .; .ARM.exidx : { @@ -102,7 +103,7 @@ SECTIONS _edata = . ; } >RAM1 - .stack : + .stack (NOLOAD): { . = ALIGN(4); _sstack = .; @@ -112,7 +113,7 @@ SECTIONS } >RAM1 __bss_start = .; - .bss : + .bss (NOLOAD): { . = ALIGN(4); /* This is used by the startup in order to initialize the .bss secion */