Optimizing writes in nobag inference kernel#157
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When D is an exact multiple of (kWarpSize * kOutputsPerThread), skip the half2 scale/bias header at row[0] via a +1 read offset (in scalar_t units) and drop the D_padding shift on output_d. This eliminates the mostly-empty tail iteration that the original loop runs, which on AMD wave-64 for D=256 wastes 63/64 lanes. The branch is hoisted out of the per-iter loop nest — the compiler hoists the predicate but not the branch itself, which would otherwise add ~3-5% per-iter overhead on non-triggering D values.
avbokovoy
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May 20, 2026
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Overall LGTM with potential for further improvements
| {% else %} | ||
| using scalar_t = {{ emb_weight_type.cpp_type_name }}; | ||
| {% if emb_weight_type.primitive_type == "INT" and is_rocm %} | ||
| if (D % (kWarpSize * kOutputsPerThread) == 0 && D_padding > 0) { |
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Ain't always D_padding > 0 in case of quantization to INT?
| auto thread_local_max = std::numeric_limits<float>::lowest(); | ||
| float2 qparams; | ||
| // Pass 1: min/max scan | ||
| for (uint32_t j = 0; j < opt_iters; ++j) { |
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Loops with opt_iters worth be investigated as a candidate for manual loop unrolling
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I did investigate that. I created a dynamic if-else ladder for different embedding dimensions (256, 512, 768 etc.) and manually unrolling the loops within each case. This negatively impacted the performance, though
… packedMode effects in nobag kernel
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Summary
Adds a shifted-index store fast path for the INT-weight nobag inference forward kernel (
{INT8,INT4,INT2}_split_embedding_nobag_codegen_forward_unweighted_kernel_small_L) on ROCm.When
D % (kWarpSize * kOutputsPerThread) == 0andD_padding > 0, the original store loop wastes one full iteration: the lastjiteration is fully masked out by theoutput_d < Dguard because the per-row header offset (-D_padding) shifts every lane belowD. The fast path iteratesD / (kWarpSize * kOutputsPerThread)times instead of(MaxNum128BRows + 1) / 2, drops the bounds check, and reads weights at[j * kWarpSize + threadIdx.x + kHeaderScalarOffset]to absorb the header offset on the load side.The runtime check is hoisted outside the per-
input_row_idx/ per-iloops to avoid ~3-5% per-iter branch overhead on non-triggering D values. Bagged path is unchanged.Scope
is_rocmJinja gate); CUDA path is byte-identical to upstream.Validation