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nmirom.s
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3187 lines (2804 loc) · 56 KB
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;
; HACK menu (an NMI trigger menu for M4 board)
; Written by Duke 2018/2019 - http://www.spinpoint.org
;
; Added menu keyboard shortcuts, improved memory dump feature
; by Cebe74
;
; Assemble with RASM assembler from http://www.roudoudou.com/rasm/
; into nmirom.bin and use M4 firmware "dev version" (M4FIRM_dev_version.zip) to load it from root of microSD card
;
C_OPEN equ 0x4301
C_READ equ 0x4302
C_READ2 equ 0x4312
C_WRITE equ 0x4303
C_RENAME equ 0x430F
C_WRITE2 equ 0x431B
C_COPYFILE2 equ 0x431C
C_CLOSE equ 0x4304
C_SEEK equ 0x4305
C_READDIR equ 0x4306
C_NMIOFF equ 0x4319
C_ROMWRITE equ 0x43FD
FA_READ equ 1
FA_WRITE equ 2
FA_CREATE_NEW equ 4
FA_CREATE_ALWAYS equ 8
FA_OPEN_ALWAYS equ 16
FA_REALMODE equ 128
DATAPORT equ 0xFE00
ACKPORT equ 0xFC00
;snamem equ 0xF300
; screen layout (column<<8)|line
L_MAINTITLE equ (51<<8)|24
L_Z80_REGSTITLE equ (L_Z80_REGS_X<<8)|L_Z80_REGS_Y
L_Z80_REGS_X equ 60
L_Z80_REGS_Y equ 7
L_HW_REGS_X equ 0
L_HW_REGS_Y equ 7
L_HW_REGSHEADER equ (L_HW_REGS_X+6<<8)|L_HW_REGS_Y
L_HW_REGS equ (L_HW_REGS_X<<8)|L_HW_REGS_Y+2
L_HW_RMR_MMR_ROM_X equ 60
L_HW_RMR_MMR_ROM_Y equ 18
L_HW_PPI_X equ 71
L_HW_PPI_Y equ 18
L_KEYBOARDTYPE equ (60<<8)|21
L_MENU_X equ 0
L_MENU_Y equ 13
L_MENU equ (L_MENU_X+3<<8)|L_MENU_Y
L_SAVESNAPSHOT equ (0<<8)|23
I_SAVESNAPSHOT equ (16<<8)|60 ; xpos=16, max_len = 60
L_SAVING equ (0<<8)|24
L_LOADSNAPSHOT equ (0<<8)|23
I_LOADSNAPSHOT equ (16<<8)|60 ; xpos=16, max_len = 60
L_LOADING equ (0<<8)|24
L_DUMPSIZE equ (L_MENU_X+3+20<<8)|L_MENU_Y+2
L_POKEADDRESS equ (0<<8)|23
I_POKEADDRESS equ (6<<8)|4 ; xpos=6, max_len = 4
L_POKEVAL equ (12<<8)|23
I_POKEVAL equ (17<<8)|2 ; xpos=16, max_len = 2
L_POKEAPPLIED equ (0<<8)|24
L_DISPMEM equ (0<<8)|23
I_DISPMEM equ (6<<8)|4 ; xpos=6, max_len = 4
L_DISPMEMDUMP equ (0<<8)|0
N_DISPMEM equ 6
N_DISPMEMBYTES equ N_DISPMEM*16
org 0x0
m4romnum: db 6
keyb_layout: db 0
org 0x38
ld a,1
ret
org 0x66
nmi: jp main
org 0x100
; sna header
sna_header: db "MV - SNA"
unused: ds 8,0
version: db 1
cpu_regs: ds 29,0
ga_pen: db 0
palette: ds 17,0
ga_multi: db 0
ramconf: db 0
crtc_sel: db 0
crtc_regs: ds 18,0
romsel: db 0
ppiA: db 0
ppiB: db 0
ppiC: db 0
ppiCtrl: db 0
psg_sel: db 0
psg_regs: ds 16,0
memdump_sz: db 0
reserved: ds 116,0
m4snaident: db "M4 Board by Duke"
ds 16,0
; at entry
; lowerrom is force enabled in romCore logic, until next RMR write
; ramdis & romdis is asserted in read from 0-0x3FFF
main:
; store regs
ld (0xFFFE),sp ; 0xFFFE
ld sp,0xFFFC
push hl ; 0xFFFA
push de ; 0xFFF8
push bc ; 0xFFF6
push af ; 0xFFF4
ld a,r
push af ; 0xFFF2
ld a,i
push af ; 0xFFF0
ld a,(m4romnum)
ld bc, 0xDF00
out (c),a ; select M4 rom
;
; first write to RMR, enables lowerrom, so we are no longer executing from RAMDIS "ram" mode
;
ld bc, 0x7F8A ; enable upper and lower rom
out (c),c
; NMI is set back to open drain
; and RAMDIS signal set to back to input signal (no driving)
; disable ram dis
ld bc,DATAPORT ; data out port
out (c),c
ld a, 0x1A ;
out (c),a ; command lo
ld a, 0x43 ;
out (c),a ; command hi
ld b,ACKPORT>>8 ; kick command
out (c),c
ld bc, 0x7F8A ; enable lower rom and disable upper
out (c),c
; setup CRTC (to ensure interrupt is generated)
ld sp,0xFFFC
; mute sound
ld hl,ui_psg_regs+15
ld a,15
psg_loop:
ld bc,0xF4C0
out (c),a
ld b, 0xF6
out (c),c
out (c),0
dec b
outd
ld bc,0xF680
out (c),c
out (c),0
dec a
jp p,psg_loop
; setup CRTC (to ensure interrupt is generated)
ld hl,ui_crtc_regs+16
ld bc,0xbc0f
crtc_loop:
out (c),c
dec hl
ld a,(hl)
inc b
out (c),a
dec b
dec c
jp p,crtc_loop
ld hl,cpu_regs
; copy regs to ROM
ld bc,DATAPORT ; data out port
out (c),c
ld a, C_ROMWRITE & 0xFF ;
out (c),a ; command lo
ld a, C_ROMWRITE>>8 ;
out (c),a ; command hi
out (c),l ; rom dest addr
out (c),h ; rom dest addr => snamem
ld a,29
out (c),a ; size
xor a
out (c),a ; size 29
ld a,255
out (c),a ; 1 bank (0 = M4 ROM, 255 = nmi rom)
; copy af,bc,de,hl to snamem+0x11
ld a,8
ld hl, 0xFFF4
cp_regs4:
inc b
outi
dec a
jr nz,cp_regs4
ld a, (0xFFF3) ; r
out (c),a
ld a,(0xFFF1) ; i
out (c),a
ld a,(0xFFF2) ; get flags (PF flag)
srl a
srl a
and 1
out (c),a ; IFF0
out (c),a ; IFF1
db 0xDD,0x5D ; ld e, IXl
db 0xDD,0x54 ; ld d, IXh
out (c),e ; IXl
out (c),d ; IXh
db 0xFD,0x5D ; ld e, IXl
db 0xFD,0x54 ; ld d, IXh
out (c),e ; IYl
out (c),d ; IYh
ld hl,(0xFFFE)
ld de,2
add hl,de ; skip PC on stack (not using retn)
out (c),l
out (c),h
xor a
ld hl,get_pc_stack
ld de,0xFFF0
ld bc,12
ldir
ld hl,(0xFFFE)
ld bc,0x7F8C
jp 0xFFF0 ; read PC from stack with both roms disabled.
ret_pc:
ld bc,DATAPORT
out (c),e ; PCl
out (c),d ; PCh
ld sp,0xFFFE
ld a,im2_jumptable>>8
ld i,a
xor a
;ld hl,detect
;push hl
;retn
detect:
ei
halt
di
; a should now return 1 for IM 1 and 2 for IM2
out (c),a
; save alternate reg set
ex af,af'
push af ; 0x..
ex af,af'
pop hl
out (c),l ; AF´l
out (c),h ; AF´h
exx
push bc
exx
pop hl
out (c),l ; BC´l
out (c),h ; BC´h
exx
ld bc,DATAPORT
out (c),e ; DE´l
out (c),d ; DE´h
out (c),l ; HL´l
out (c),h ; HL´h
exx
ld bc,ACKPORT
out (c),c ; write it to M4 rom
ld bc, 0x7F8A ; enable upper and lower rom
out (c),c
; -- put code here
ld sp,0xFFFC
;jr back ; temp skip write mem
jp write_base_ram
back_write_base_ram:
ld sp,0xC000
ld bc, 0x7F82 ; enable upper and lower rom, screen mode 2
out (c),c
ld a,(memdump_sz)
cp 0
jr nz,no_detect
; detect if 64KB or 128KB ram
ld bc,0x7FC0
out (c),c
ld a,(0x6000)
xor 0xF5
ld (0x6000),a
ld e,a
ld a,(0x6001)
xor 0xA3
ld (0x6001),a
ld d,a
; select bank 4
ld bc,0x7FC7
out (c),c
ld c,0x40 ; 64KB
ld a,(0x6000)
cp e
jr z,not_128
ld a,(0x6001)
cp d
jr z,not_128
ld c,0x80 ; 128KB
not_128:
ld e,c
ld bc,0x7FC0
out (c),c
call set_dump_size
no_detect:
call write_jumper
ld bc, 0x7F8A ; disable upper and enable lower rom, screen mode 2
out (c),c
; ui handling
call interface
ld bc, 0x7F82 ; enable upper and lower rom
out (c),c
ld sp,0
jp read_base_ram
ret_read_base_ram:
ld bc, 0x7F82 ; enable upper and lower rom
out (c),c
ld a,(sna_header+0x25)
cp 0
jr nz, not_im0
im 0
not_im0:cp 1
jr nz, not_im1
im 1
not_im1:cp 2
jr nz, not_im2
im 2
not_im2:
; store "sna jumper" copy in RAM aswell
ld hl,0xFFF0
ld d,h
ld e,l
ld bc, 16
ldir
ld bc, 0x7F8A ; disable upper and enable lower rom, screen mode 2
out (c),c
;jp skipset
; Setup pen colors 0 to 15 and border color
ld hl,sna_header+0x2F+16
ld bc,0x7F10
SNA_SetupGA:
out (c),c
ld a,(hl)
dec hl
set 6,a
out (c),a
dec c
jp p,SNA_SetupGA
; Select last active pen
ld a,(hl)
out (c),a
; CRTC setup
ld hl,sna_header+0x43+17
ld bc,0xBD00+17
SNA_SetupCRTC:
dec b
out (c),c
ld b,0xBE
outd
dec c
jp p,SNA_SetupCRTC
; Select active CRTC register
; HL = Offset &42
; B = &BD
outd
; ram config
ld a,(sna_header+0x41)
or 0xC0
ld bc,0x7f00
out (c),a
; Setup AY3 registers
ld hl,sna_header+0x5B+15
ld a,15
SNA_SetupAY3:
ld bc,0xF4C0
out (c),a
ld b, 0xF6
out (c),c
out (c),0
dec b
outd
ld bc,0xF680
out (c),c
out (c),0
dec a
jp p,SNA_SetupAY3
; Select last active AY3 register
ld bc,0xF5C0
outd
ld b,0xF6
out (c),c
out (c),0
; will disable nmi rom in "next" rmr write
ld bc,DATAPORT
xor a
out (c),a ; ignore first byte
ld a,C_NMIOFF&0xFF
out (c),a
ld a,C_NMIOFF>>8
out (c),a
ld b,ACKPORT>>8 ; kick command
out (c),c
; pop registers
exx
ex af, af' ; '
ld sp,sna_header+0x26
pop af
pop bc
pop de
pop hl
ex af, af' ; '
exx
ld sp,sna_header+0x15
pop de
pop hl
ld a,(sna_header+0x1A)
ld i,a
ld sp,sna_header+0x1d
pop ix
pop iy
ld a,(ga_multi)
or 0x80
ld c,a
ld b,0x7F
ld sp,cpu_regs ; sna_header+0x11
pop af
ld sp,(sna_header+0x21)
jp 0xFFF0
; exit back
; write jump back routine to upper rom
; only use reg a and bc
write_jumper:
ld bc,DATAPORT ; data out port
out (c),c
ld a, C_ROMWRITE & 0xFF ;
out (c),a ; command lo
ld a, C_ROMWRITE>>8 ;
out (c),a ; command hi
ld a,0xF0
out (c),a ; rom dest addr
ld a,0xFF
out (c),a ; rom dest addr 0xFFF0
ld a,14
out (c),a ; size
xor a
out (c),a ; size 12
out (c),a ; 0 bank (0 = M4 ROM)
; code
ld a,0xED
out (c),a ; 1
ld a,0x49
out (c),a ; 2 ED 49 out (c),c
ld a,0x01
out (c),a ; 3 ld bc,0xDFxx
ld a,(romsel)
out (c),a ; 4 xx
ld a,0xDF
out (c),a ; 5 DF
ld a,0xED
out (c),a ; 6
ld a,0x49
out (c),a ; 7 ED 49 out (c),c
ld a,0x01 ;
out (c),a ; 8 ld bc,xxxx
ld hl,(cpu_regs+2)
out (c),l ; 9
out (c),h ; 10
ld l, 0xFB ; ei
ld a,(sna_header+0x1B)
and 1
jr nz,int_en
ld l,0xF3 ; di
int_en:
out (c),l ; 11
ld a,0xC3
out (c),a ; 12 JP
ld hl,(sna_header+0x23) ;
out (c),l ; 13 PCl
out (c),h ; 14 PCh
ld b,ACKPORT>>8 ; kick command
out (c),c
ret
; hl = src filename
; copy sna file into tmp1.bin
load_sna:
ld a,(m4romnum)
ld bc, 0xDF00
out (c),a ; select M4 rom
ld bc, 0x7F82 ; enable upper and lower rom
out (c),c
ld iy,(0xFF02) ; get ROM response table
;
ld bc,DATAPORT
out (c),c ; ignore first byte
ld a,C_COPYFILE2&0xFF
out (c),a
ld a,C_COPYFILE2>>8
out (c),a
; output dest filename
ld de, temp_fn
lsrc_fn:
ld a,(de)
inc de
out (c),a
or a
jr nz, lsrc_fn
; output src filename
ld e,l
ld d,h
ldest_fn:
ld a,(de)
inc de
out (c),a
or a
jr nz, ldest_fn
ld b,ACKPORT>>8 ; kick command
out (c),c
ld a,(iy+3) ; get response
or a
ret nz
; read sna header
ld hl,cmd_open2
ld bc,DATAPORT
ld a,17
rsendloop2:
inc b
outi
dec a
jr nz, rsendloop2
ld b,ACKPORT>>8 ; kick command
out (c),c
ld e,(iy+3) ; get fd
ld bc,DATAPORT
out (c),c ; ignore first byte
ld a,C_READ2&0xFF
out (c),a
ld a,C_READ2>>8
out (c),a
out (c),e ; fd
xor a
out (c),a ; size 00
ld a,1
out (c),a ; size 0x0100
ld b,ACKPORT>>8 ; kick command
out (c),c
push de
; overwrite current sna header
ld bc,DATAPORT ; data out port
out (c),c
ld a, C_ROMWRITE & 0xFF ;
out (c),a ; command lo
ld a, C_ROMWRITE>>8 ;
out (c),a ; command hi
xor a
out (c),a ; rom dest addr
ld a,0x1 ;
out (c),a ; offset 0x100
ld a,0xFF
out (c),a ; size
xor a
out (c),a ; size 00E0
ld a,255
out (c),a ; 1 bank (0 = M4 ROM, 255 = nmi rom)
ld hl,(0xFF02)
ld de,8
add hl,de ; point to response data
ld d,0xFF
wrtsnahead:
ld a,(hl)
out (c),a ; write memdump size
inc hl
dec d
jr nz,wrtsnahead
ld b,ACKPORT>>8 ; kick command
out (c),c
call write_jumper
pop de ; restore fd
; load banks, if needed
ld a,(memdump_sz)
cp 0x40
jr z,no_add_banks
ld bc,DATAPORT
out (c),c ; ignore first byte
ld a,C_SEEK&0xFF
out (c),a
ld a,C_SEEK>>8
out (c),a
out (c),e ; fd
xor a
out (c),a
ld a,1
out (c),a ; size 0x0100
ld a,1
out (c),a
xor a
out (c),a ; size 0x00010100
ld b,ACKPORT>>8 ; kick command
out (c),c
ld bc,0x7FC4
banks_loop:
out (c),c ; select bank
push bc
exx
ld de,0x4000
exx
ld d,8 ; 8 * 2048 = 16384
readbnkloop:
ld bc,DATAPORT
out (c),c ; ignore first byte
ld a,C_READ2&0xFF
out (c),a
ld a,C_READ2>>8
out (c),a
out (c),e ; fd
xor a
out (c),a ; size 00
ld a,8
out (c),a ; size 0x0800
ld b,ACKPORT>>8 ; kick command
out (c),c
exx
ld hl,(0xFF02) ; copy to ram
ld bc,8
add hl,bc
; de increases from 0
ld bc,0x800
ldir
exx
dec d
jr nz, readbnkloop
pop bc
inc c ; next bank
ld a,0xC8
cp c
jr nz,banks_loop
ld bc,0x7FC0
out (c),c
no_add_banks:
; close the file
ld bc,DATAPORT
out (c),c ; ignore first byte
ld a,C_CLOSE&0xFF
out (c),a
ld a,C_CLOSE>>8
out (c),a
out (c),e ; fd
ld b,ACKPORT>>8 ; kick command
out (c),c
xor a
ret
write_sna:
ld a,(m4romnum)
ld bc, 0xDF00
out (c),a ; select M4 rom
ld bc, 0x7F82 ; enable upper and lower rom
out (c),c
ld iy,(0xFF02) ; get ROM response table
;
ld bc,DATAPORT
out (c),c ; ignore first byte
ld a,C_COPYFILE2&0xFF
out (c),a
ld a,C_COPYFILE2>>8
out (c),a
; output dest filename
ld e,l
ld d,h
dest_fn:
ld a,(de)
inc de
out (c),a
or a
jr nz, dest_fn
; output src filename
ld de, temp_fn
src_fn:
ld a,(de)
inc de
out (c),a
or a
jr nz, src_fn
ld b,ACKPORT>>8 ; kick command
out (c),c
ld a,(iy+3) ; get response
cp 0
ret nz
; open dest file
ld bc,DATAPORT
out (c),c ; ignore first byte
ld a,C_OPEN&0xFF
out (c),a
ld a,C_OPEN>>8
out (c),a
ld a,FA_READ | FA_WRITE | FA_REALMODE
out (c),a
; filename still in HL
new_fn:
ld a,(hl)
inc hl
out (c),a
or a
jr nz, new_fn
ld b,ACKPORT>>8 ; kick command
out (c),c
; now overwrite sna header, with valid one
ld bc,DATAPORT
out (c),c ; ignore first byte
ld a,C_WRITE2&0xFF
out (c),a
ld a,C_WRITE2>>8
out (c),a
ld e,(iy+3) ; get fd
out (c),e ; fd
xor a
out (c),a ; size 00
ld a,0x1
out (c),a ; size 0x0100
ld hl,sna_header
ld a,255
sendhead2:
inc b
outi
dec a
jr nz, sendhead2
inc b
outi
ld b,ACKPORT>>8 ; kick command
out (c),c
; check if 128KB
ld a,(memdump_sz)
cp 0x40
jr z,is_only64KB
; otherwise write extended banks also
ld bc,DATAPORT
out (c),c ; ignore first byte
ld a,C_SEEK&0xFF
out (c),a
ld a,C_SEEK>>8
out (c),a
out (c),e ; fd
xor a
out (c),a
ld a,1
out (c),a ; size 0x0100
out (c),a ; size 0x010100
xor a
out (c),a ; size 0x00010100
ld b,ACKPORT>>8 ; kick command
out (c),c
; write banks
exx
ld bc,0x7FC4
ld e,4
bankloop:
out (c),c
exx
ld d,16 ; 16 * 1024 = 16384
ld hl,0x4000
writebank:
ld bc,DATAPORT
out (c),c ; ignore first byte
ld a,C_WRITE2&0xFF
out (c),a
ld a,C_WRITE2>>8
out (c),a
out (c),e ; fd
db 0xDD,0x6B ; ld IXl, e
db 0xDD,0x62 ; ld IXh, d
ld de,0x400
out (c),e ; size 00
out (c),d ; size 0x0400
xor a
sendbank:
inc b ; 1
outi ; 2
dec de ; 1
cp e ; 1
jr nz,sendbank ; 2
cp d ; 1
jr nz, sendbank ; 2 = 10
ld b,ACKPORT>>8 ; kick command
out (c),c
db 0xDD,0x5D ; ld e, IXl
db 0xDD,0x54 ; ld d, IXh
dec d
jr nz, writebank
exx
inc c ; C4, C5..
dec e
jr nz,bankloop
exx
is_only64KB:
; close the file
ld bc,DATAPORT
out (c),c ; ignore first byte
ld a,C_CLOSE&0xFF
out (c),a
ld a,C_CLOSE>>8
out (c),a
out (c),e ; fd
ld b,ACKPORT>>8 ; kick command
out (c),c
; done
xor a
ret
read_base_ram:
; open file for read
ld hl,cmd_open2
ld bc,DATAPORT
ld a,17
rsendloop1:
inc b
outi
dec a
jr nz, rsendloop1
ld b,ACKPORT>>8 ; kick command
out (c),c
ld bc,0x7FC0
out (c),c
ld a,(m4romnum)
ld bc, 0xDF00
out (c),a ; select M4 rom
ld bc, 0x7F82 ; enable upper and lower rom
out (c),c
ld iy,(0xFF02) ; get ROM response table
ld e,(iy+3) ; get fd
ld bc,DATAPORT
out (c),c ; ignore first byte
ld a,C_SEEK&0xFF
out (c),a
ld a,C_SEEK>>8
out (c),a
out (c),e ; fd
xor a
out (c),a
ld a,1
out (c),a ; size 0x0100
xor a
out (c),a
out (c),a ; size 0x00000100
ld b,ACKPORT>>8 ; kick command
out (c),c
exx
ld de,0
exx
ld d,32 ; 64 * 1024 = 65536
readloop:
ld bc,DATAPORT
out (c),c ; ignore first byte
ld a,C_READ2&0xFF
out (c),a
ld a,C_READ2>>8
out (c),a
out (c),e ; fd
xor a
out (c),a ; size 00
ld a,8
out (c),a ; size 0x0800
ld b,ACKPORT>>8 ; kick command
out (c),c
exx
ld hl,(0xFF02) ; copy to ram
ld bc,8
add hl,bc
; de increases from 0
ld bc,0x800