[ERROR] Failed to register evaluation callback

[mikeurbach]

Hi @Kuree, I was able to get HGDB running with VCS on a design. But when I tried to debug it, I received this error in the VCS logs:

[ERROR] Failed to register evaluation callback

Do you have any idea where that comes from?

The steps I took were:

• run the simulation with VCS
• pick a random line that was present in the HGDB json symbol table and set a breakpoint
• run the simulation in VS Code

As the simulation starts, the error is printed out, and now the debugger UI waits. The breakpoint is now marked Unverified Breakpoint:

If I click the step or run button in the UI, the simulation proceeds until complete, but no debugger breakpoint is triggered.

Let me know if you have any idea what could be happening. This is not an open source design, but I can try to reproduce with RocketChip if that would be helpful.

[mikeurbach]

If it matters, I will share one other point about the setup. Because I haven't been able to get remote debug working (Kuree/hgdb-debugger#9), I set up the debugger with VCS on the remote machine, but ran VS Code on the local machine (with port forwarding to the remote port 8888). The code on the local machine is on the exact same commit as the code used to generate the debug symbol table on the remote machine. Since CIRCT file locators currently don't use absolute paths, I thought it shouldn't matter, but I could be mistaken.

[Kuree]

This error comes from heuristics that tries to attach the debugging logic to the clock:

hgdb/src/debug.cc

Lines 1162 to 1169 in f0f876e

	void Debugger::add_cb_clocks() {
	if (rtl_ && !rtl_->is_verilator()) {
	// only trigger eval at the posedge clk
	auto clock_signals = util::get_clock_signals(rtl_.get(), db_.get());
	bool r = rtl_->monitor_signals(clock_signals, eval_hgdb_on_clk, this);
	if (!r || clock_signals.empty()) log_error("Failed to register evaluation callback");
	}
	}

which uses the two strategies to obtain the clock signals from the design:

1. If a particular signals is annotated in the symbol table as the clock signal
2. Walk from the top to every module instance and see if the name matches

You can see the code here:

hgdb/src/scheduler.cc

Lines 578 to 594 in f0f876e

	std::vector<std::string> get_clock_signals(RTLSimulatorClient *rtl, SymbolTableProvider *db) {
	if (!rtl) return {};
	std::vector<std::string> result;
	if (db) {
	// always load from db first
	auto db_clock_names = db->get_annotation_values("clock");
	for (auto const &name : db_clock_names) {
	auto full_name = rtl->get_full_name(name);
	result.emplace_back(full_name);
	}
	}
	if (result.empty()) {
	// use rtl based heuristics
	result = rtl->get_clocks_from_design();
	}
	return result;
	}

The RocketChip uses the clock signal names that covered by option 2, so it works out fine. I haven't added attribute-based implementation to JSON-based symbol table yet. I will work on this as soon as I can and let you know how to modify the symbol table to use option 1 and see if it helps.

[Kuree]

@mikeurbach Can you try to add design-level clock information to the symbol table? Here is an example:

hgdb/tests/test_db.cc

Lines 936 to 941 in b4ea7d0

	"attributes": [
	{
	"name": "clock",
	"value": "mod.clock"
	}
	]

The value should be a hierarchical path from the design top (the design generated from CIRCT). For instance, if the design top module is called Chip and it contains a clock signal called clk, you should put Chip.clk as the value. The runtime backend will automatically map the name into the complete path during the simulation.

[mikeurbach]

Thanks for the pointers and the quick turnaround. I will see if I can get the clock annotation to work for this design.