Makefile

TOP=tb/tb_simplerisc.v
RTL=rtl/simplerisc_top.v rtl/decode.vh rtl/immu.v rtl/alu.v rtl/regfile.v rtl/control_unit.v rtl/imem.v rtl/dmem.v
ALU=rtl/bk_adder32.v rtl/alu.v rtl/mul_tree32.v rtl/div_nonrestoring32_bk.v rtl/barrel_shifter.v rtl/slt.v rtl/bk_subtractor32.v
TB=tb/tb_simplerisc.v
VVP=sim.vvp

all: run

test_alu:
	iverilog -g2012 -I rtl -o build/alu_tb.vvp tb/alu_tb.v $(ALU)
	vvp build/alu_tb.vvp

test_simplerisc:
	iverilog -g2012 -I rtl -o build/tb_simplerisc.vvp rtl/*.v  $(TOP)
	vvp build/tb_simplerisc.vvp

assemble:
	python tools/asm.py program.asm program.hex

build:
	iverilog -g2012 -o $(VVP) $(TB) $(RTL)

run: build
	vvp $(VVP)

wave: run
	@echo "Open wave.vcd in GTKWave"

clean:
	rm -f $(VVP) wave.vcd