diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and.cir b/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and.pro b/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and.sch b/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and.sub b/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and-cache.lib new file mode 100644 index 000000000..fc177c1f9 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and-rescue.lib b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and-rescue.lib new file mode 100644 index 000000000..483b8efb8 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and.cir b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and.cir new file mode 100644 index 000000000..6a05b9b5d --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and.cir.out new file mode 100644 index 000000000..6a6b126a7 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and.pro b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and.pro new file mode 100644 index 000000000..c16a3f858 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and.pro @@ -0,0 +1,49 @@ +update=Wed Mar 18 19:59:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_User +LibName15=eSim_Sources +LibName16=eSim_Subckt diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and.sch b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and.sch new file mode 100644 index 000000000..aef3c0436 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:5_and-rescue +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_User +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-5_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and.sub b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and.sub new file mode 100644 index 000000000..35b10e173 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and_Previous_Values.xml new file mode 100644 index 000000000..ae2c08a7f --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/5_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141-cache.lib new file mode 100644 index 000000000..504bcdc37 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141-cache.lib @@ -0,0 +1,200 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141.cir b/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141.cir new file mode 100644 index 000000000..698f7e425 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141.cir @@ -0,0 +1,51 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74141\74141.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/21/26 15:43:02 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad3_ Net-_Q10-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q1-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q3-Pad3_ Net-_Q10-Pad2_ Net-_Q4-Pad3_ eSim_NPN +Q5 Net-_Q5-Pad1_ Net-_Q1-Pad2_ Net-_Q5-Pad3_ eSim_NPN +Q6 Net-_Q5-Pad3_ Net-_Q10-Pad2_ Net-_Q6-Pad3_ eSim_NPN +Q7 Net-_Q7-Pad1_ Net-_Q1-Pad2_ Net-_Q7-Pad3_ eSim_NPN +Q8 Net-_Q7-Pad3_ Net-_Q10-Pad2_ Net-_Q8-Pad3_ eSim_NPN +Q9 Net-_Q9-Pad1_ Net-_Q1-Pad2_ Net-_Q10-Pad1_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +U10 GND Net-_Q1-Pad1_ zener +U11 GND Net-_Q2-Pad3_ zener +U12 GND Net-_Q3-Pad1_ zener +U13 GND Net-_Q4-Pad3_ zener +U14 GND Net-_Q5-Pad1_ zener +U15 GND Net-_Q6-Pad3_ zener +U16 GND Net-_Q7-Pad1_ zener +U17 GND Net-_Q8-Pad3_ zener +U18 GND Net-_Q9-Pad1_ zener +U19 GND Net-_Q10-Pad3_ zener +X4 Net-_U22-Pad1_ Net-_U23-Pad1_ Net-_U24-Pad1_ Net-_U25-Pad1_ Net-_U4-Pad3_ Net-_U27-Pad1_ 5_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_and +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_and +U4 Net-_U1-Pad3_ Net-_U2-Pad3_ Net-_U4-Pad3_ d_nor +U6 Net-_U1-Pad1_ Net-_U4-Pad3_ Net-_U22-Pad1_ d_nand +U3 Net-_U20-Pad3_ Net-_U21-Pad1_ d_inverter +U5 Net-_U21-Pad1_ Net-_U26-Pad1_ d_inverter +X3 Net-_U23-Pad1_ Net-_U4-Pad3_ Net-_U2-Pad2_ Net-_U9-Pad1_ 3_and +X2 Net-_U4-Pad3_ Net-_U1-Pad2_ Net-_U23-Pad1_ Net-_U8-Pad1_ 3_and +X1 Net-_U1-Pad2_ Net-_U4-Pad3_ Net-_U2-Pad2_ Net-_U7-Pad1_ 3_and +U7 Net-_U7-Pad1_ Net-_U23-Pad1_ d_inverter +U8 Net-_U8-Pad1_ Net-_U24-Pad1_ d_inverter +U9 Net-_U9-Pad1_ Net-_U25-Pad1_ d_inverter +U20 Net-_Q1-Pad1_ Net-_Q2-Pad3_ Net-_U20-Pad3_ Net-_U1-Pad1_ ? Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_Q8-Pad3_ Net-_Q7-Pad1_ Net-_Q3-Pad1_ Net-_Q4-Pad3_ GND Net-_Q6-Pad3_ Net-_Q5-Pad1_ Net-_Q9-Pad1_ Net-_Q10-Pad3_ PORT +U22 Net-_U22-Pad1_ Net-_Q1-Pad3_ dac_bridge_1 +U23 Net-_U23-Pad1_ Net-_Q3-Pad3_ dac_bridge_1 +U24 Net-_U24-Pad1_ Net-_Q5-Pad3_ dac_bridge_1 +U25 Net-_U25-Pad1_ Net-_Q7-Pad3_ dac_bridge_1 +U26 Net-_U26-Pad1_ Net-_Q1-Pad2_ dac_bridge_1 +U27 Net-_U27-Pad1_ Net-_Q10-Pad1_ dac_bridge_1 +U21 Net-_U21-Pad1_ Net-_Q10-Pad2_ dac_bridge_1 + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141.cir.out new file mode 100644 index 000000000..27d514aad --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141.cir.out @@ -0,0 +1,133 @@ +* c:\fossee\esim\library\subcircuitlibrary\74141\74141.cir + +.include 3_and.sub +.include 5_and.sub +.include NPN.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q1-pad3_ net-_q10-pad2_ net-_q2-pad3_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad2_ net-_q3-pad3_ Q2N2222 +q4 net-_q3-pad3_ net-_q10-pad2_ net-_q4-pad3_ Q2N2222 +q5 net-_q5-pad1_ net-_q1-pad2_ net-_q5-pad3_ Q2N2222 +q6 net-_q5-pad3_ net-_q10-pad2_ net-_q6-pad3_ Q2N2222 +q7 net-_q7-pad1_ net-_q1-pad2_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q10-pad2_ net-_q8-pad3_ Q2N2222 +q9 net-_q9-pad1_ net-_q1-pad2_ net-_q10-pad1_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +* u10 gnd net-_q1-pad1_ zener +* u11 gnd net-_q2-pad3_ zener +* u12 gnd net-_q3-pad1_ zener +* u13 gnd net-_q4-pad3_ zener +* u14 gnd net-_q5-pad1_ zener +* u15 gnd net-_q6-pad3_ zener +* u16 gnd net-_q7-pad1_ zener +* u17 gnd net-_q8-pad3_ zener +* u18 gnd net-_q9-pad1_ zener +* u19 gnd net-_q10-pad3_ zener +x4 net-_u22-pad1_ net-_u23-pad1_ net-_u24-pad1_ net-_u25-pad1_ net-_u4-pad3_ net-_u27-pad1_ 5_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u4 net-_u1-pad3_ net-_u2-pad3_ net-_u4-pad3_ d_nor +* u6 net-_u1-pad1_ net-_u4-pad3_ net-_u22-pad1_ d_nand +* u3 net-_u20-pad3_ net-_u21-pad1_ d_inverter +* u5 net-_u21-pad1_ net-_u26-pad1_ d_inverter +x3 net-_u23-pad1_ net-_u4-pad3_ net-_u2-pad2_ net-_u9-pad1_ 3_and +x2 net-_u4-pad3_ net-_u1-pad2_ net-_u23-pad1_ net-_u8-pad1_ 3_and +x1 net-_u1-pad2_ net-_u4-pad3_ net-_u2-pad2_ net-_u7-pad1_ 3_and +* u7 net-_u7-pad1_ net-_u23-pad1_ d_inverter +* u8 net-_u8-pad1_ net-_u24-pad1_ d_inverter +* u9 net-_u9-pad1_ net-_u25-pad1_ d_inverter +* u20 net-_q1-pad1_ net-_q2-pad3_ net-_u20-pad3_ net-_u1-pad1_ ? net-_u2-pad2_ net-_u1-pad2_ net-_q8-pad3_ net-_q7-pad1_ net-_q3-pad1_ net-_q4-pad3_ gnd net-_q6-pad3_ net-_q5-pad1_ net-_q9-pad1_ net-_q10-pad3_ port +* u22 net-_u22-pad1_ net-_q1-pad3_ dac_bridge_1 +* u23 net-_u23-pad1_ net-_q3-pad3_ dac_bridge_1 +* u24 net-_u24-pad1_ net-_q5-pad3_ dac_bridge_1 +* u25 net-_u25-pad1_ net-_q7-pad3_ dac_bridge_1 +* u26 net-_u26-pad1_ net-_q1-pad2_ dac_bridge_1 +* u27 net-_u27-pad1_ net-_q10-pad1_ dac_bridge_1 +* u21 net-_u21-pad1_ net-_q10-pad2_ dac_bridge_1 +a1 gnd net-_q1-pad1_ u10 +a2 gnd net-_q2-pad3_ u11 +a3 gnd net-_q3-pad1_ u12 +a4 gnd net-_q4-pad3_ u13 +a5 gnd net-_q5-pad1_ u14 +a6 gnd net-_q6-pad3_ u15 +a7 gnd net-_q7-pad1_ u16 +a8 gnd net-_q8-pad3_ u17 +a9 gnd net-_q9-pad1_ u18 +a10 gnd net-_q10-pad3_ u19 +a11 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1 +a12 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a13 [net-_u1-pad3_ net-_u2-pad3_ ] net-_u4-pad3_ u4 +a14 [net-_u1-pad1_ net-_u4-pad3_ ] net-_u22-pad1_ u6 +a15 net-_u20-pad3_ net-_u21-pad1_ u3 +a16 net-_u21-pad1_ net-_u26-pad1_ u5 +a17 net-_u7-pad1_ net-_u23-pad1_ u7 +a18 net-_u8-pad1_ net-_u24-pad1_ u8 +a19 net-_u9-pad1_ net-_u25-pad1_ u9 +a20 [net-_u22-pad1_ ] [net-_q1-pad3_ ] u22 +a21 [net-_u23-pad1_ ] [net-_q3-pad3_ ] u23 +a22 [net-_u24-pad1_ ] [net-_q5-pad3_ ] u24 +a23 [net-_u25-pad1_ ] [net-_q7-pad3_ ] u25 +a24 [net-_u26-pad1_ ] [net-_q1-pad2_ ] u26 +a25 [net-_u27-pad1_ ] [net-_q10-pad1_ ] u27 +a26 [net-_u21-pad1_ ] [net-_q10-pad2_ ] u21 +* Schematic Name: zener, NgSpice Name: zener +.model u10 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u11 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u12 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u13 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u14 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u15 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u16 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u17 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u18 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u19 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u23 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141.pro b/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141.sch b/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141.sch new file mode 100644 index 000000000..95c8465a5 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141.sch @@ -0,0 +1,1008 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 69996B1C +P 9050 1250 +F 0 "Q1" H 8950 1300 50 0000 R CNN +F 1 "eSim_NPN" H 9000 1400 50 0000 R CNN +F 2 "" H 9250 1350 29 0000 C CNN +F 3 "" H 9050 1250 60 0000 C CNN + 1 9050 1250 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 69996BA7 +P 9050 1650 +F 0 "Q2" H 8950 1700 50 0000 R CNN +F 1 "eSim_NPN" H 9000 1800 50 0000 R CNN +F 2 "" H 9250 1750 29 0000 C CNN +F 3 "" H 9050 1650 60 0000 C CNN + 1 9050 1650 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 69996C7B +P 9050 2200 +F 0 "Q3" H 8950 2250 50 0000 R CNN +F 1 "eSim_NPN" H 9000 2350 50 0000 R CNN +F 2 "" H 9250 2300 29 0000 C CNN +F 3 "" H 9050 2200 60 0000 C CNN + 1 9050 2200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 69996C81 +P 9050 2600 +F 0 "Q4" H 8950 2650 50 0000 R CNN +F 1 "eSim_NPN" H 9000 2750 50 0000 R CNN +F 2 "" H 9250 2700 29 0000 C CNN +F 3 "" H 9050 2600 60 0000 C CNN + 1 9050 2600 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 69996CBD +P 9050 3150 +F 0 "Q5" H 8950 3200 50 0000 R CNN +F 1 "eSim_NPN" H 9000 3300 50 0000 R CNN +F 2 "" H 9250 3250 29 0000 C CNN +F 3 "" H 9050 3150 60 0000 C CNN + 1 9050 3150 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 69996CC3 +P 9050 3550 +F 0 "Q6" H 8950 3600 50 0000 R CNN +F 1 "eSim_NPN" H 9000 3700 50 0000 R CNN +F 2 "" H 9250 3650 29 0000 C CNN +F 3 "" H 9050 3550 60 0000 C CNN + 1 9050 3550 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 69996DD2 +P 9050 4200 +F 0 "Q7" H 8950 4250 50 0000 R CNN +F 1 "eSim_NPN" H 9000 4350 50 0000 R CNN +F 2 "" H 9250 4300 29 0000 C CNN +F 3 "" H 9050 4200 60 0000 C CNN + 1 9050 4200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 69996DD8 +P 9050 4600 +F 0 "Q8" H 8950 4650 50 0000 R CNN +F 1 "eSim_NPN" H 9000 4750 50 0000 R CNN +F 2 "" H 9250 4700 29 0000 C CNN +F 3 "" H 9050 4600 60 0000 C CNN + 1 9050 4600 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 69996E34 +P 9050 5300 +F 0 "Q9" H 8950 5350 50 0000 R CNN +F 1 "eSim_NPN" H 9000 5450 50 0000 R CNN +F 2 "" H 9250 5400 29 0000 C CNN +F 3 "" H 9050 5300 60 0000 C CNN + 1 9050 5300 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 69996E3A +P 9050 5700 +F 0 "Q10" H 8950 5750 50 0000 R CNN +F 1 "eSim_NPN" H 9000 5850 50 0000 R CNN +F 2 "" H 9250 5800 29 0000 C CNN +F 3 "" H 9050 5700 60 0000 C CNN + 1 9050 5700 + 0 -1 -1 0 +$EndComp +$Comp +L zener U10 +U 1 1 69996E60 +P 10000 1200 +F 0 "U10" H 9950 1100 60 0000 C CNN +F 1 "zener" H 10000 1300 60 0000 C CNN +F 2 "" H 10050 1200 60 0000 C CNN +F 3 "" H 10050 1200 60 0000 C CNN + 1 10000 1200 + -1 0 0 1 +$EndComp +$Comp +L zener U11 +U 1 1 69996EE6 +P 10000 1650 +F 0 "U11" H 9950 1550 60 0000 C CNN +F 1 "zener" H 10000 1750 60 0000 C CNN +F 2 "" H 10050 1650 60 0000 C CNN +F 3 "" H 10050 1650 60 0000 C CNN + 1 10000 1650 + -1 0 0 1 +$EndComp +$Comp +L zener U12 +U 1 1 69996F2A +P 10000 2200 +F 0 "U12" H 9950 2100 60 0000 C CNN +F 1 "zener" H 10000 2300 60 0000 C CNN +F 2 "" H 10050 2200 60 0000 C CNN +F 3 "" H 10050 2200 60 0000 C CNN + 1 10000 2200 + -1 0 0 1 +$EndComp +$Comp +L zener U13 +U 1 1 69996F77 +P 10000 2650 +F 0 "U13" H 9950 2550 60 0000 C CNN +F 1 "zener" H 10000 2750 60 0000 C CNN +F 2 "" H 10050 2650 60 0000 C CNN +F 3 "" H 10050 2650 60 0000 C CNN + 1 10000 2650 + -1 0 0 1 +$EndComp +$Comp +L zener U14 +U 1 1 69996FBD +P 10000 3100 +F 0 "U14" H 9950 3000 60 0000 C CNN +F 1 "zener" H 10000 3200 60 0000 C CNN +F 2 "" H 10050 3100 60 0000 C CNN +F 3 "" H 10050 3100 60 0000 C CNN + 1 10000 3100 + -1 0 0 1 +$EndComp +$Comp +L zener U15 +U 1 1 69997008 +P 10000 3600 +F 0 "U15" H 9950 3500 60 0000 C CNN +F 1 "zener" H 10000 3700 60 0000 C CNN +F 2 "" H 10050 3600 60 0000 C CNN +F 3 "" H 10050 3600 60 0000 C CNN + 1 10000 3600 + -1 0 0 1 +$EndComp +$Comp +L zener U16 +U 1 1 69997058 +P 10000 4200 +F 0 "U16" H 9950 4100 60 0000 C CNN +F 1 "zener" H 10000 4300 60 0000 C CNN +F 2 "" H 10050 4200 60 0000 C CNN +F 3 "" H 10050 4200 60 0000 C CNN + 1 10000 4200 + -1 0 0 1 +$EndComp +$Comp +L zener U17 +U 1 1 699970AF +P 10000 4600 +F 0 "U17" H 9950 4500 60 0000 C CNN +F 1 "zener" H 10000 4700 60 0000 C CNN +F 2 "" H 10050 4600 60 0000 C CNN +F 3 "" H 10050 4600 60 0000 C CNN + 1 10000 4600 + -1 0 0 1 +$EndComp +$Comp +L zener U18 +U 1 1 69997107 +P 10000 5300 +F 0 "U18" H 9950 5200 60 0000 C CNN +F 1 "zener" H 10000 5400 60 0000 C CNN +F 2 "" H 10050 5300 60 0000 C CNN +F 3 "" H 10050 5300 60 0000 C CNN + 1 10000 5300 + -1 0 0 1 +$EndComp +$Comp +L zener U19 +U 1 1 69997166 +P 10000 5700 +F 0 "U19" H 9950 5600 60 0000 C CNN +F 1 "zener" H 10000 5800 60 0000 C CNN +F 2 "" H 10050 5700 60 0000 C CNN +F 3 "" H 10050 5700 60 0000 C CNN + 1 10000 5700 + -1 0 0 1 +$EndComp +$Comp +L 5_and X4 +U 1 1 69997A0D +P 7650 5500 +F 0 "X4" H 7700 5400 60 0000 C CNN +F 1 "5_and" H 7750 5650 60 0000 C CNN +F 2 "" H 7650 5500 60 0000 C CNN +F 3 "" H 7650 5500 60 0000 C CNN + 1 7650 5500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U1 +U 1 1 69997D24 +P 1800 1650 +F 0 "U1" H 1800 1650 60 0000 C CNN +F 1 "d_and" H 1850 1750 60 0000 C CNN +F 2 "" H 1800 1650 60 0000 C CNN +F 3 "" H 1800 1650 60 0000 C CNN + 1 1800 1650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 69997E30 +P 1800 2300 +F 0 "U2" H 1800 2300 60 0000 C CNN +F 1 "d_and" H 1850 2400 60 0000 C CNN +F 2 "" H 1800 2300 60 0000 C CNN +F 3 "" H 1800 2300 60 0000 C CNN + 1 1800 2300 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U4 +U 1 1 69997E92 +P 2700 1950 +F 0 "U4" H 2700 1950 60 0000 C CNN +F 1 "d_nor" H 2750 2050 60 0000 C CNN +F 2 "" H 2700 1950 60 0000 C CNN +F 3 "" H 2700 1950 60 0000 C CNN + 1 2700 1950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U6 +U 1 1 69997F1D +P 4000 1150 +F 0 "U6" H 4000 1150 60 0000 C CNN +F 1 "d_nand" H 4050 1250 60 0000 C CNN +F 2 "" H 4000 1150 60 0000 C CNN +F 3 "" H 4000 1150 60 0000 C CNN + 1 4000 1150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 69997FDC +P 1950 5150 +F 0 "U3" H 1950 5050 60 0000 C CNN +F 1 "d_inverter" H 1950 5300 60 0000 C CNN +F 2 "" H 2000 5100 60 0000 C CNN +F 3 "" H 2000 5100 60 0000 C CNN + 1 1950 5150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 699980C4 +P 3350 5150 +F 0 "U5" H 3350 5050 60 0000 C CNN +F 1 "d_inverter" H 3350 5300 60 0000 C CNN +F 2 "" H 3400 5100 60 0000 C CNN +F 3 "" H 3400 5100 60 0000 C CNN + 1 3350 5150 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 69997C74 +P 3850 4300 +F 0 "X3" H 3950 4250 60 0000 C CNN +F 1 "3_and" H 4000 4450 60 0000 C CNN +F 2 "" H 3850 4300 60 0000 C CNN +F 3 "" H 3850 4300 60 0000 C CNN + 1 3850 4300 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 69997BF9 +P 3850 3400 +F 0 "X2" H 3950 3350 60 0000 C CNN +F 1 "3_and" H 4000 3550 60 0000 C CNN +F 2 "" H 3850 3400 60 0000 C CNN +F 3 "" H 3850 3400 60 0000 C CNN + 1 3850 3400 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 69997AC4 +P 3850 2550 +F 0 "X1" H 3950 2500 60 0000 C CNN +F 1 "3_and" H 4000 2700 60 0000 C CNN +F 2 "" H 3850 2550 60 0000 C CNN +F 3 "" H 3850 2550 60 0000 C CNN + 1 3850 2550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 69998ED9 +P 4750 2500 +F 0 "U7" H 4750 2400 60 0000 C CNN +F 1 "d_inverter" H 4750 2650 60 0000 C CNN +F 2 "" H 4800 2450 60 0000 C CNN +F 3 "" H 4800 2450 60 0000 C CNN + 1 4750 2500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 69998F53 +P 4750 3350 +F 0 "U8" H 4750 3250 60 0000 C CNN +F 1 "d_inverter" H 4750 3500 60 0000 C CNN +F 2 "" H 4800 3300 60 0000 C CNN +F 3 "" H 4800 3300 60 0000 C CNN + 1 4750 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 69998FCF +P 4800 4250 +F 0 "U9" H 4800 4150 60 0000 C CNN +F 1 "d_inverter" H 4800 4400 60 0000 C CNN +F 2 "" H 4850 4200 60 0000 C CNN +F 3 "" H 4850 4200 60 0000 C CNN + 1 4800 4250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9250 1350 10350 1350 +Wire Wire Line + 9250 1550 10350 1550 +Wire Wire Line + 9700 1200 9700 1350 +Connection ~ 9700 1350 +Wire Wire Line + 9700 1650 9700 1550 +Connection ~ 9700 1550 +Wire Wire Line + 9250 2300 10350 2300 +Wire Wire Line + 9250 2500 10350 2500 +Wire Wire Line + 9700 2200 9700 2300 +Connection ~ 9700 2300 +Wire Wire Line + 9700 2650 9700 2500 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+ 9050 6350 9050 5900 +Wire Wire Line + 2600 6350 2600 5150 +Connection ~ 2600 5150 +Wire Wire Line + 3500 4350 700 4350 +Wire Wire Line + 1350 2300 1150 2300 +Wire Wire Line + 1150 2300 1150 4350 +Connection ~ 1150 4350 +Connection ~ 1150 2600 +Wire Wire Line + 1350 1650 800 1650 +Wire Wire Line + 800 1650 800 3350 +Wire Wire Line + 600 3350 3500 3350 +Connection ~ 800 3350 +Wire Wire Line + 3550 1150 3250 1150 +Wire Wire Line + 3250 1150 3250 4750 +Wire Wire Line + 3250 4750 3900 4750 +Wire Wire Line + 3900 4750 3900 5700 +Wire Wire Line + 3900 5700 7200 5700 +Wire Wire Line + 3500 4250 3250 4250 +Connection ~ 3250 4250 +Connection ~ 3250 3450 +Wire Wire Line + 3500 2500 3250 2500 +Connection ~ 3250 2500 +Wire Wire Line + 2250 1600 2250 1850 +Wire Wire Line + 2250 1950 2250 2250 +Wire Wire Line + 1350 1550 1050 1550 +Wire Wire Line + 1050 1550 1050 1050 +Connection ~ 1050 1050 +Wire Wire Line + 1200 1550 1200 2200 +Wire Wire Line + 1200 2200 1350 2200 +Connection ~ 1200 1550 +Connection ~ 800 2400 +Wire Wire Line + 3500 2600 1150 2600 +Wire Wire Line + 3500 2400 800 2400 +Wire Wire Line + 4350 2500 4450 2500 +Wire Wire Line + 4350 3350 4450 3350 +Wire Wire Line + 4350 4250 4500 4250 +Wire Wire Line + 3500 3450 3400 3450 +Wire Wire Line + 3400 3450 3400 4150 +Wire Wire Line + 3400 4150 3500 4150 +Wire Wire Line + 3500 3250 3250 3250 +Connection ~ 3250 3250 +Wire Wire Line + 8850 1350 8650 1350 +Wire Wire Line + 8650 1100 8650 1550 +Wire Wire Line + 8650 1550 8850 1550 +Wire Wire Line + 8850 2300 8650 2300 +Wire Wire Line + 8650 2300 8650 2500 +Wire Wire Line + 8850 3250 8650 3250 +Wire Wire Line + 8650 3250 8650 3450 +Wire Wire Line + 8650 3450 8850 3450 +Wire Wire Line + 8850 4300 8700 4300 +Wire Wire Line + 8700 4250 8700 4500 +Wire Wire Line + 8700 4500 8850 4500 +Wire Wire Line + 8850 5400 8650 5400 +Wire Wire Line + 8650 5400 8650 5600 +Wire Wire Line + 8650 5600 8850 5600 +Connection ~ 8650 1350 +Connection ~ 8650 2500 +Connection ~ 8650 3350 +Connection ~ 8700 4300 +Wire Wire Line + 9050 1050 9050 850 +Wire Wire Line + 9050 850 8350 850 +Wire Wire Line + 8350 850 8350 5150 +Connection ~ 8350 5150 +Wire Wire Line + 9050 2000 8350 2000 +Connection ~ 8350 2000 +Wire Wire Line + 9050 2950 8350 2950 +Connection ~ 8350 2950 +Wire Wire Line + 9050 4000 8350 4000 +Connection ~ 8350 4000 +Wire Wire Line + 9050 1850 8500 1850 +Wire Wire Line + 8500 1850 8500 6350 +Connection ~ 8500 6350 +Wire Wire Line + 9050 2800 8500 2800 +Connection ~ 8500 2800 +Wire Wire Line + 9050 3750 8500 3750 +Connection ~ 8500 3750 +Wire Wire Line + 9050 4800 8500 4800 +Connection ~ 8500 4800 +Wire Wire Line + 7200 5300 7000 5300 +Wire Wire Line + 7000 5300 7000 1100 +Connection ~ 7000 1100 +Wire Wire Line + 7200 5400 6750 5400 +Wire Wire Line + 6750 5400 6750 2500 +Connection ~ 6750 2500 +Wire Wire Line + 7200 5500 6550 5500 +Wire Wire Line + 6550 5500 6550 3350 +Connection ~ 6550 3350 +Wire Wire Line + 7200 5600 6000 5600 +Wire Wire Line + 6000 5600 6000 4250 +Connection ~ 6000 4250 +Wire Wire Line + 3400 3800 6750 3800 +Connection ~ 6750 3800 +Connection ~ 3400 3800 +Wire Wire Line + 10200 1650 10700 1650 +Wire Wire Line + 10700 1650 10700 1700 +Wire Wire Line + 10200 2650 10750 2650 +Wire Wire Line + 10750 2650 10750 2700 +Wire Wire Line + 10200 3600 10750 3600 +Wire Wire Line + 10750 3600 10750 3700 +Wire Wire Line + 10200 4600 10750 4600 +Wire Wire Line + 10750 4600 10750 4700 +Wire Wire Line + 10200 5700 10750 5700 +Wire Wire Line + 10750 5700 10750 5750 +$Comp +L PORT U20 +U 1 1 6999B815 +P 10600 1350 +F 0 "U20" H 10650 1450 30 0000 C CNN +F 1 "PORT" H 10600 1350 30 0000 C CNN +F 2 "" H 10600 1350 60 0000 C CNN +F 3 "" H 10600 1350 60 0000 C CNN + 1 10600 1350 + -1 0 0 1 +$EndComp +$Comp +L PORT U20 +U 2 1 6999BB1E +P 10600 1550 +F 0 "U20" H 10650 1650 30 0000 C CNN +F 1 "PORT" H 10600 1550 30 0000 C CNN +F 2 "" H 10600 1550 60 0000 C CNN +F 3 "" H 10600 1550 60 0000 C CNN + 2 10600 1550 + -1 0 0 1 +$EndComp +$Comp +L PORT U20 +U 3 1 6999BB9F +P 850 5150 +F 0 "U20" H 900 5250 30 0000 C CNN +F 1 "PORT" H 850 5150 30 0000 C CNN +F 2 "" H 850 5150 60 0000 C CNN +F 3 "" H 850 5150 60 0000 C CNN + 3 850 5150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U20 +U 4 1 6999BC0C +P 700 1050 +F 0 "U20" H 750 1150 30 0000 C CNN +F 1 "PORT" H 700 1050 30 0000 C CNN +F 2 "" H 700 1050 60 0000 C CNN +F 3 "" H 700 1050 60 0000 C CNN + 4 700 1050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U20 +U 5 1 6999BC6F +P 800 7500 +F 0 "U20" H 850 7600 30 0000 C CNN +F 1 "PORT" H 800 7500 30 0000 C CNN +F 2 "" H 800 7500 60 0000 C CNN +F 3 "" H 800 7500 60 0000 C CNN + 5 800 7500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U20 +U 6 1 6999BCE2 +P 700 4600 +F 0 "U20" H 750 4700 30 0000 C CNN +F 1 "PORT" H 700 4600 30 0000 C CNN +F 2 "" H 700 4600 60 0000 C CNN +F 3 "" H 700 4600 60 0000 C CNN + 6 700 4600 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U20 +U 7 1 6999BD69 +P 600 3600 +F 0 "U20" H 650 3700 30 0000 C CNN +F 1 "PORT" H 600 3600 30 0000 C CNN +F 2 "" H 600 3600 60 0000 C CNN +F 3 "" H 600 3600 60 0000 C CNN + 7 600 3600 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U20 +U 8 1 6999BDDE +P 10600 4500 +F 0 "U20" H 10650 4600 30 0000 C CNN +F 1 "PORT" H 10600 4500 30 0000 C CNN +F 2 "" H 10600 4500 60 0000 C CNN +F 3 "" H 10600 4500 60 0000 C CNN + 8 10600 4500 + -1 0 0 1 +$EndComp +$Comp +L PORT U20 +U 9 1 6999BE4F +P 10600 4300 +F 0 "U20" H 10650 4400 30 0000 C CNN +F 1 "PORT" H 10600 4300 30 0000 C CNN +F 2 "" H 10600 4300 60 0000 C CNN +F 3 "" H 10600 4300 60 0000 C CNN + 9 10600 4300 + -1 0 0 1 +$EndComp +$Comp +L PORT U20 +U 10 1 6999BEC4 +P 10600 2300 +F 0 "U20" H 10650 2400 30 0000 C CNN +F 1 "PORT" H 10600 2300 30 0000 C CNN +F 2 "" H 10600 2300 60 0000 C CNN +F 3 "" H 10600 2300 60 0000 C CNN + 10 10600 2300 + -1 0 0 1 +$EndComp +$Comp +L PORT U20 +U 11 1 6999BF33 +P 10600 2500 +F 0 "U20" H 10650 2600 30 0000 C CNN +F 1 "PORT" H 10600 2500 30 0000 C CNN +F 2 "" H 10600 2500 60 0000 C CNN +F 3 "" H 10600 2500 60 0000 C CNN + 11 10600 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U20 +U 12 1 6999BFC2 +P 2000 6900 +F 0 "U20" H 2050 7000 30 0000 C CNN +F 1 "PORT" H 2000 6900 30 0000 C CNN +F 2 "" H 2000 6900 60 0000 C CNN +F 3 "" H 2000 6900 60 0000 C CNN + 12 2000 6900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U20 +U 13 1 6999C04D +P 10600 3450 +F 0 "U20" H 10650 3550 30 0000 C CNN +F 1 "PORT" H 10600 3450 30 0000 C CNN +F 2 "" H 10600 3450 60 0000 C CNN +F 3 "" H 10600 3450 60 0000 C CNN + 13 10600 3450 + -1 0 0 1 +$EndComp +$Comp +L PORT U20 +U 14 1 6999C0D2 +P 10600 3250 +F 0 "U20" H 10650 3350 30 0000 C CNN +F 1 "PORT" H 10600 3250 30 0000 C CNN +F 2 "" H 10600 3250 60 0000 C CNN +F 3 "" H 10600 3250 60 0000 C CNN + 14 10600 3250 + -1 0 0 1 +$EndComp +Wire Wire Line + 3150 1900 3250 1900 +Connection ~ 3250 1900 +Connection ~ 8650 5500 +Text GLabel 2400 6900 2 60 Input ~ 0 +GND +Wire Wire Line + 2250 6900 2400 6900 +Text GLabel 10850 1300 2 60 Input ~ 0 +GND +Text GLabel 10700 1700 2 60 Input ~ 0 +GND +Text GLabel 10750 2300 2 60 Input ~ 0 +GND +Text GLabel 10750 2700 2 60 Input ~ 0 +GND +Text GLabel 10750 3700 2 60 Input ~ 0 +GND +Text GLabel 10750 4250 2 60 Input ~ 0 +GND +Text GLabel 10750 4700 2 60 Input ~ 0 +GND +Text GLabel 10750 5300 2 60 Input ~ 0 +GND +Text GLabel 10750 5750 2 60 Input ~ 0 +GND +Wire Wire Line + 1650 5150 1100 5150 +Wire Wire Line + 950 1050 3550 1050 +$Comp +L PORT U20 +U 15 1 6999F9E9 +P 10600 5400 +F 0 "U20" H 10650 5500 30 0000 C CNN +F 1 "PORT" H 10600 5400 30 0000 C CNN +F 2 "" H 10600 5400 60 0000 C CNN +F 3 "" H 10600 5400 60 0000 C CNN + 15 10600 5400 + -1 0 0 1 +$EndComp +$Comp +L PORT U20 +U 16 1 6999FB0C +P 10600 5600 +F 0 "U20" H 10650 5700 30 0000 C CNN +F 1 "PORT" H 10600 5600 30 0000 C CNN +F 2 "" H 10600 5600 60 0000 C CNN +F 3 "" H 10600 5600 60 0000 C CNN + 16 10600 5600 + -1 0 0 1 +$EndComp +NoConn ~ 1050 7500 +Wire Wire Line + 10200 1200 10850 1200 +Wire Wire Line + 10850 1200 10850 1300 +Text GLabel 10750 3100 2 60 Input ~ 0 +GND +$Comp +L dac_bridge_1 U22 +U 1 1 699A260C +P 7700 1050 +F 0 "U22" H 7700 1050 60 0000 C CNN +F 1 "dac_bridge_1" H 7700 1200 60 0000 C CNN +F 2 "" H 7700 1050 60 0000 C CNN +F 3 "" H 7700 1050 60 0000 C CNN + 1 7700 1050 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U23 +U 1 1 699A2735 +P 7700 2400 +F 0 "U23" H 7700 2400 60 0000 C CNN +F 1 "dac_bridge_1" H 7700 2550 60 0000 C CNN +F 2 "" H 7700 2400 60 0000 C CNN +F 3 "" H 7700 2400 60 0000 C CNN + 1 7700 2400 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U24 +U 1 1 699A2816 +P 7700 3200 +F 0 "U24" H 7700 3200 60 0000 C CNN +F 1 "dac_bridge_1" H 7700 3350 60 0000 C CNN +F 2 "" H 7700 3200 60 0000 C CNN +F 3 "" H 7700 3200 60 0000 C CNN + 1 7700 3200 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U25 +U 1 1 699A28D2 +P 7700 4150 +F 0 "U25" H 7700 4150 60 0000 C CNN +F 1 "dac_bridge_1" H 7700 4300 60 0000 C CNN +F 2 "" H 7700 4150 60 0000 C CNN +F 3 "" H 7700 4150 60 0000 C CNN + 1 7700 4150 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U26 +U 1 1 699A298D +P 7700 5050 +F 0 "U26" H 7700 5050 60 0000 C CNN +F 1 "dac_bridge_1" H 7700 5200 60 0000 C CNN +F 2 "" H 7700 5050 60 0000 C CNN +F 3 "" H 7700 5050 60 0000 C CNN + 1 7700 5050 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U27 +U 1 1 699A2A4B +P 7850 6100 +F 0 "U27" H 7850 6100 60 0000 C CNN +F 1 "dac_bridge_1" H 7850 6250 60 0000 C CNN +F 2 "" H 7850 6100 60 0000 C CNN +F 3 "" H 7850 6100 60 0000 C CNN + 1 7850 6100 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U21 +U 1 1 699A2B08 +P 5200 6400 +F 0 "U21" H 5200 6400 60 0000 C CNN +F 1 "dac_bridge_1" H 5200 6550 60 0000 C CNN +F 2 "" H 5200 6400 60 0000 C CNN +F 3 "" H 5200 6400 60 0000 C CNN + 1 5200 6400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 1100 7100 1100 +Wire Wire Line + 7100 1100 7100 1000 +Wire Wire Line + 8250 1000 8250 1100 +Wire Wire Line + 8250 1100 8650 1100 +Wire Wire Line + 5050 2500 7100 2500 +Wire Wire Line + 7100 2500 7100 2350 +Wire Wire Line + 8250 2350 8250 2500 +Wire Wire Line + 8250 2500 8850 2500 +Wire Wire Line + 5050 3350 7100 3350 +Wire Wire Line + 7100 3350 7100 3150 +Wire Wire Line + 8250 3150 8250 3350 +Wire Wire Line + 8250 3350 8650 3350 +Wire Wire Line + 5100 4250 7100 4250 +Wire Wire Line + 7100 4250 7100 4100 +Wire Wire Line + 8250 4100 8250 4250 +Wire Wire Line + 8250 4250 8700 4250 +Wire Wire Line + 3650 5150 7100 5150 +Wire Wire Line + 7100 5150 7100 5000 +Wire Wire Line + 8250 5000 8250 5150 +Wire Wire Line + 8250 5150 8950 5150 +Wire Wire Line + 5750 6350 9050 6350 +Wire Wire Line + 8650 5500 8400 5500 +Wire Wire Line + 8400 5500 8400 6050 +Wire Wire Line + 8200 5500 8200 5850 +Wire Wire Line + 8200 5850 7250 5850 +Wire Wire Line + 7250 5850 7250 6050 +Wire Wire Line + 2600 6350 4600 6350 +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141.sub b/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141.sub new file mode 100644 index 000000000..e5b5394b0 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141.sub @@ -0,0 +1,127 @@ +* Subcircuit 74141 +.subckt 74141 net-_q1-pad1_ net-_q2-pad3_ net-_u20-pad3_ net-_u1-pad1_ ? net-_u2-pad2_ net-_u1-pad2_ net-_q8-pad3_ net-_q7-pad1_ net-_q3-pad1_ net-_q4-pad3_ gnd net-_q6-pad3_ net-_q5-pad1_ net-_q9-pad1_ net-_q10-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\74141\74141.cir +.include 3_and.sub +.include 5_and.sub +.include NPN.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q1-pad3_ net-_q10-pad2_ net-_q2-pad3_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad2_ net-_q3-pad3_ Q2N2222 +q4 net-_q3-pad3_ net-_q10-pad2_ net-_q4-pad3_ Q2N2222 +q5 net-_q5-pad1_ net-_q1-pad2_ net-_q5-pad3_ Q2N2222 +q6 net-_q5-pad3_ net-_q10-pad2_ net-_q6-pad3_ Q2N2222 +q7 net-_q7-pad1_ net-_q1-pad2_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q10-pad2_ net-_q8-pad3_ Q2N2222 +q9 net-_q9-pad1_ net-_q1-pad2_ net-_q10-pad1_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +* u10 gnd net-_q1-pad1_ zener +* u11 gnd net-_q2-pad3_ zener +* u12 gnd net-_q3-pad1_ zener +* u13 gnd net-_q4-pad3_ zener +* u14 gnd net-_q5-pad1_ zener +* u15 gnd net-_q6-pad3_ zener +* u16 gnd net-_q7-pad1_ zener +* u17 gnd net-_q8-pad3_ zener +* u18 gnd net-_q9-pad1_ zener +* u19 gnd net-_q10-pad3_ zener +x4 net-_u22-pad1_ net-_u23-pad1_ net-_u24-pad1_ net-_u25-pad1_ net-_u4-pad3_ net-_u27-pad1_ 5_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u4 net-_u1-pad3_ net-_u2-pad3_ net-_u4-pad3_ d_nor +* u6 net-_u1-pad1_ net-_u4-pad3_ net-_u22-pad1_ d_nand +* u3 net-_u20-pad3_ net-_u21-pad1_ d_inverter +* u5 net-_u21-pad1_ net-_u26-pad1_ d_inverter +x3 net-_u23-pad1_ net-_u4-pad3_ net-_u2-pad2_ net-_u9-pad1_ 3_and +x2 net-_u4-pad3_ net-_u1-pad2_ net-_u23-pad1_ net-_u8-pad1_ 3_and +x1 net-_u1-pad2_ net-_u4-pad3_ net-_u2-pad2_ net-_u7-pad1_ 3_and +* u7 net-_u7-pad1_ net-_u23-pad1_ d_inverter +* u8 net-_u8-pad1_ net-_u24-pad1_ d_inverter +* u9 net-_u9-pad1_ net-_u25-pad1_ d_inverter +* u22 net-_u22-pad1_ net-_q1-pad3_ dac_bridge_1 +* u23 net-_u23-pad1_ net-_q3-pad3_ dac_bridge_1 +* u24 net-_u24-pad1_ net-_q5-pad3_ dac_bridge_1 +* u25 net-_u25-pad1_ net-_q7-pad3_ dac_bridge_1 +* u26 net-_u26-pad1_ net-_q1-pad2_ dac_bridge_1 +* u27 net-_u27-pad1_ net-_q10-pad1_ dac_bridge_1 +* u21 net-_u21-pad1_ net-_q10-pad2_ dac_bridge_1 +a1 gnd net-_q1-pad1_ u10 +a2 gnd net-_q2-pad3_ u11 +a3 gnd net-_q3-pad1_ u12 +a4 gnd net-_q4-pad3_ u13 +a5 gnd net-_q5-pad1_ u14 +a6 gnd net-_q6-pad3_ u15 +a7 gnd net-_q7-pad1_ u16 +a8 gnd net-_q8-pad3_ u17 +a9 gnd net-_q9-pad1_ u18 +a10 gnd net-_q10-pad3_ u19 +a11 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1 +a12 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a13 [net-_u1-pad3_ net-_u2-pad3_ ] net-_u4-pad3_ u4 +a14 [net-_u1-pad1_ net-_u4-pad3_ ] net-_u22-pad1_ u6 +a15 net-_u20-pad3_ net-_u21-pad1_ u3 +a16 net-_u21-pad1_ net-_u26-pad1_ u5 +a17 net-_u7-pad1_ net-_u23-pad1_ u7 +a18 net-_u8-pad1_ net-_u24-pad1_ u8 +a19 net-_u9-pad1_ net-_u25-pad1_ u9 +a20 [net-_u22-pad1_ ] [net-_q1-pad3_ ] u22 +a21 [net-_u23-pad1_ ] [net-_q3-pad3_ ] u23 +a22 [net-_u24-pad1_ ] [net-_q5-pad3_ ] u24 +a23 [net-_u25-pad1_ ] [net-_q7-pad3_ ] u25 +a24 [net-_u26-pad1_ ] [net-_q1-pad2_ ] u26 +a25 [net-_u27-pad1_ ] [net-_q10-pad1_ ] u27 +a26 [net-_u21-pad1_ ] [net-_q10-pad2_ ] u21 +* Schematic Name: zener, NgSpice Name: zener +.model u10 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u11 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u12 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u13 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u14 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u15 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u16 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u17 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u18 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u19 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u23 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends 74141 \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141_Previous_Values.xml new file mode 100644 index 000000000..415c2888c --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/74141_Previous_Values.xml @@ -0,0 +1 @@ +zenerzenerzenerzenerzenerzenerzenerzenerzenerzenerd_andd_andd_nord_nandd_inverterd_inverterd_inverterd_inverterd_inverterdac_bridgedac_bridgedac_bridgedac_bridgedac_bridgedac_bridgedac_bridgeC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/NPN.lib b/FOSSEE/eSim/library/SubcircuitLibrary/74141/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74141/analysis b/FOSSEE/eSim/library/SubcircuitLibrary/74141/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74141/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and.cir b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and.pro b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and.sch b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and.sub b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165-cache.lib new file mode 100644 index 000000000..69fde18c4 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165-cache.lib @@ -0,0 +1,125 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165.cir b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165.cir new file mode 100644 index 000000000..b9cbbdc68 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165.cir @@ -0,0 +1,69 @@ +* C:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\74HCT165\74HCT165.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/22/26 16:11:17 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad4_ Net-_U12-Pad5_ ? d_dff +U9 Net-_U14-Pad2_ Net-_U10-Pad2_ Net-_U10-Pad1_ d_nand +U11 Net-_U10-Pad1_ Net-_U11-Pad2_ d_inverter +U14 Net-_U1-Pad11_ Net-_U14-Pad2_ d_buffer +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nand +U13 Net-_U10-Pad3_ Net-_U12-Pad4_ d_inverter +U18 Net-_U12-Pad5_ Net-_U12-Pad2_ Net-_U17-Pad2_ Net-_U18-Pad4_ Net-_U18-Pad5_ ? d_dff +U15 Net-_U15-Pad1_ Net-_U10-Pad2_ Net-_U15-Pad3_ d_nand +U17 Net-_U15-Pad3_ Net-_U17-Pad2_ d_inverter +U20 Net-_U1-Pad12_ Net-_U15-Pad1_ d_buffer +U16 Net-_U15-Pad3_ Net-_U10-Pad2_ Net-_U16-Pad3_ d_nand +U19 Net-_U16-Pad3_ Net-_U18-Pad4_ d_inverter +U24 Net-_U18-Pad5_ Net-_U12-Pad2_ Net-_U23-Pad2_ Net-_U24-Pad4_ Net-_U24-Pad5_ ? d_dff +U21 Net-_U21-Pad1_ Net-_U10-Pad2_ Net-_U21-Pad3_ d_nand +U23 Net-_U21-Pad3_ Net-_U23-Pad2_ d_inverter +U26 Net-_U1-Pad13_ Net-_U21-Pad1_ d_buffer +U22 Net-_U21-Pad3_ Net-_U10-Pad2_ Net-_U22-Pad3_ d_nand +U25 Net-_U22-Pad3_ Net-_U24-Pad4_ d_inverter +U30 Net-_U24-Pad5_ Net-_U12-Pad2_ Net-_U29-Pad2_ Net-_U30-Pad4_ Net-_U30-Pad5_ ? d_dff +U27 Net-_U27-Pad1_ Net-_U10-Pad2_ Net-_U27-Pad3_ d_nand +U29 Net-_U27-Pad3_ Net-_U29-Pad2_ d_inverter +U32 Net-_U1-Pad14_ Net-_U27-Pad1_ d_buffer +U28 Net-_U27-Pad3_ Net-_U10-Pad2_ Net-_U28-Pad3_ d_nand +U31 Net-_U28-Pad3_ Net-_U30-Pad4_ d_inverter +U36 Net-_U30-Pad5_ Net-_U12-Pad2_ Net-_U35-Pad2_ Net-_U36-Pad4_ Net-_U36-Pad5_ ? d_dff +U33 Net-_U33-Pad1_ Net-_U10-Pad2_ Net-_U33-Pad3_ d_nand +U35 Net-_U33-Pad3_ Net-_U35-Pad2_ d_inverter +U38 Net-_U1-Pad3_ Net-_U33-Pad1_ d_buffer +U34 Net-_U33-Pad3_ Net-_U10-Pad2_ Net-_U34-Pad3_ d_nand +U37 Net-_U34-Pad3_ Net-_U36-Pad4_ d_inverter +U42 Net-_U36-Pad5_ Net-_U12-Pad2_ Net-_U41-Pad2_ Net-_U42-Pad4_ Net-_U42-Pad5_ ? d_dff +U39 Net-_U39-Pad1_ Net-_U10-Pad2_ Net-_U39-Pad3_ d_nand +U41 Net-_U39-Pad3_ Net-_U41-Pad2_ d_inverter +U44 Net-_U1-Pad4_ Net-_U39-Pad1_ d_buffer +U40 Net-_U39-Pad3_ Net-_U10-Pad2_ Net-_U40-Pad3_ d_nand +U43 Net-_U40-Pad3_ Net-_U42-Pad4_ d_inverter +U48 Net-_U42-Pad5_ Net-_U12-Pad2_ Net-_U47-Pad2_ Net-_U48-Pad4_ Net-_U48-Pad5_ ? d_dff +U45 Net-_U45-Pad1_ Net-_U10-Pad2_ Net-_U45-Pad3_ d_nand +U47 Net-_U45-Pad3_ Net-_U47-Pad2_ d_inverter +U50 Net-_U1-Pad5_ Net-_U45-Pad1_ d_buffer +U46 Net-_U45-Pad3_ Net-_U10-Pad2_ Net-_U46-Pad3_ d_nand +U49 Net-_U46-Pad3_ Net-_U48-Pad4_ d_inverter +U54 Net-_U48-Pad5_ Net-_U12-Pad2_ Net-_U53-Pad2_ Net-_U54-Pad4_ Net-_U54-Pad5_ Net-_U54-Pad6_ d_dff +U51 Net-_U51-Pad1_ Net-_U10-Pad2_ Net-_U51-Pad3_ d_nand +U53 Net-_U51-Pad3_ Net-_U53-Pad2_ d_inverter +U56 Net-_U1-Pad6_ Net-_U51-Pad1_ d_buffer +U52 Net-_U51-Pad3_ Net-_U10-Pad2_ Net-_U52-Pad3_ d_nand +U55 Net-_U52-Pad3_ Net-_U54-Pad4_ d_inverter +U57 Net-_U54-Pad5_ Net-_U1-Pad9_ d_buffer +U58 Net-_U54-Pad6_ Net-_U1-Pad7_ d_buffer +U6 Net-_U1-Pad10_ Net-_U6-Pad2_ d_inverter +U7 Net-_U6-Pad2_ Net-_U12-Pad1_ d_inverter +X1 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U8-Pad1_ 3_and +U8 Net-_U8-Pad1_ Net-_U12-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad15_ Net-_U4-Pad2_ d_inverter +U2 Net-_U1-Pad1_ Net-_U10-Pad2_ d_inverter +U5 Net-_U10-Pad2_ Net-_U5-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165.cir.out new file mode 100644 index 000000000..b88d71514 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165.cir.out @@ -0,0 +1,242 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\74hct165\74hct165.cir + +.include 3_and.sub +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad2_ net-_u12-pad4_ net-_u12-pad5_ ? d_dff +* u9 net-_u14-pad2_ net-_u10-pad2_ net-_u10-pad1_ d_nand +* u11 net-_u10-pad1_ net-_u11-pad2_ d_inverter +* u14 net-_u1-pad11_ net-_u14-pad2_ d_buffer +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u13 net-_u10-pad3_ net-_u12-pad4_ d_inverter +* u18 net-_u12-pad5_ net-_u12-pad2_ net-_u17-pad2_ net-_u18-pad4_ net-_u18-pad5_ ? d_dff +* u15 net-_u15-pad1_ net-_u10-pad2_ net-_u15-pad3_ d_nand +* u17 net-_u15-pad3_ net-_u17-pad2_ d_inverter +* u20 net-_u1-pad12_ net-_u15-pad1_ d_buffer +* u16 net-_u15-pad3_ net-_u10-pad2_ net-_u16-pad3_ d_nand +* u19 net-_u16-pad3_ net-_u18-pad4_ d_inverter +* u24 net-_u18-pad5_ net-_u12-pad2_ net-_u23-pad2_ net-_u24-pad4_ net-_u24-pad5_ ? d_dff +* u21 net-_u21-pad1_ net-_u10-pad2_ net-_u21-pad3_ d_nand +* u23 net-_u21-pad3_ net-_u23-pad2_ d_inverter +* u26 net-_u1-pad13_ net-_u21-pad1_ d_buffer +* u22 net-_u21-pad3_ net-_u10-pad2_ net-_u22-pad3_ d_nand +* u25 net-_u22-pad3_ net-_u24-pad4_ d_inverter +* u30 net-_u24-pad5_ net-_u12-pad2_ net-_u29-pad2_ net-_u30-pad4_ net-_u30-pad5_ ? d_dff +* u27 net-_u27-pad1_ net-_u10-pad2_ net-_u27-pad3_ d_nand +* u29 net-_u27-pad3_ net-_u29-pad2_ d_inverter +* u32 net-_u1-pad14_ net-_u27-pad1_ d_buffer +* u28 net-_u27-pad3_ net-_u10-pad2_ net-_u28-pad3_ d_nand +* u31 net-_u28-pad3_ net-_u30-pad4_ d_inverter +* u36 net-_u30-pad5_ net-_u12-pad2_ net-_u35-pad2_ net-_u36-pad4_ net-_u36-pad5_ ? d_dff +* u33 net-_u33-pad1_ net-_u10-pad2_ net-_u33-pad3_ d_nand +* u35 net-_u33-pad3_ net-_u35-pad2_ d_inverter +* u38 net-_u1-pad3_ net-_u33-pad1_ d_buffer +* u34 net-_u33-pad3_ net-_u10-pad2_ net-_u34-pad3_ d_nand +* u37 net-_u34-pad3_ net-_u36-pad4_ d_inverter +* u42 net-_u36-pad5_ net-_u12-pad2_ net-_u41-pad2_ net-_u42-pad4_ net-_u42-pad5_ ? d_dff +* u39 net-_u39-pad1_ net-_u10-pad2_ net-_u39-pad3_ d_nand +* u41 net-_u39-pad3_ net-_u41-pad2_ d_inverter +* u44 net-_u1-pad4_ net-_u39-pad1_ d_buffer +* u40 net-_u39-pad3_ net-_u10-pad2_ net-_u40-pad3_ d_nand +* u43 net-_u40-pad3_ net-_u42-pad4_ d_inverter +* u48 net-_u42-pad5_ net-_u12-pad2_ net-_u47-pad2_ net-_u48-pad4_ net-_u48-pad5_ ? d_dff +* u45 net-_u45-pad1_ net-_u10-pad2_ net-_u45-pad3_ d_nand +* u47 net-_u45-pad3_ net-_u47-pad2_ d_inverter +* u50 net-_u1-pad5_ net-_u45-pad1_ d_buffer +* u46 net-_u45-pad3_ net-_u10-pad2_ net-_u46-pad3_ d_nand +* u49 net-_u46-pad3_ net-_u48-pad4_ d_inverter +* u54 net-_u48-pad5_ net-_u12-pad2_ net-_u53-pad2_ net-_u54-pad4_ net-_u54-pad5_ net-_u54-pad6_ d_dff +* u51 net-_u51-pad1_ net-_u10-pad2_ net-_u51-pad3_ d_nand +* u53 net-_u51-pad3_ net-_u53-pad2_ d_inverter +* u56 net-_u1-pad6_ net-_u51-pad1_ d_buffer +* u52 net-_u51-pad3_ net-_u10-pad2_ net-_u52-pad3_ d_nand +* u55 net-_u52-pad3_ net-_u54-pad4_ d_inverter +* u57 net-_u54-pad5_ net-_u1-pad9_ d_buffer +* u58 net-_u54-pad6_ net-_u1-pad7_ d_buffer +* u6 net-_u1-pad10_ net-_u6-pad2_ d_inverter +* u7 net-_u6-pad2_ net-_u12-pad1_ d_inverter +x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u8-pad1_ 3_and +* u8 net-_u8-pad1_ net-_u12-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad15_ net-_u4-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u10-pad2_ d_inverter +* u5 net-_u10-pad2_ net-_u5-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +a1 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad2_ net-_u12-pad4_ net-_u12-pad5_ ? u12 +a2 [net-_u14-pad2_ net-_u10-pad2_ ] net-_u10-pad1_ u9 +a3 net-_u10-pad1_ net-_u11-pad2_ u11 +a4 net-_u1-pad11_ net-_u14-pad2_ u14 +a5 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a6 net-_u10-pad3_ net-_u12-pad4_ u13 +a7 net-_u12-pad5_ net-_u12-pad2_ net-_u17-pad2_ net-_u18-pad4_ net-_u18-pad5_ ? u18 +a8 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u15-pad3_ u15 +a9 net-_u15-pad3_ net-_u17-pad2_ u17 +a10 net-_u1-pad12_ net-_u15-pad1_ u20 +a11 [net-_u15-pad3_ net-_u10-pad2_ ] net-_u16-pad3_ u16 +a12 net-_u16-pad3_ net-_u18-pad4_ u19 +a13 net-_u18-pad5_ net-_u12-pad2_ net-_u23-pad2_ net-_u24-pad4_ net-_u24-pad5_ ? u24 +a14 [net-_u21-pad1_ net-_u10-pad2_ ] net-_u21-pad3_ u21 +a15 net-_u21-pad3_ net-_u23-pad2_ u23 +a16 net-_u1-pad13_ net-_u21-pad1_ u26 +a17 [net-_u21-pad3_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a18 net-_u22-pad3_ net-_u24-pad4_ u25 +a19 net-_u24-pad5_ net-_u12-pad2_ net-_u29-pad2_ net-_u30-pad4_ net-_u30-pad5_ ? u30 +a20 [net-_u27-pad1_ net-_u10-pad2_ ] net-_u27-pad3_ u27 +a21 net-_u27-pad3_ net-_u29-pad2_ u29 +a22 net-_u1-pad14_ net-_u27-pad1_ u32 +a23 [net-_u27-pad3_ net-_u10-pad2_ ] net-_u28-pad3_ u28 +a24 net-_u28-pad3_ net-_u30-pad4_ u31 +a25 net-_u30-pad5_ net-_u12-pad2_ net-_u35-pad2_ net-_u36-pad4_ net-_u36-pad5_ ? u36 +a26 [net-_u33-pad1_ net-_u10-pad2_ ] net-_u33-pad3_ u33 +a27 net-_u33-pad3_ net-_u35-pad2_ u35 +a28 net-_u1-pad3_ net-_u33-pad1_ u38 +a29 [net-_u33-pad3_ net-_u10-pad2_ ] net-_u34-pad3_ u34 +a30 net-_u34-pad3_ net-_u36-pad4_ u37 +a31 net-_u36-pad5_ net-_u12-pad2_ net-_u41-pad2_ net-_u42-pad4_ net-_u42-pad5_ ? u42 +a32 [net-_u39-pad1_ net-_u10-pad2_ ] net-_u39-pad3_ u39 +a33 net-_u39-pad3_ net-_u41-pad2_ u41 +a34 net-_u1-pad4_ net-_u39-pad1_ u44 +a35 [net-_u39-pad3_ net-_u10-pad2_ ] net-_u40-pad3_ u40 +a36 net-_u40-pad3_ net-_u42-pad4_ u43 +a37 net-_u42-pad5_ net-_u12-pad2_ net-_u47-pad2_ net-_u48-pad4_ net-_u48-pad5_ ? u48 +a38 [net-_u45-pad1_ net-_u10-pad2_ ] net-_u45-pad3_ u45 +a39 net-_u45-pad3_ net-_u47-pad2_ u47 +a40 net-_u1-pad5_ net-_u45-pad1_ u50 +a41 [net-_u45-pad3_ net-_u10-pad2_ ] net-_u46-pad3_ u46 +a42 net-_u46-pad3_ net-_u48-pad4_ u49 +a43 net-_u48-pad5_ net-_u12-pad2_ net-_u53-pad2_ net-_u54-pad4_ net-_u54-pad5_ net-_u54-pad6_ u54 +a44 [net-_u51-pad1_ net-_u10-pad2_ ] net-_u51-pad3_ u51 +a45 net-_u51-pad3_ net-_u53-pad2_ u53 +a46 net-_u1-pad6_ net-_u51-pad1_ u56 +a47 [net-_u51-pad3_ net-_u10-pad2_ ] net-_u52-pad3_ u52 +a48 net-_u52-pad3_ net-_u54-pad4_ u55 +a49 net-_u54-pad5_ net-_u1-pad9_ u57 +a50 net-_u54-pad6_ net-_u1-pad7_ u58 +a51 net-_u1-pad10_ net-_u6-pad2_ u6 +a52 net-_u6-pad2_ net-_u12-pad1_ u7 +a53 net-_u8-pad1_ net-_u12-pad2_ u8 +a54 net-_u1-pad2_ net-_u3-pad2_ u3 +a55 net-_u1-pad15_ net-_u4-pad2_ u4 +a56 net-_u1-pad1_ net-_u10-pad2_ u2 +a57 net-_u10-pad2_ net-_u5-pad2_ u5 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u12 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u14 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u18 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u20 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u24 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u32 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u36 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u38 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u42 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u44 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u48 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u45 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u50 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u54 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u53 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u56 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u52 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u57 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u58 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165.pro b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165.sch b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165.sch new file mode 100644 index 000000000..0115af1ad --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165.sch @@ -0,0 +1,1213 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74HCT165-cache +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_dff U12 +U 1 1 699A817A +P 9850 11650 +F 0 "U12" H 9850 11650 60 0000 C CNN +F 1 "d_dff" H 9850 11800 60 0000 C CNN +F 2 "" H 9850 11650 60 0000 C CNN +F 3 "" H 9850 11650 60 0000 C CNN + 1 9850 11650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U9 +U 1 1 699A81BF +P 9800 9750 +F 0 "U9" H 9800 9750 60 0000 C CNN +F 1 "d_nand" H 9850 9850 60 0000 C CNN +F 2 "" H 9800 9750 60 0000 C CNN +F 3 "" H 9800 9750 60 0000 C CNN + 1 9800 9750 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U11 +U 1 1 699A8227 +P 9850 10650 +F 0 "U11" H 9850 10550 60 0000 C CNN +F 1 "d_inverter" H 9850 10800 60 0000 C CNN +F 2 "" H 9900 10600 60 0000 C CNN +F 3 "" H 9900 10600 60 0000 C CNN + 1 9850 10650 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U14 +U 1 1 699A8331 +P 9900 8350 +F 0 "U14" H 9900 8300 60 0000 C CNN +F 1 "d_buffer" H 9900 8400 60 0000 C CNN +F 2 "" H 9900 8350 60 0000 C CNN +F 3 "" H 9900 8350 60 0000 C CNN + 1 9900 8350 + 0 1 1 0 +$EndComp +$Comp +L d_nand U10 +U 1 1 699A872D +P 9800 13600 +F 0 "U10" H 9800 13600 60 0000 C CNN +F 1 "d_nand" H 9850 13700 60 0000 C CNN +F 2 "" H 9800 13600 60 0000 C CNN +F 3 "" H 9800 13600 60 0000 C CNN + 1 9800 13600 + 0 1 -1 0 +$EndComp +$Comp +L d_inverter U13 +U 1 1 699A8733 +P 9850 12700 +F 0 "U13" H 9850 12600 60 0000 C CNN +F 1 "d_inverter" H 9850 12850 60 0000 C CNN +F 2 "" H 9900 12650 60 0000 C CNN +F 3 "" H 9900 12650 60 0000 C CNN + 1 9850 12700 + 0 1 -1 0 +$EndComp +Wire Wire Line + 9850 10950 9850 11000 +Wire Wire Line + 9850 10200 9850 10350 +Wire Wire Line + 9900 9000 9900 9300 +Wire Wire Line + 9850 13150 9850 13000 +Wire Wire Line + 9850 12250 9850 12400 +Wire Wire Line + 9900 14050 9900 14150 +Wire Wire Line + 9900 14150 10650 14150 +Wire Wire Line + 10650 14150 10650 10300 +Wire Wire Line + 10650 10300 9850 10300 +Connection ~ 9850 10300 +$Comp +L d_dff U18 +U 1 1 699AB2B9 +P 11750 11650 +F 0 "U18" H 11750 11650 60 0000 C CNN +F 1 "d_dff" H 11750 11800 60 0000 C CNN +F 2 "" H 11750 11650 60 0000 C CNN +F 3 "" H 11750 11650 60 0000 C CNN + 1 11750 11650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U15 +U 1 1 699AB2BF +P 11700 9750 +F 0 "U15" H 11700 9750 60 0000 C CNN +F 1 "d_nand" H 11750 9850 60 0000 C CNN +F 2 "" H 11700 9750 60 0000 C CNN +F 3 "" H 11700 9750 60 0000 C CNN + 1 11700 9750 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U17 +U 1 1 699AB2C5 +P 11750 10650 +F 0 "U17" H 11750 10550 60 0000 C CNN +F 1 "d_inverter" H 11750 10800 60 0000 C CNN +F 2 "" H 11800 10600 60 0000 C CNN +F 3 "" H 11800 10600 60 0000 C CNN + 1 11750 10650 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U20 +U 1 1 699AB2CB +P 11800 8350 +F 0 "U20" H 11800 8300 60 0000 C CNN +F 1 "d_buffer" H 11800 8400 60 0000 C CNN +F 2 "" H 11800 8350 60 0000 C CNN +F 3 "" H 11800 8350 60 0000 C CNN + 1 11800 8350 + 0 1 1 0 +$EndComp +$Comp +L d_nand U16 +U 1 1 699AB2D1 +P 11700 13600 +F 0 "U16" H 11700 13600 60 0000 C CNN +F 1 "d_nand" H 11750 13700 60 0000 C CNN +F 2 "" H 11700 13600 60 0000 C CNN +F 3 "" H 11700 13600 60 0000 C CNN + 1 11700 13600 + 0 1 -1 0 +$EndComp +$Comp +L d_inverter U19 +U 1 1 699AB2D7 +P 11750 12700 +F 0 "U19" H 11750 12600 60 0000 C CNN +F 1 "d_inverter" H 11750 12850 60 0000 C CNN +F 2 "" H 11800 12650 60 0000 C CNN +F 3 "" H 11800 12650 60 0000 C CNN + 1 11750 12700 + 0 1 -1 0 +$EndComp +Wire Wire Line + 11750 10950 11750 11000 +Wire Wire Line + 11750 10200 11750 10350 +Wire Wire Line + 11800 9000 11800 9300 +Wire Wire Line + 11750 13150 11750 13000 +Wire Wire Line + 11750 12250 11750 12400 +Wire Wire Line + 11800 14050 11800 14150 +Wire Wire Line + 12300 11300 13800 11300 +Wire Wire Line + 11800 14150 12550 14150 +Wire Wire Line + 12550 14150 12550 10300 +Wire Wire Line + 12550 10300 11750 10300 +Connection ~ 11750 10300 +Wire Wire Line + 10400 11300 11200 11300 +Wire Wire Line + 11000 14350 11000 11950 +Wire Wire Line + 11000 11950 11200 11950 +Connection ~ 11000 14350 +Wire Wire Line + 9800 9300 9800 9150 +Connection ~ 9800 9150 +Wire Wire Line + 11700 9300 11700 9150 +Connection ~ 11700 9150 +Wire Wire Line + 9900 7850 9900 7700 +Wire Wire Line + 11800 7850 11800 7700 +$Comp +L d_dff U24 +U 1 1 699ACC2B +P 14350 11650 +F 0 "U24" H 14350 11650 60 0000 C CNN +F 1 "d_dff" H 14350 11800 60 0000 C CNN +F 2 "" H 14350 11650 60 0000 C CNN +F 3 "" H 14350 11650 60 0000 C CNN + 1 14350 11650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U21 +U 1 1 699ACC31 +P 14300 9750 +F 0 "U21" H 14300 9750 60 0000 C CNN +F 1 "d_nand" H 14350 9850 60 0000 C CNN +F 2 "" H 14300 9750 60 0000 C CNN +F 3 "" H 14300 9750 60 0000 C CNN + 1 14300 9750 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U23 +U 1 1 699ACC37 +P 14350 10650 +F 0 "U23" H 14350 10550 60 0000 C CNN +F 1 "d_inverter" H 14350 10800 60 0000 C CNN +F 2 "" H 14400 10600 60 0000 C CNN +F 3 "" H 14400 10600 60 0000 C CNN + 1 14350 10650 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U26 +U 1 1 699ACC3D +P 14400 8350 +F 0 "U26" H 14400 8300 60 0000 C CNN +F 1 "d_buffer" H 14400 8400 60 0000 C CNN +F 2 "" H 14400 8350 60 0000 C CNN +F 3 "" H 14400 8350 60 0000 C CNN + 1 14400 8350 + 0 1 1 0 +$EndComp +$Comp +L d_nand U22 +U 1 1 699ACC43 +P 14300 13600 +F 0 "U22" H 14300 13600 60 0000 C CNN +F 1 "d_nand" H 14350 13700 60 0000 C CNN +F 2 "" H 14300 13600 60 0000 C CNN +F 3 "" H 14300 13600 60 0000 C CNN + 1 14300 13600 + 0 1 -1 0 +$EndComp +$Comp +L d_inverter U25 +U 1 1 699ACC49 +P 14350 12700 +F 0 "U25" H 14350 12600 60 0000 C CNN +F 1 "d_inverter" H 14350 12850 60 0000 C CNN +F 2 "" H 14400 12650 60 0000 C CNN +F 3 "" H 14400 12650 60 0000 C CNN + 1 14350 12700 + 0 1 -1 0 +$EndComp +Wire Wire Line + 14350 10950 14350 11000 +Wire Wire Line + 14350 10200 14350 10350 +Wire Wire Line + 14400 9000 14400 9300 +Wire Wire Line + 14350 13150 14350 13000 +Wire Wire Line + 14350 12250 14350 12400 +Wire Wire Line + 14400 14050 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16300 8400 60 0000 C CNN +F 2 "" H 16300 8350 60 0000 C CNN +F 3 "" H 16300 8350 60 0000 C CNN + 1 16300 8350 + 0 1 1 0 +$EndComp +$Comp +L d_nand U28 +U 1 1 699ACC71 +P 16200 13600 +F 0 "U28" H 16200 13600 60 0000 C CNN +F 1 "d_nand" H 16250 13700 60 0000 C CNN +F 2 "" H 16200 13600 60 0000 C CNN +F 3 "" H 16200 13600 60 0000 C CNN + 1 16200 13600 + 0 1 -1 0 +$EndComp +$Comp +L d_inverter U31 +U 1 1 699ACC77 +P 16250 12700 +F 0 "U31" H 16250 12600 60 0000 C CNN +F 1 "d_inverter" H 16250 12850 60 0000 C CNN +F 2 "" H 16300 12650 60 0000 C CNN +F 3 "" H 16300 12650 60 0000 C CNN + 1 16250 12700 + 0 1 -1 0 +$EndComp +Wire Wire Line + 16250 10950 16250 11000 +Wire Wire Line + 16250 10200 16250 10350 +Wire Wire Line + 16300 9000 16300 9300 +Wire Wire Line + 16250 13150 16250 13000 +Wire Wire Line + 16250 12250 16250 12400 +Wire Wire Line + 16300 14050 16300 14150 +Wire Wire Line + 16800 11300 18300 11300 +Wire Wire Line + 16300 14150 17050 14150 +Wire Wire Line + 17050 14150 17050 10300 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1 0 +$EndComp +$Comp +L d_inverter U35 +U 1 1 699AE147 +P 18850 10650 +F 0 "U35" H 18850 10550 60 0000 C CNN +F 1 "d_inverter" H 18850 10800 60 0000 C CNN +F 2 "" H 18900 10600 60 0000 C CNN +F 3 "" H 18900 10600 60 0000 C CNN + 1 18850 10650 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U38 +U 1 1 699AE14D +P 18900 8350 +F 0 "U38" H 18900 8300 60 0000 C CNN +F 1 "d_buffer" H 18900 8400 60 0000 C CNN +F 2 "" H 18900 8350 60 0000 C CNN +F 3 "" H 18900 8350 60 0000 C CNN + 1 18900 8350 + 0 1 1 0 +$EndComp +$Comp +L d_nand U34 +U 1 1 699AE153 +P 18800 13600 +F 0 "U34" H 18800 13600 60 0000 C CNN +F 1 "d_nand" H 18850 13700 60 0000 C CNN +F 2 "" H 18800 13600 60 0000 C CNN +F 3 "" H 18800 13600 60 0000 C CNN + 1 18800 13600 + 0 1 -1 0 +$EndComp +$Comp +L d_inverter U37 +U 1 1 699AE159 +P 18850 12700 +F 0 "U37" H 18850 12600 60 0000 C CNN +F 1 "d_inverter" H 18850 12850 60 0000 C CNN +F 2 "" H 18900 12650 60 0000 C CNN +F 3 "" H 18900 12650 60 0000 C CNN + 1 18850 12700 + 0 1 -1 0 +$EndComp +Wire Wire Line + 18850 10950 18850 11000 +Wire Wire Line + 18850 10200 18850 10350 +Wire Wire Line + 18900 9000 18900 9300 +Wire Wire Line + 18850 13150 18850 13000 +Wire Wire Line + 18850 12250 18850 12400 +Wire Wire Line + 18900 14050 18900 14150 +Wire Wire Line + 18900 14150 19650 14150 +Wire Wire Line + 19650 14150 19650 10300 +Wire Wire Line + 19650 10300 18850 10300 +Connection ~ 18850 10300 +$Comp +L d_dff U42 +U 1 1 699AE169 +P 20750 11650 +F 0 "U42" H 20750 11650 60 0000 C CNN +F 1 "d_dff" H 20750 11800 60 0000 C CNN +F 2 "" H 20750 11650 60 0000 C CNN +F 3 "" H 20750 11650 60 0000 C CNN + 1 20750 11650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U39 +U 1 1 699AE16F +P 20700 9750 +F 0 "U39" H 20700 9750 60 0000 C CNN +F 1 "d_nand" H 20750 9850 60 0000 C CNN +F 2 "" H 20700 9750 60 0000 C CNN +F 3 "" H 20700 9750 60 0000 C CNN + 1 20700 9750 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U41 +U 1 1 699AE175 +P 20750 10650 +F 0 "U41" H 20750 10550 60 0000 C CNN +F 1 "d_inverter" H 20750 10800 60 0000 C CNN +F 2 "" H 20800 10600 60 0000 C CNN +F 3 "" H 20800 10600 60 0000 C CNN + 1 20750 10650 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U44 +U 1 1 699AE17B +P 20800 8350 +F 0 "U44" H 20800 8300 60 0000 C CNN +F 1 "d_buffer" H 20800 8400 60 0000 C CNN +F 2 "" H 20800 8350 60 0000 C CNN +F 3 "" H 20800 8350 60 0000 C CNN + 1 20800 8350 + 0 1 1 0 +$EndComp +$Comp +L d_nand U40 +U 1 1 699AE181 +P 20700 13600 +F 0 "U40" H 20700 13600 60 0000 C CNN +F 1 "d_nand" H 20750 13700 60 0000 C CNN +F 2 "" H 20700 13600 60 0000 C CNN +F 3 "" H 20700 13600 60 0000 C CNN + 1 20700 13600 + 0 1 -1 0 +$EndComp +$Comp +L d_inverter U43 +U 1 1 699AE187 +P 20750 12700 +F 0 "U43" H 20750 12600 60 0000 C CNN +F 1 "d_inverter" H 20750 12850 60 0000 C CNN +F 2 "" H 20800 12650 60 0000 C CNN +F 3 "" H 20800 12650 60 0000 C CNN + 1 20750 12700 + 0 1 -1 0 +$EndComp +Wire Wire Line + 20750 10950 20750 11000 +Wire Wire Line + 20750 10200 20750 10350 +Wire Wire Line + 20800 9000 20800 9300 +Wire Wire Line + 20750 13150 20750 13000 +Wire Wire Line + 20750 12250 20750 12400 +Wire Wire Line + 20800 14050 20800 14150 +Wire Wire Line + 21300 11300 22800 11300 +Wire Wire Line + 20800 14150 21550 14150 +Wire Wire Line + 21550 14150 21550 10300 +Wire Wire Line + 21550 10300 20750 10300 +Connection ~ 20750 10300 +Wire Wire Line + 19400 11300 20200 11300 +Wire Wire Line + 20000 14350 20000 11950 +Wire Wire Line + 20000 11950 20200 11950 +Connection ~ 20000 14350 +Wire Wire Line + 18800 9300 18800 9150 +Connection ~ 18800 9150 +Wire Wire Line + 20700 9300 20700 9150 +Connection ~ 20700 9150 +Wire Wire Line + 18900 7850 18900 7700 +Wire Wire Line + 20800 7850 20800 7700 +$Comp +L d_dff U48 +U 1 1 699AE1A5 +P 23350 11650 +F 0 "U48" H 23350 11650 60 0000 C CNN +F 1 "d_dff" H 23350 11800 60 0000 C CNN +F 2 "" H 23350 11650 60 0000 C CNN +F 3 "" H 23350 11650 60 0000 C CNN + 1 23350 11650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U45 +U 1 1 699AE1AB +P 23300 9750 +F 0 "U45" H 23300 9750 60 0000 C CNN +F 1 "d_nand" H 23350 9850 60 0000 C CNN +F 2 "" H 23300 9750 60 0000 C CNN +F 3 "" H 23300 9750 60 0000 C CNN + 1 23300 9750 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U47 +U 1 1 699AE1B1 +P 23350 10650 +F 0 "U47" H 23350 10550 60 0000 C CNN +F 1 "d_inverter" H 23350 10800 60 0000 C CNN +F 2 "" H 23400 10600 60 0000 C CNN +F 3 "" H 23400 10600 60 0000 C CNN + 1 23350 10650 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U50 +U 1 1 699AE1B7 +P 23400 8350 +F 0 "U50" H 23400 8300 60 0000 C CNN +F 1 "d_buffer" H 23400 8400 60 0000 C CNN +F 2 "" H 23400 8350 60 0000 C CNN +F 3 "" H 23400 8350 60 0000 C CNN + 1 23400 8350 + 0 1 1 0 +$EndComp +$Comp +L d_nand U46 +U 1 1 699AE1BD +P 23300 13600 +F 0 "U46" H 23300 13600 60 0000 C CNN +F 1 "d_nand" H 23350 13700 60 0000 C CNN +F 2 "" H 23300 13600 60 0000 C CNN +F 3 "" H 23300 13600 60 0000 C CNN + 1 23300 13600 + 0 1 -1 0 +$EndComp +$Comp +L d_inverter U49 +U 1 1 699AE1C3 +P 23350 12700 +F 0 "U49" H 23350 12600 60 0000 C CNN +F 1 "d_inverter" H 23350 12850 60 0000 C CNN +F 2 "" H 23400 12650 60 0000 C CNN +F 3 "" H 23400 12650 60 0000 C CNN + 1 23350 12700 + 0 1 -1 0 +$EndComp +Wire Wire Line + 23350 10950 23350 11000 +Wire Wire Line + 23350 10200 23350 10350 +Wire Wire Line + 23400 9000 23400 9300 +Wire Wire Line + 23350 13150 23350 13000 +Wire Wire Line + 23350 12250 23350 12400 +Wire Wire Line + 23400 14050 23400 14150 +Wire Wire Line + 23400 14150 24150 14150 +Wire Wire Line + 24150 14150 24150 10300 +Wire Wire Line + 24150 10300 23350 10300 +Connection ~ 23350 10300 +$Comp +L d_dff U54 +U 1 1 699AE1D3 +P 25250 11650 +F 0 "U54" H 25250 11650 60 0000 C CNN +F 1 "d_dff" H 25250 11800 60 0000 C CNN +F 2 "" H 25250 11650 60 0000 C CNN +F 3 "" H 25250 11650 60 0000 C CNN + 1 25250 11650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U51 +U 1 1 699AE1D9 +P 25200 9750 +F 0 "U51" H 25200 9750 60 0000 C CNN +F 1 "d_nand" H 25250 9850 60 0000 C CNN +F 2 "" H 25200 9750 60 0000 C CNN +F 3 "" H 25200 9750 60 0000 C CNN + 1 25200 9750 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U53 +U 1 1 699AE1DF +P 25250 10650 +F 0 "U53" H 25250 10550 60 0000 C CNN +F 1 "d_inverter" H 25250 10800 60 0000 C CNN +F 2 "" H 25300 10600 60 0000 C CNN +F 3 "" H 25300 10600 60 0000 C CNN + 1 25250 10650 + 0 1 1 0 +$EndComp +$Comp +L d_buffer U56 +U 1 1 699AE1E5 +P 25300 8350 +F 0 "U56" H 25300 8300 60 0000 C CNN +F 1 "d_buffer" H 25300 8400 60 0000 C CNN +F 2 "" H 25300 8350 60 0000 C CNN +F 3 "" H 25300 8350 60 0000 C CNN + 1 25300 8350 + 0 1 1 0 +$EndComp +$Comp +L d_nand U52 +U 1 1 699AE1EB +P 25200 13600 +F 0 "U52" H 25200 13600 60 0000 C CNN +F 1 "d_nand" H 25250 13700 60 0000 C CNN +F 2 "" H 25200 13600 60 0000 C CNN +F 3 "" H 25200 13600 60 0000 C CNN + 1 25200 13600 + 0 1 -1 0 +$EndComp +$Comp +L d_inverter U55 +U 1 1 699AE1F1 +P 25250 12700 +F 0 "U55" H 25250 12600 60 0000 C CNN +F 1 "d_inverter" H 25250 12850 60 0000 C CNN +F 2 "" H 25300 12650 60 0000 C CNN +F 3 "" H 25300 12650 60 0000 C CNN + 1 25250 12700 + 0 1 -1 0 +$EndComp +Wire Wire Line + 25250 10950 25250 11000 +Wire Wire Line + 25250 10200 25250 10350 +Wire Wire Line + 25300 9000 25300 9300 +Wire Wire Line + 25250 13150 25250 13000 +Wire Wire Line + 25250 12250 25250 12400 +Wire Wire Line + 25300 14050 25300 14150 +Wire Wire Line + 25800 11300 26650 11300 +Wire Wire Line + 25300 14150 26050 14150 +Wire Wire Line + 26050 14150 26050 10300 +Wire Wire Line + 26050 10300 25250 10300 +Connection ~ 25250 10300 +Wire Wire Line + 23900 11300 24700 11300 +Wire Wire Line + 24500 14350 24500 11950 +Wire Wire Line + 24500 11950 24700 11950 +Wire Wire Line + 23300 9300 23300 9150 +Connection ~ 23300 9150 +Wire Wire Line + 25200 9300 25200 9150 +Wire Wire Line + 23400 7850 23400 7700 +Wire Wire Line + 25300 7850 25300 7700 +Wire Wire Line + 22800 11950 22350 11950 +Wire Wire Line + 22350 11950 22350 14350 +Connection ~ 22350 14350 +Wire Wire Line + 18300 11950 18000 11950 +Wire Wire Line + 18000 11950 18000 14350 +Connection ~ 18000 14350 +NoConn ~ 10400 11950 +NoConn ~ 12300 11950 +NoConn ~ 14900 11950 +NoConn ~ 16800 11950 +NoConn ~ 19400 11950 +NoConn ~ 21300 11950 +NoConn ~ 23900 11950 +Wire Wire Line + 25800 11950 26700 11950 +$Comp +L d_buffer U57 +U 1 1 699B0124 +P 27150 11300 +F 0 "U57" H 27150 11250 60 0000 C CNN +F 1 "d_buffer" H 27150 11350 60 0000 C CNN +F 2 "" H 27150 11300 60 0000 C CNN +F 3 "" H 27150 11300 60 0000 C CNN + 1 27150 11300 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U58 +U 1 1 699B033E +P 27200 11950 +F 0 "U58" H 27200 11900 60 0000 C CNN +F 1 "d_buffer" H 27200 12000 60 0000 C CNN +F 2 "" H 27200 11950 60 0000 C CNN +F 3 "" H 27200 11950 60 0000 C CNN + 1 27200 11950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8750 11950 9300 11950 +Wire Wire Line + 8950 11950 8950 14350 +Wire Wire Line + 8550 9150 8550 14500 +$Comp +L d_inverter U6 +U 1 1 699B1535 +P 7100 10550 +F 0 "U6" H 7100 10450 60 0000 C CNN +F 1 "d_inverter" H 7100 10700 60 0000 C CNN +F 2 "" H 7150 10500 60 0000 C CNN +F 3 "" H 7150 10500 60 0000 C CNN + 1 7100 10550 + 1 0 0 1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 699B171A +P 8000 10550 +F 0 "U7" H 8000 10450 60 0000 C CNN +F 1 "d_inverter" H 8000 10700 60 0000 C CNN +F 2 "" H 8050 10500 60 0000 C CNN +F 3 "" H 8050 10500 60 0000 C CNN + 1 8000 10550 + 1 0 0 1 +$EndComp +$Comp +L 3_and X1 +U 1 1 699ADAE2 +P 7100 12050 +F 0 "X1" H 7200 12000 60 0000 C CNN +F 1 "3_and" H 7250 12200 60 0000 C CNN +F 2 "" H 7100 12050 60 0000 C CNN +F 3 "" H 7100 12050 60 0000 C CNN + 1 7100 12050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 699ADEBA +P 8000 12000 +F 0 "U8" H 8000 11900 60 0000 C CNN +F 1 "d_inverter" H 8000 12150 60 0000 C CNN +F 2 "" H 8050 11950 60 0000 C CNN +F 3 "" H 8050 11950 60 0000 C CNN + 1 8000 12000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7600 12000 7700 12000 +$Comp +L d_inverter U3 +U 1 1 699AE6A1 +P 6150 11700 +F 0 "U3" H 6150 11600 60 0000 C CNN +F 1 "d_inverter" H 6150 11850 60 0000 C CNN +F 2 "" H 6200 11650 60 0000 C CNN +F 3 "" H 6200 11650 60 0000 C CNN + 1 6150 11700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 699AE7FC +P 6150 12050 +F 0 "U4" H 6150 11950 60 0000 C CNN +F 1 "d_inverter" H 6150 12200 60 0000 C CNN +F 2 "" H 6200 12000 60 0000 C CNN +F 3 "" H 6200 12000 60 0000 C CNN + 1 6150 12050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 699AE8D0 +P 5450 12550 +F 0 "U2" H 5450 12450 60 0000 C CNN +F 1 "d_inverter" H 5450 12700 60 0000 C CNN +F 2 "" H 5500 12500 60 0000 C CNN +F 3 "" H 5500 12500 60 0000 C CNN + 1 5450 12550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 699AE9AF +P 6300 12550 +F 0 "U5" H 6300 12450 60 0000 C CNN +F 1 "d_inverter" H 6300 12700 60 0000 C CNN +F 2 "" H 6350 12500 60 0000 C CNN +F 3 "" H 6350 12500 60 0000 C CNN + 1 6300 12550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6450 11700 6700 11700 +Wire Wire Line + 6700 11700 6700 11900 +Wire Wire Line + 6700 11900 6750 11900 +Wire Wire Line + 6450 12050 6600 12050 +Wire Wire Line + 6600 12050 6600 12000 +Wire Wire Line + 6600 12000 6750 12000 +Wire Wire Line + 6750 12100 6600 12100 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11700 14450 +Wire Wire Line + 14300 14050 14300 14450 +Connection ~ 14300 14450 +Wire Wire Line + 16200 14050 16200 14450 +Connection ~ 16200 14450 +Wire Wire Line + 18800 14050 18800 14450 +Connection ~ 18800 14450 +Wire Wire Line + 20700 14050 20700 14450 +Connection ~ 20700 14450 +Wire Wire Line + 23300 14050 23300 14450 +Connection ~ 23300 14450 +Wire Wire Line + 27800 11300 28050 11300 +Wire Wire Line + 27850 11950 28050 11950 +$Comp +L PORT U1 +U 8 1 699B91C4 +P 1050 1300 +F 0 "U1" H 1100 1400 30 0000 C CNN +F 1 "PORT" H 1050 1300 30 0000 C CNN +F 2 "" H 1050 1300 60 0000 C CNN +F 3 "" H 1050 1300 60 0000 C CNN + 8 1050 1300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 699B94A4 +P 28300 11300 +F 0 "U1" H 28350 11400 30 0000 C CNN +F 1 "PORT" H 28300 11300 30 0000 C CNN +F 2 "" H 28300 11300 60 0000 C CNN +F 3 "" H 28300 11300 60 0000 C CNN + 9 28300 11300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 699B9575 +P 6250 10550 +F 0 "U1" H 6300 10650 30 0000 C CNN +F 1 "PORT" H 6250 10550 30 0000 C CNN +F 2 "" H 6250 10550 60 0000 C CNN +F 3 "" H 6250 10550 60 0000 C CNN + 10 6250 10550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 699B9604 +P 9900 7450 +F 0 "U1" H 9950 7550 30 0000 C CNN +F 1 "PORT" H 9900 7450 30 0000 C CNN +F 2 "" H 9900 7450 60 0000 C CNN +F 3 "" H 9900 7450 60 0000 C CNN + 11 9900 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 699B9695 +P 11800 7450 +F 0 "U1" H 11850 7550 30 0000 C CNN +F 1 "PORT" H 11800 7450 30 0000 C CNN +F 2 "" H 11800 7450 60 0000 C CNN +F 3 "" H 11800 7450 60 0000 C CNN + 12 11800 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 699B973E +P 14400 7450 +F 0 "U1" H 14450 7550 30 0000 C CNN +F 1 "PORT" H 14400 7450 30 0000 C CNN +F 2 "" H 14400 7450 60 0000 C CNN +F 3 "" H 14400 7450 60 0000 C CNN + 13 14400 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 699B97D5 +P 5400 11700 +F 0 "U1" H 5450 11800 30 0000 C CNN +F 1 "PORT" H 5400 11700 30 0000 C CNN +F 2 "" H 5400 11700 60 0000 C CNN +F 3 "" H 5400 11700 60 0000 C CNN + 2 5400 11700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 699B9A78 +P 18900 7450 +F 0 "U1" H 18950 7550 30 0000 C CNN +F 1 "PORT" H 18900 7450 30 0000 C CNN +F 2 "" H 18900 7450 60 0000 C CNN +F 3 "" H 18900 7450 60 0000 C CNN + 3 18900 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 699B9D63 +P 20800 7450 +F 0 "U1" H 20850 7550 30 0000 C CNN +F 1 "PORT" H 20800 7450 30 0000 C CNN +F 2 "" H 20800 7450 60 0000 C CNN +F 3 "" H 20800 7450 60 0000 C CNN + 4 20800 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 699B9DFE +P 23400 7450 +F 0 "U1" H 23450 7550 30 0000 C CNN +F 1 "PORT" H 23400 7450 30 0000 C CNN +F 2 "" H 23400 7450 60 0000 C CNN +F 3 "" H 23400 7450 60 0000 C CNN + 5 23400 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 699B9E9B +P 4700 12550 +F 0 "U1" H 4750 12650 30 0000 C CNN +F 1 "PORT" H 4700 12550 30 0000 C CNN +F 2 "" H 4700 12550 60 0000 C CNN +F 3 "" H 4700 12550 60 0000 C CNN + 1 4700 12550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 699B9F3A +P 25300 7450 +F 0 "U1" H 25350 7550 30 0000 C CNN +F 1 "PORT" H 25300 7450 30 0000 C CNN +F 2 "" H 25300 7450 60 0000 C CNN +F 3 "" H 25300 7450 60 0000 C CNN + 6 25300 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 699BA1C5 +P 28300 11950 +F 0 "U1" H 28350 12050 30 0000 C CNN +F 1 "PORT" H 28300 11950 30 0000 C CNN +F 2 "" H 28300 11950 60 0000 C CNN +F 3 "" H 28300 11950 60 0000 C CNN + 7 28300 11950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 699BA268 +P 16300 7450 +F 0 "U1" H 16350 7550 30 0000 C CNN +F 1 "PORT" H 16300 7450 30 0000 C CNN +F 2 "" H 16300 7450 60 0000 C CNN +F 3 "" H 16300 7450 60 0000 C CNN + 14 16300 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 15 1 699BA505 +P 5350 12050 +F 0 "U1" H 5400 12150 30 0000 C CNN +F 1 "PORT" H 5350 12050 30 0000 C CNN +F 2 "" H 5350 12050 60 0000 C CNN +F 3 "" H 5350 12050 60 0000 C CNN + 15 5350 12050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 699BA5AC +P 1050 6200 +F 0 "U1" H 1100 6300 30 0000 C CNN +F 1 "PORT" H 1050 6200 30 0000 C CNN +F 2 "" H 1050 6200 60 0000 C CNN +F 3 "" H 1050 6200 60 0000 C CNN + 16 1050 6200 + 1 0 0 -1 +$EndComp +NoConn ~ 1300 6200 +NoConn ~ 1300 1300 +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165.sub b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165.sub new file mode 100644 index 000000000..24d0619bf --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165.sub @@ -0,0 +1,236 @@ +* Subcircuit 74HCT165 +.subckt 74HCT165 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\74hct165\74hct165.cir +.include 3_and.sub +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad2_ net-_u12-pad4_ net-_u12-pad5_ ? d_dff +* u9 net-_u14-pad2_ net-_u10-pad2_ net-_u10-pad1_ d_nand +* u11 net-_u10-pad1_ net-_u11-pad2_ d_inverter +* u14 net-_u1-pad11_ net-_u14-pad2_ d_buffer +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u13 net-_u10-pad3_ net-_u12-pad4_ d_inverter +* u18 net-_u12-pad5_ net-_u12-pad2_ net-_u17-pad2_ net-_u18-pad4_ net-_u18-pad5_ ? d_dff +* u15 net-_u15-pad1_ net-_u10-pad2_ net-_u15-pad3_ d_nand +* u17 net-_u15-pad3_ net-_u17-pad2_ d_inverter +* u20 net-_u1-pad12_ net-_u15-pad1_ d_buffer +* u16 net-_u15-pad3_ net-_u10-pad2_ net-_u16-pad3_ d_nand +* u19 net-_u16-pad3_ net-_u18-pad4_ d_inverter +* u24 net-_u18-pad5_ net-_u12-pad2_ net-_u23-pad2_ net-_u24-pad4_ net-_u24-pad5_ ? d_dff +* u21 net-_u21-pad1_ net-_u10-pad2_ net-_u21-pad3_ d_nand +* u23 net-_u21-pad3_ net-_u23-pad2_ d_inverter +* u26 net-_u1-pad13_ net-_u21-pad1_ d_buffer +* u22 net-_u21-pad3_ net-_u10-pad2_ net-_u22-pad3_ d_nand +* u25 net-_u22-pad3_ net-_u24-pad4_ d_inverter +* u30 net-_u24-pad5_ net-_u12-pad2_ net-_u29-pad2_ net-_u30-pad4_ net-_u30-pad5_ ? d_dff +* u27 net-_u27-pad1_ net-_u10-pad2_ net-_u27-pad3_ d_nand +* u29 net-_u27-pad3_ net-_u29-pad2_ d_inverter +* u32 net-_u1-pad14_ net-_u27-pad1_ d_buffer +* u28 net-_u27-pad3_ net-_u10-pad2_ net-_u28-pad3_ d_nand +* u31 net-_u28-pad3_ net-_u30-pad4_ d_inverter +* u36 net-_u30-pad5_ net-_u12-pad2_ net-_u35-pad2_ net-_u36-pad4_ net-_u36-pad5_ ? d_dff +* u33 net-_u33-pad1_ net-_u10-pad2_ net-_u33-pad3_ d_nand +* u35 net-_u33-pad3_ net-_u35-pad2_ d_inverter +* u38 net-_u1-pad3_ net-_u33-pad1_ d_buffer +* u34 net-_u33-pad3_ net-_u10-pad2_ net-_u34-pad3_ d_nand +* u37 net-_u34-pad3_ net-_u36-pad4_ d_inverter +* u42 net-_u36-pad5_ net-_u12-pad2_ net-_u41-pad2_ net-_u42-pad4_ net-_u42-pad5_ ? d_dff +* u39 net-_u39-pad1_ net-_u10-pad2_ net-_u39-pad3_ d_nand +* u41 net-_u39-pad3_ net-_u41-pad2_ d_inverter +* u44 net-_u1-pad4_ net-_u39-pad1_ d_buffer +* u40 net-_u39-pad3_ net-_u10-pad2_ net-_u40-pad3_ d_nand +* u43 net-_u40-pad3_ net-_u42-pad4_ d_inverter +* u48 net-_u42-pad5_ net-_u12-pad2_ net-_u47-pad2_ net-_u48-pad4_ net-_u48-pad5_ ? d_dff +* u45 net-_u45-pad1_ net-_u10-pad2_ net-_u45-pad3_ d_nand +* u47 net-_u45-pad3_ net-_u47-pad2_ d_inverter +* u50 net-_u1-pad5_ net-_u45-pad1_ d_buffer +* u46 net-_u45-pad3_ net-_u10-pad2_ net-_u46-pad3_ d_nand +* u49 net-_u46-pad3_ net-_u48-pad4_ d_inverter +* u54 net-_u48-pad5_ net-_u12-pad2_ net-_u53-pad2_ net-_u54-pad4_ net-_u54-pad5_ net-_u54-pad6_ d_dff +* u51 net-_u51-pad1_ net-_u10-pad2_ net-_u51-pad3_ d_nand +* u53 net-_u51-pad3_ net-_u53-pad2_ d_inverter +* u56 net-_u1-pad6_ net-_u51-pad1_ d_buffer +* u52 net-_u51-pad3_ net-_u10-pad2_ net-_u52-pad3_ d_nand +* u55 net-_u52-pad3_ net-_u54-pad4_ d_inverter +* u57 net-_u54-pad5_ net-_u1-pad9_ d_buffer +* u58 net-_u54-pad6_ net-_u1-pad7_ d_buffer +* u6 net-_u1-pad10_ net-_u6-pad2_ d_inverter +* u7 net-_u6-pad2_ net-_u12-pad1_ d_inverter +x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u8-pad1_ 3_and +* u8 net-_u8-pad1_ net-_u12-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad15_ net-_u4-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u10-pad2_ d_inverter +* u5 net-_u10-pad2_ net-_u5-pad2_ d_inverter +a1 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad2_ net-_u12-pad4_ net-_u12-pad5_ ? u12 +a2 [net-_u14-pad2_ net-_u10-pad2_ ] net-_u10-pad1_ u9 +a3 net-_u10-pad1_ net-_u11-pad2_ u11 +a4 net-_u1-pad11_ net-_u14-pad2_ u14 +a5 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a6 net-_u10-pad3_ net-_u12-pad4_ u13 +a7 net-_u12-pad5_ net-_u12-pad2_ net-_u17-pad2_ net-_u18-pad4_ net-_u18-pad5_ ? u18 +a8 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u15-pad3_ u15 +a9 net-_u15-pad3_ net-_u17-pad2_ u17 +a10 net-_u1-pad12_ net-_u15-pad1_ u20 +a11 [net-_u15-pad3_ net-_u10-pad2_ ] net-_u16-pad3_ u16 +a12 net-_u16-pad3_ net-_u18-pad4_ u19 +a13 net-_u18-pad5_ net-_u12-pad2_ net-_u23-pad2_ net-_u24-pad4_ net-_u24-pad5_ ? u24 +a14 [net-_u21-pad1_ net-_u10-pad2_ ] net-_u21-pad3_ u21 +a15 net-_u21-pad3_ net-_u23-pad2_ u23 +a16 net-_u1-pad13_ net-_u21-pad1_ u26 +a17 [net-_u21-pad3_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a18 net-_u22-pad3_ net-_u24-pad4_ u25 +a19 net-_u24-pad5_ net-_u12-pad2_ net-_u29-pad2_ net-_u30-pad4_ net-_u30-pad5_ ? u30 +a20 [net-_u27-pad1_ net-_u10-pad2_ ] net-_u27-pad3_ u27 +a21 net-_u27-pad3_ net-_u29-pad2_ u29 +a22 net-_u1-pad14_ net-_u27-pad1_ u32 +a23 [net-_u27-pad3_ net-_u10-pad2_ ] net-_u28-pad3_ u28 +a24 net-_u28-pad3_ net-_u30-pad4_ u31 +a25 net-_u30-pad5_ net-_u12-pad2_ net-_u35-pad2_ net-_u36-pad4_ net-_u36-pad5_ ? u36 +a26 [net-_u33-pad1_ net-_u10-pad2_ ] net-_u33-pad3_ u33 +a27 net-_u33-pad3_ net-_u35-pad2_ u35 +a28 net-_u1-pad3_ net-_u33-pad1_ u38 +a29 [net-_u33-pad3_ net-_u10-pad2_ ] net-_u34-pad3_ u34 +a30 net-_u34-pad3_ net-_u36-pad4_ u37 +a31 net-_u36-pad5_ net-_u12-pad2_ net-_u41-pad2_ net-_u42-pad4_ net-_u42-pad5_ ? u42 +a32 [net-_u39-pad1_ net-_u10-pad2_ ] net-_u39-pad3_ u39 +a33 net-_u39-pad3_ net-_u41-pad2_ u41 +a34 net-_u1-pad4_ net-_u39-pad1_ u44 +a35 [net-_u39-pad3_ net-_u10-pad2_ ] net-_u40-pad3_ u40 +a36 net-_u40-pad3_ net-_u42-pad4_ u43 +a37 net-_u42-pad5_ net-_u12-pad2_ net-_u47-pad2_ net-_u48-pad4_ net-_u48-pad5_ ? u48 +a38 [net-_u45-pad1_ net-_u10-pad2_ ] net-_u45-pad3_ u45 +a39 net-_u45-pad3_ net-_u47-pad2_ u47 +a40 net-_u1-pad5_ net-_u45-pad1_ u50 +a41 [net-_u45-pad3_ net-_u10-pad2_ ] net-_u46-pad3_ u46 +a42 net-_u46-pad3_ net-_u48-pad4_ u49 +a43 net-_u48-pad5_ net-_u12-pad2_ net-_u53-pad2_ net-_u54-pad4_ net-_u54-pad5_ net-_u54-pad6_ u54 +a44 [net-_u51-pad1_ net-_u10-pad2_ ] net-_u51-pad3_ u51 +a45 net-_u51-pad3_ net-_u53-pad2_ u53 +a46 net-_u1-pad6_ net-_u51-pad1_ u56 +a47 [net-_u51-pad3_ net-_u10-pad2_ ] net-_u52-pad3_ u52 +a48 net-_u52-pad3_ net-_u54-pad4_ u55 +a49 net-_u54-pad5_ net-_u1-pad9_ u57 +a50 net-_u54-pad6_ net-_u1-pad7_ u58 +a51 net-_u1-pad10_ net-_u6-pad2_ u6 +a52 net-_u6-pad2_ net-_u12-pad1_ u7 +a53 net-_u8-pad1_ net-_u12-pad2_ u8 +a54 net-_u1-pad2_ net-_u3-pad2_ u3 +a55 net-_u1-pad15_ net-_u4-pad2_ u4 +a56 net-_u1-pad1_ net-_u10-pad2_ u2 +a57 net-_u10-pad2_ net-_u5-pad2_ u5 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u12 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u14 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u18 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u20 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u24 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u32 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u36 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u38 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u42 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u44 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u48 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u45 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u50 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u54 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u53 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u56 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u52 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u57 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u58 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74HCT165 \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165_Previous_Values.xml new file mode 100644 index 000000000..561b7a311 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/74HCT165_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_dffd_nandd_inverterd_bufferd_nandd_inverterd_dffd_nandd_inverterd_bufferd_nandd_inverterd_dffd_nandd_inverterd_bufferd_nandd_inverterd_dffd_nandd_inverterd_bufferd_nandd_inverterd_dffd_nandd_inverterd_bufferd_nandd_inverterd_dffd_nandd_inverterd_bufferd_nandd_inverterd_dffd_nandd_inverterd_bufferd_nandd_inverterd_dffd_nandd_inverterd_bufferd_nandd_inverterd_bufferd_bufferd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_and \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/analysis b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/74HCT165/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and.cir b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and.pro b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and.sch b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and.sub b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR-cache.lib new file mode 100644 index 000000000..155f5e601 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR.cir b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR.cir new file mode 100644 index 000000000..b338b7b5f --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR.cir.out new file mode 100644 index 000000000..adb6b01be --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR.pro b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR.pro new file mode 100644 index 000000000..881563ebd --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR.sch b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR.sch new file mode 100644 index 000000000..118968656 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR.sub b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR.sub new file mode 100644 index 000000000..d1fd3a241 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR_Previous_Values.xml new file mode 100644 index 000000000..0683d9eb6 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112-cache.lib new file mode 100644 index 000000000..cba523827 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112-cache.lib @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112.cir b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112.cir new file mode 100644 index 000000000..3b1b065a2 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112.cir @@ -0,0 +1,62 @@ +* C:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\SN54112\SN54112.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/17/26 16:05:56 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U23 Net-_U2-Pad2_ Net-_U23-Pad2_ d_inverter +U24 Net-_U24-Pad1_ Net-_U24-Pad2_ d_inverter +U25 Net-_U25-Pad1_ Net-_U25-Pad2_ d_inverter +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U24-Pad1_ d_inverter +U4 Net-_U1-Pad3_ Net-_U25-Pad1_ d_inverter +U43 Net-_U11-Pad2_ Net-_U43-Pad2_ d_inverter +U26 Net-_U26-Pad1_ Net-_U26-Pad2_ d_inverter +U27 Net-_U27-Pad1_ Net-_U27-Pad2_ d_inverter +U28 Net-_U28-Pad1_ Net-_U28-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U26-Pad1_ d_inverter +U6 Net-_U1-Pad5_ Net-_U27-Pad1_ d_inverter +U7 Net-_U1-Pad6_ Net-_U28-Pad1_ d_inverter +U29 Net-_U29-Pad1_ Net-_U29-Pad2_ d_inverter +U30 Net-_U30-Pad1_ Net-_U30-Pad2_ d_inverter +U31 Net-_U10-Pad2_ Net-_U31-Pad2_ d_inverter +U8 Net-_U1-Pad7_ Net-_U29-Pad1_ d_inverter +U9 Net-_U1-Pad8_ Net-_U30-Pad1_ d_inverter +U10 Net-_U1-Pad9_ Net-_U10-Pad2_ d_inverter +U44 Net-_U12-Pad2_ Net-_U44-Pad2_ d_inverter +U45 Net-_U13-Pad2_ Net-_U45-Pad2_ d_inverter +X1 Net-_U24-Pad1_ Net-_U25-Pad1_ Net-_U23-Pad2_ Net-_X1-Pad4_ 3_and +X2 Net-_U2-Pad2_ Net-_U25-Pad1_ Net-_U24-Pad2_ Net-_X13-Pad2_ 3_and +X3 Net-_U24-Pad1_ Net-_U2-Pad2_ Net-_U25-Pad2_ Net-_X13-Pad3_ 3_and +X4 Net-_U25-Pad2_ Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_X13-Pad4_ 3_and +X5 Net-_U27-Pad1_ Net-_U28-Pad1_ Net-_U26-Pad2_ Net-_X14-Pad1_ 3_and +X6 Net-_U26-Pad1_ Net-_U28-Pad1_ Net-_U27-Pad2_ Net-_X14-Pad2_ 3_and +X7 Net-_U27-Pad1_ Net-_U26-Pad1_ Net-_U28-Pad2_ Net-_X14-Pad3_ 3_and +X8 Net-_U28-Pad2_ Net-_U27-Pad2_ Net-_U26-Pad2_ Net-_X14-Pad4_ 3_and +X9 Net-_U30-Pad1_ Net-_U10-Pad2_ Net-_U29-Pad2_ Net-_X15-Pad1_ 3_and +X10 Net-_U29-Pad1_ Net-_U10-Pad2_ Net-_U30-Pad2_ Net-_X10-Pad4_ 3_and +X11 Net-_U30-Pad1_ Net-_U29-Pad1_ Net-_U31-Pad2_ Net-_X11-Pad4_ 3_and +X12 Net-_U31-Pad2_ Net-_U30-Pad2_ Net-_U29-Pad2_ Net-_X12-Pad4_ 3_and +X16 Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U43-Pad2_ Net-_X16-Pad4_ 3_and +X17 Net-_U11-Pad2_ Net-_U13-Pad2_ Net-_U44-Pad2_ Net-_X17-Pad4_ 3_and +X18 Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U45-Pad2_ Net-_X18-Pad4_ 3_and +X19 Net-_U43-Pad2_ Net-_U44-Pad2_ Net-_U45-Pad2_ Net-_X19-Pad4_ 3_and +X20 Net-_U44-Pad2_ Net-_U45-Pad2_ Net-_U11-Pad2_ Net-_X20-Pad4_ 3_and +X21 Net-_U12-Pad2_ Net-_U43-Pad2_ Net-_U45-Pad2_ Net-_X21-Pad4_ 3_and +X22 Net-_U44-Pad2_ Net-_U43-Pad2_ Net-_U13-Pad2_ Net-_X22-Pad4_ 3_and +X23 Net-_U12-Pad2_ Net-_U11-Pad2_ Net-_U13-Pad2_ Net-_X23-Pad4_ 3_and +X13 Net-_X1-Pad4_ Net-_X13-Pad2_ Net-_X13-Pad3_ Net-_X13-Pad4_ Net-_U11-Pad1_ 4_OR +X14 Net-_X14-Pad1_ Net-_X14-Pad2_ Net-_X14-Pad3_ Net-_X14-Pad4_ Net-_U12-Pad1_ 4_OR +X15 Net-_X15-Pad1_ Net-_X10-Pad4_ Net-_X11-Pad4_ Net-_X12-Pad4_ Net-_U13-Pad1_ 4_OR +X25 Net-_X20-Pad4_ Net-_X21-Pad4_ Net-_X22-Pad4_ Net-_X23-Pad4_ Net-_U15-Pad1_ 4_OR +U15 Net-_U15-Pad1_ Net-_U1-Pad11_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +X24 Net-_X16-Pad4_ Net-_X17-Pad4_ Net-_X18-Pad4_ Net-_X19-Pad4_ Net-_U14-Pad1_ 4_OR +U14 Net-_U14-Pad1_ Net-_U1-Pad10_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ PORT + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112.cir.out new file mode 100644 index 000000000..415133133 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112.cir.out @@ -0,0 +1,143 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn54112\sn54112.cir + +.include 3_and.sub +.include 4_OR.sub +* u23 net-_u2-pad2_ net-_u23-pad2_ d_inverter +* u24 net-_u24-pad1_ net-_u24-pad2_ d_inverter +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u24-pad1_ d_inverter +* u4 net-_u1-pad3_ net-_u25-pad1_ d_inverter +* u43 net-_u11-pad2_ net-_u43-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u28 net-_u28-pad1_ net-_u28-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u26-pad1_ d_inverter +* u6 net-_u1-pad5_ net-_u27-pad1_ d_inverter +* u7 net-_u1-pad6_ net-_u28-pad1_ d_inverter +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +* u30 net-_u30-pad1_ net-_u30-pad2_ d_inverter +* u31 net-_u10-pad2_ net-_u31-pad2_ d_inverter +* u8 net-_u1-pad7_ net-_u29-pad1_ d_inverter +* u9 net-_u1-pad8_ net-_u30-pad1_ d_inverter +* u10 net-_u1-pad9_ net-_u10-pad2_ d_inverter +* u44 net-_u12-pad2_ net-_u44-pad2_ d_inverter +* u45 net-_u13-pad2_ net-_u45-pad2_ d_inverter +x1 net-_u24-pad1_ net-_u25-pad1_ net-_u23-pad2_ net-_x1-pad4_ 3_and +x2 net-_u2-pad2_ net-_u25-pad1_ net-_u24-pad2_ net-_x13-pad2_ 3_and +x3 net-_u24-pad1_ net-_u2-pad2_ net-_u25-pad2_ net-_x13-pad3_ 3_and +x4 net-_u25-pad2_ net-_u24-pad2_ net-_u23-pad2_ net-_x13-pad4_ 3_and +x5 net-_u27-pad1_ net-_u28-pad1_ net-_u26-pad2_ net-_x14-pad1_ 3_and +x6 net-_u26-pad1_ net-_u28-pad1_ net-_u27-pad2_ net-_x14-pad2_ 3_and +x7 net-_u27-pad1_ net-_u26-pad1_ net-_u28-pad2_ net-_x14-pad3_ 3_and +x8 net-_u28-pad2_ net-_u27-pad2_ net-_u26-pad2_ net-_x14-pad4_ 3_and +x9 net-_u30-pad1_ net-_u10-pad2_ net-_u29-pad2_ net-_x15-pad1_ 3_and +x10 net-_u29-pad1_ net-_u10-pad2_ net-_u30-pad2_ net-_x10-pad4_ 3_and +x11 net-_u30-pad1_ net-_u29-pad1_ net-_u31-pad2_ net-_x11-pad4_ 3_and +x12 net-_u31-pad2_ net-_u30-pad2_ net-_u29-pad2_ net-_x12-pad4_ 3_and +x16 net-_u12-pad2_ net-_u13-pad2_ net-_u43-pad2_ net-_x16-pad4_ 3_and +x17 net-_u11-pad2_ net-_u13-pad2_ net-_u44-pad2_ net-_x17-pad4_ 3_and +x18 net-_u11-pad2_ net-_u12-pad2_ net-_u45-pad2_ net-_x18-pad4_ 3_and +x19 net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_x19-pad4_ 3_and +x20 net-_u44-pad2_ net-_u45-pad2_ net-_u11-pad2_ net-_x20-pad4_ 3_and +x21 net-_u12-pad2_ net-_u43-pad2_ net-_u45-pad2_ net-_x21-pad4_ 3_and +x22 net-_u44-pad2_ net-_u43-pad2_ net-_u13-pad2_ net-_x22-pad4_ 3_and +x23 net-_u12-pad2_ net-_u11-pad2_ net-_u13-pad2_ net-_x23-pad4_ 3_and +x13 net-_x1-pad4_ net-_x13-pad2_ net-_x13-pad3_ net-_x13-pad4_ net-_u11-pad1_ 4_OR +x14 net-_x14-pad1_ net-_x14-pad2_ net-_x14-pad3_ net-_x14-pad4_ net-_u12-pad1_ 4_OR +x15 net-_x15-pad1_ net-_x10-pad4_ net-_x11-pad4_ net-_x12-pad4_ net-_u13-pad1_ 4_OR +x25 net-_x20-pad4_ net-_x21-pad4_ net-_x22-pad4_ net-_x23-pad4_ net-_u15-pad1_ 4_OR +* u15 net-_u15-pad1_ net-_u1-pad11_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +x24 net-_x16-pad4_ net-_x17-pad4_ net-_x18-pad4_ net-_x19-pad4_ net-_u14-pad1_ 4_OR +* u14 net-_u14-pad1_ net-_u1-pad10_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ port +a1 net-_u2-pad2_ net-_u23-pad2_ u23 +a2 net-_u24-pad1_ net-_u24-pad2_ u24 +a3 net-_u25-pad1_ net-_u25-pad2_ u25 +a4 net-_u1-pad1_ net-_u2-pad2_ u2 +a5 net-_u1-pad2_ net-_u24-pad1_ u3 +a6 net-_u1-pad3_ net-_u25-pad1_ u4 +a7 net-_u11-pad2_ net-_u43-pad2_ u43 +a8 net-_u26-pad1_ net-_u26-pad2_ u26 +a9 net-_u27-pad1_ net-_u27-pad2_ u27 +a10 net-_u28-pad1_ net-_u28-pad2_ u28 +a11 net-_u1-pad4_ net-_u26-pad1_ u5 +a12 net-_u1-pad5_ net-_u27-pad1_ u6 +a13 net-_u1-pad6_ net-_u28-pad1_ u7 +a14 net-_u29-pad1_ net-_u29-pad2_ u29 +a15 net-_u30-pad1_ net-_u30-pad2_ u30 +a16 net-_u10-pad2_ net-_u31-pad2_ u31 +a17 net-_u1-pad7_ net-_u29-pad1_ u8 +a18 net-_u1-pad8_ net-_u30-pad1_ u9 +a19 net-_u1-pad9_ net-_u10-pad2_ u10 +a20 net-_u12-pad2_ net-_u44-pad2_ u44 +a21 net-_u13-pad2_ net-_u45-pad2_ u45 +a22 net-_u15-pad1_ net-_u1-pad11_ u15 +a23 net-_u13-pad1_ net-_u13-pad2_ u13 +a24 net-_u12-pad1_ net-_u12-pad2_ u12 +a25 net-_u11-pad1_ net-_u11-pad2_ u11 +a26 net-_u14-pad1_ net-_u1-pad10_ u14 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-09 100e-09 0e-09 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112.pro b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112.sch b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112.sch new file mode 100644 index 000000000..140481e89 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112.sch @@ -0,0 +1,1229 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN54112-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U23 +U 1 1 6992CFD3 +P 9350 3250 +F 0 "U23" H 9350 3150 60 0000 C CNN +F 1 "d_inverter" H 9350 3400 60 0000 C CNN +F 2 "" H 9400 3200 60 0000 C CNN +F 3 "" H 9400 3200 60 0000 C CNN + 1 9350 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U24 +U 1 1 6992D02E +P 9350 4000 +F 0 "U24" H 9350 3900 60 0000 C CNN +F 1 "d_inverter" H 9350 4150 60 0000 C CNN +F 2 "" H 9400 3950 60 0000 C CNN +F 3 "" H 9400 3950 60 0000 C CNN + 1 9350 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U25 +U 1 1 6992D07C +P 9350 4950 +F 0 "U25" H 9350 4850 60 0000 C CNN +F 1 "d_inverter" H 9350 5100 60 0000 C CNN +F 2 "" H 9400 4900 60 0000 C CNN +F 3 "" H 9400 4900 60 0000 C CNN + 1 9350 4950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 6992D148 +P 7550 3250 +F 0 "U2" H 7550 3150 60 0000 C CNN +F 1 "d_inverter" H 7550 3400 60 0000 C CNN +F 2 "" H 7600 3200 60 0000 C CNN +F 3 "" H 7600 3200 60 0000 C CNN + 1 7550 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 6992D14E +P 7550 4000 +F 0 "U3" H 7550 3900 60 0000 C CNN +F 1 "d_inverter" H 7550 4150 60 0000 C CNN +F 2 "" H 7600 3950 60 0000 C CNN +F 3 "" H 7600 3950 60 0000 C CNN + 1 7550 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 6992D154 +P 7550 4950 +F 0 "U4" H 7550 4850 60 0000 C CNN +F 1 "d_inverter" H 7550 5100 60 0000 C CNN +F 2 "" H 7600 4900 60 0000 C CNN +F 3 "" H 7600 4900 60 0000 C CNN + 1 7550 4950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U43 +U 1 1 6992EDA8 +P 14750 4000 +F 0 "U43" H 14750 3900 60 0000 C CNN +F 1 "d_inverter" H 14750 4150 60 0000 C CNN +F 2 "" H 14800 3950 60 0000 C CNN +F 3 "" H 14800 3950 60 0000 C CNN + 1 14750 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U26 +U 1 1 6992F28B +P 9350 6850 +F 0 "U26" H 9350 6750 60 0000 C CNN +F 1 "d_inverter" H 9350 7000 60 0000 C CNN +F 2 "" H 9400 6800 60 0000 C CNN +F 3 "" H 9400 6800 60 0000 C CNN + 1 9350 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U27 +U 1 1 6992F291 +P 9350 7600 +F 0 "U27" H 9350 7500 60 0000 C CNN +F 1 "d_inverter" H 9350 7750 60 0000 C CNN +F 2 "" H 9400 7550 60 0000 C CNN +F 3 "" H 9400 7550 60 0000 C CNN + 1 9350 7600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U28 +U 1 1 6992F297 +P 9350 8550 +F 0 "U28" H 9350 8450 60 0000 C CNN +F 1 "d_inverter" H 9350 8700 60 0000 C CNN +F 2 "" H 9400 8500 60 0000 C CNN +F 3 "" H 9400 8500 60 0000 C CNN + 1 9350 8550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6992F29D +P 7550 6850 +F 0 "U5" H 7550 6750 60 0000 C CNN +F 1 "d_inverter" H 7550 7000 60 0000 C CNN +F 2 "" H 7600 6800 60 0000 C CNN +F 3 "" H 7600 6800 60 0000 C CNN + 1 7550 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6992F2A3 +P 7550 7600 +F 0 "U6" H 7550 7500 60 0000 C CNN +F 1 "d_inverter" H 7550 7750 60 0000 C CNN +F 2 "" H 7600 7550 60 0000 C CNN +F 3 "" H 7600 7550 60 0000 C CNN + 1 7550 7600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 6992F2A9 +P 7550 8550 +F 0 "U7" H 7550 8450 60 0000 C CNN +F 1 "d_inverter" H 7550 8700 60 0000 C CNN +F 2 "" H 7600 8500 60 0000 C CNN +F 3 "" H 7600 8500 60 0000 C CNN + 1 7550 8550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U29 +U 1 1 6992F6C2 +P 9350 10800 +F 0 "U29" H 9350 10700 60 0000 C CNN +F 1 "d_inverter" H 9350 10950 60 0000 C CNN +F 2 "" H 9400 10750 60 0000 C CNN +F 3 "" H 9400 10750 60 0000 C CNN + 1 9350 10800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U30 +U 1 1 6992F6C8 +P 9350 11550 +F 0 "U30" H 9350 11450 60 0000 C CNN +F 1 "d_inverter" H 9350 11700 60 0000 C CNN +F 2 "" H 9400 11500 60 0000 C CNN +F 3 "" H 9400 11500 60 0000 C CNN + 1 9350 11550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U31 +U 1 1 6992F6CE +P 9350 12500 +F 0 "U31" H 9350 12400 60 0000 C CNN +F 1 "d_inverter" H 9350 12650 60 0000 C CNN +F 2 "" H 9400 12450 60 0000 C CNN +F 3 "" H 9400 12450 60 0000 C CNN + 1 9350 12500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 6992F6D4 +P 7550 10800 +F 0 "U8" H 7550 10700 60 0000 C CNN +F 1 "d_inverter" H 7550 10950 60 0000 C CNN +F 2 "" H 7600 10750 60 0000 C CNN +F 3 "" H 7600 10750 60 0000 C CNN + 1 7550 10800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 6992F6DA +P 7550 11550 +F 0 "U9" H 7550 11450 60 0000 C CNN +F 1 "d_inverter" H 7550 11700 60 0000 C CNN +F 2 "" H 7600 11500 60 0000 C CNN +F 3 "" H 7600 11500 60 0000 C CNN + 1 7550 11550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 6992F6E0 +P 7550 12500 +F 0 "U10" H 7550 12400 60 0000 C CNN +F 1 "d_inverter" H 7550 12650 60 0000 C CNN +F 2 "" H 7600 12450 60 0000 C CNN +F 3 "" H 7600 12450 60 0000 C CNN + 1 7550 12500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U44 +U 1 1 69930028 +P 14800 7600 +F 0 "U44" H 14800 7500 60 0000 C CNN +F 1 "d_inverter" H 14800 7750 60 0000 C CNN +F 2 "" H 14850 7550 60 0000 C CNN +F 3 "" H 14850 7550 60 0000 C CNN + 1 14800 7600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U45 +U 1 1 699301CD +P 14900 11550 +F 0 "U45" H 14900 11450 60 0000 C CNN +F 1 "d_inverter" H 14900 11700 60 0000 C CNN +F 2 "" H 14950 11500 60 0000 C CNN +F 3 "" H 14950 11500 60 0000 C CNN + 1 14900 11550 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X1 +U 1 1 699350BE +P 10500 3000 +F 0 "X1" H 10600 2950 60 0000 C CNN +F 1 "3_and" H 10650 3150 60 0000 C CNN +F 2 "" H 10500 3000 60 0000 C CNN +F 3 "" H 10500 3000 60 0000 C CNN + 1 10500 3000 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 69935D00 +P 10500 3800 +F 0 "X2" H 10600 3750 60 0000 C CNN +F 1 "3_and" H 10650 3950 60 0000 C CNN +F 2 "" H 10500 3800 60 0000 C CNN +F 3 "" H 10500 3800 60 0000 C CNN + 1 10500 3800 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 69935FB8 +P 10500 4600 +F 0 "X3" H 10600 4550 60 0000 C CNN +F 1 "3_and" H 10650 4750 60 0000 C CNN +F 2 "" H 10500 4600 60 0000 C CNN +F 3 "" H 10500 4600 60 0000 C CNN + 1 10500 4600 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X4 +U 1 1 69936565 +P 10500 5400 +F 0 "X4" H 10600 5350 60 0000 C CNN +F 1 "3_and" H 10650 5550 60 0000 C CNN +F 2 "" H 10500 5400 60 0000 C CNN +F 3 "" H 10500 5400 60 0000 C CNN + 1 10500 5400 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X5 +U 1 1 69936F56 +P 10500 6600 +F 0 "X5" H 10600 6550 60 0000 C CNN +F 1 "3_and" H 10650 6750 60 0000 C CNN +F 2 "" H 10500 6600 60 0000 C CNN +F 3 "" H 10500 6600 60 0000 C CNN + 1 10500 6600 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X6 +U 1 1 699373E6 +P 10500 7400 +F 0 "X6" H 10600 7350 60 0000 C CNN +F 1 "3_and" H 10650 7550 60 0000 C CNN +F 2 "" H 10500 7400 60 0000 C CNN +F 3 "" H 10500 7400 60 0000 C CNN + 1 10500 7400 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X7 +U 1 1 699377CA +P 10500 8200 +F 0 "X7" H 10600 8150 60 0000 C CNN +F 1 "3_and" H 10650 8350 60 0000 C CNN +F 2 "" H 10500 8200 60 0000 C CNN +F 3 "" H 10500 8200 60 0000 C CNN + 1 10500 8200 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X8 +U 1 1 69937FCE +P 10500 9000 +F 0 "X8" H 10600 8950 60 0000 C CNN +F 1 "3_and" H 10650 9150 60 0000 C CNN +F 2 "" H 10500 9000 60 0000 C CNN +F 3 "" H 10500 9000 60 0000 C CNN + 1 10500 9000 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X9 +U 1 1 69938353 +P 10500 10550 +F 0 "X9" H 10600 10500 60 0000 C CNN +F 1 "3_and" H 10650 10700 60 0000 C CNN +F 2 "" H 10500 10550 60 0000 C CNN +F 3 "" H 10500 10550 60 0000 C CNN + 1 10500 10550 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X10 +U 1 1 69938AF9 +P 10500 11350 +F 0 "X10" H 10600 11300 60 0000 C CNN +F 1 "3_and" H 10650 11500 60 0000 C CNN +F 2 "" H 10500 11350 60 0000 C CNN +F 3 "" H 10500 11350 60 0000 C CNN + 1 10500 11350 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X11 +U 1 1 69938FB6 +P 10500 12150 +F 0 "X11" H 10600 12100 60 0000 C CNN +F 1 "3_and" H 10650 12300 60 0000 C CNN +F 2 "" H 10500 12150 60 0000 C CNN +F 3 "" H 10500 12150 60 0000 C CNN + 1 10500 12150 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X12 +U 1 1 699392B8 +P 10500 12950 +F 0 "X12" H 10600 12900 60 0000 C CNN +F 1 "3_and" H 10650 13100 60 0000 C CNN +F 2 "" H 10500 12950 60 0000 C CNN +F 3 "" H 10500 12950 60 0000 C CNN + 1 10500 12950 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X16 +U 1 1 6993A246 +P 16650 3950 +F 0 "X16" H 16750 3900 60 0000 C CNN +F 1 "3_and" H 16800 4100 60 0000 C CNN +F 2 "" H 16650 3950 60 0000 C CNN +F 3 "" H 16650 3950 60 0000 C CNN + 1 16650 3950 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X17 +U 1 1 6993A51C +P 16650 4750 +F 0 "X17" H 16750 4700 60 0000 C CNN +F 1 "3_and" H 16800 4900 60 0000 C CNN +F 2 "" H 16650 4750 60 0000 C CNN +F 3 "" H 16650 4750 60 0000 C CNN + 1 16650 4750 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X18 +U 1 1 6993A63B +P 16650 5550 +F 0 "X18" H 16750 5500 60 0000 C CNN +F 1 "3_and" H 16800 5700 60 0000 C CNN +F 2 "" H 16650 5550 60 0000 C CNN +F 3 "" H 16650 5550 60 0000 C CNN + 1 16650 5550 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X19 +U 1 1 6993A911 +P 16650 6350 +F 0 "X19" H 16750 6300 60 0000 C CNN +F 1 "3_and" H 16800 6500 60 0000 C CNN +F 2 "" H 16650 6350 60 0000 C CNN +F 3 "" H 16650 6350 60 0000 C CNN + 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+$Comp +L PORT U1 +U 4 1 6993A973 +P 6750 6850 +F 0 "U1" H 6800 6950 30 0000 C CNN +F 1 "PORT" H 6750 6850 30 0000 C CNN +F 2 "" H 6750 6850 60 0000 C CNN +F 3 "" H 6750 6850 60 0000 C CNN + 4 6750 6850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6993ABCF +P 6800 4950 +F 0 "U1" H 6850 5050 30 0000 C CNN +F 1 "PORT" H 6800 4950 30 0000 C CNN +F 2 "" H 6800 4950 60 0000 C CNN +F 3 "" H 6800 4950 60 0000 C CNN + 3 6800 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6993AA0C +P 6850 4000 +F 0 "U1" H 6900 4100 30 0000 C CNN +F 1 "PORT" H 6850 4000 30 0000 C CNN +F 2 "" H 6850 4000 60 0000 C CNN +F 3 "" H 6850 4000 60 0000 C CNN + 2 6850 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6993ADF6 +P 6750 3250 +F 0 "U1" H 6800 3350 30 0000 C CNN +F 1 "PORT" H 6750 3250 30 0000 C CNN +F 2 "" H 6750 3250 60 0000 C CNN +F 3 "" H 6750 3250 60 0000 C CNN + 1 6750 3250 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112.sub b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112.sub new file mode 100644 index 000000000..41ed1f369 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112.sub @@ -0,0 +1,137 @@ +* Subcircuit SN54112 +.subckt SN54112 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn54112\sn54112.cir +.include 3_and.sub +.include 4_OR.sub +* u23 net-_u2-pad2_ net-_u23-pad2_ d_inverter +* u24 net-_u24-pad1_ net-_u24-pad2_ d_inverter +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u24-pad1_ d_inverter +* u4 net-_u1-pad3_ net-_u25-pad1_ d_inverter +* u43 net-_u11-pad2_ net-_u43-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u28 net-_u28-pad1_ net-_u28-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u26-pad1_ d_inverter +* u6 net-_u1-pad5_ net-_u27-pad1_ d_inverter +* u7 net-_u1-pad6_ net-_u28-pad1_ d_inverter +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +* u30 net-_u30-pad1_ net-_u30-pad2_ d_inverter +* u31 net-_u10-pad2_ net-_u31-pad2_ d_inverter +* u8 net-_u1-pad7_ net-_u29-pad1_ d_inverter +* u9 net-_u1-pad8_ net-_u30-pad1_ d_inverter +* u10 net-_u1-pad9_ net-_u10-pad2_ d_inverter +* u44 net-_u12-pad2_ net-_u44-pad2_ d_inverter +* u45 net-_u13-pad2_ net-_u45-pad2_ d_inverter +x1 net-_u24-pad1_ net-_u25-pad1_ net-_u23-pad2_ net-_x1-pad4_ 3_and +x2 net-_u2-pad2_ net-_u25-pad1_ net-_u24-pad2_ net-_x13-pad2_ 3_and +x3 net-_u24-pad1_ net-_u2-pad2_ net-_u25-pad2_ net-_x13-pad3_ 3_and +x4 net-_u25-pad2_ net-_u24-pad2_ net-_u23-pad2_ net-_x13-pad4_ 3_and +x5 net-_u27-pad1_ net-_u28-pad1_ net-_u26-pad2_ net-_x14-pad1_ 3_and +x6 net-_u26-pad1_ net-_u28-pad1_ net-_u27-pad2_ net-_x14-pad2_ 3_and +x7 net-_u27-pad1_ net-_u26-pad1_ net-_u28-pad2_ net-_x14-pad3_ 3_and +x8 net-_u28-pad2_ net-_u27-pad2_ net-_u26-pad2_ net-_x14-pad4_ 3_and +x9 net-_u30-pad1_ net-_u10-pad2_ net-_u29-pad2_ net-_x15-pad1_ 3_and +x10 net-_u29-pad1_ net-_u10-pad2_ net-_u30-pad2_ net-_x10-pad4_ 3_and +x11 net-_u30-pad1_ net-_u29-pad1_ net-_u31-pad2_ net-_x11-pad4_ 3_and +x12 net-_u31-pad2_ net-_u30-pad2_ net-_u29-pad2_ net-_x12-pad4_ 3_and +x16 net-_u12-pad2_ net-_u13-pad2_ net-_u43-pad2_ net-_x16-pad4_ 3_and +x17 net-_u11-pad2_ net-_u13-pad2_ net-_u44-pad2_ net-_x17-pad4_ 3_and +x18 net-_u11-pad2_ net-_u12-pad2_ net-_u45-pad2_ net-_x18-pad4_ 3_and +x19 net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_x19-pad4_ 3_and +x20 net-_u44-pad2_ net-_u45-pad2_ net-_u11-pad2_ net-_x20-pad4_ 3_and +x21 net-_u12-pad2_ net-_u43-pad2_ net-_u45-pad2_ net-_x21-pad4_ 3_and +x22 net-_u44-pad2_ net-_u43-pad2_ net-_u13-pad2_ net-_x22-pad4_ 3_and +x23 net-_u12-pad2_ net-_u11-pad2_ net-_u13-pad2_ net-_x23-pad4_ 3_and +x13 net-_x1-pad4_ net-_x13-pad2_ net-_x13-pad3_ net-_x13-pad4_ net-_u11-pad1_ 4_OR +x14 net-_x14-pad1_ net-_x14-pad2_ net-_x14-pad3_ net-_x14-pad4_ net-_u12-pad1_ 4_OR +x15 net-_x15-pad1_ net-_x10-pad4_ net-_x11-pad4_ net-_x12-pad4_ net-_u13-pad1_ 4_OR +x25 net-_x20-pad4_ net-_x21-pad4_ net-_x22-pad4_ net-_x23-pad4_ net-_u15-pad1_ 4_OR +* u15 net-_u15-pad1_ net-_u1-pad11_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +x24 net-_x16-pad4_ net-_x17-pad4_ net-_x18-pad4_ net-_x19-pad4_ net-_u14-pad1_ 4_OR +* u14 net-_u14-pad1_ net-_u1-pad10_ d_inverter +a1 net-_u2-pad2_ net-_u23-pad2_ u23 +a2 net-_u24-pad1_ net-_u24-pad2_ u24 +a3 net-_u25-pad1_ net-_u25-pad2_ u25 +a4 net-_u1-pad1_ net-_u2-pad2_ u2 +a5 net-_u1-pad2_ net-_u24-pad1_ u3 +a6 net-_u1-pad3_ net-_u25-pad1_ u4 +a7 net-_u11-pad2_ net-_u43-pad2_ u43 +a8 net-_u26-pad1_ net-_u26-pad2_ u26 +a9 net-_u27-pad1_ net-_u27-pad2_ u27 +a10 net-_u28-pad1_ net-_u28-pad2_ u28 +a11 net-_u1-pad4_ net-_u26-pad1_ u5 +a12 net-_u1-pad5_ net-_u27-pad1_ u6 +a13 net-_u1-pad6_ net-_u28-pad1_ u7 +a14 net-_u29-pad1_ net-_u29-pad2_ u29 +a15 net-_u30-pad1_ net-_u30-pad2_ u30 +a16 net-_u10-pad2_ net-_u31-pad2_ u31 +a17 net-_u1-pad7_ net-_u29-pad1_ u8 +a18 net-_u1-pad8_ net-_u30-pad1_ u9 +a19 net-_u1-pad9_ net-_u10-pad2_ u10 +a20 net-_u12-pad2_ net-_u44-pad2_ u44 +a21 net-_u13-pad2_ net-_u45-pad2_ u45 +a22 net-_u15-pad1_ net-_u1-pad11_ u15 +a23 net-_u13-pad1_ net-_u13-pad2_ u13 +a24 net-_u12-pad1_ net-_u12-pad2_ u12 +a25 net-_u11-pad1_ net-_u11-pad2_ u11 +a26 net-_u14-pad1_ net-_u1-pad10_ u14 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN54112 \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112_Previous_Values.xml new file mode 100644 index 000000000..b07c85088 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/SN54112_Previous_Values.xml @@ -0,0 +1 @@ +dc5dc0dc5dc0dc5dc0dc5dc0dc5and3_gateand3_gateand3_gateand3_gated_inverterd_inverterd_inverterd_inverterd_inverterd_inverternor_fourand3_gateand3_gateand3_gateand3_gatenor_fourd_inverterand3_gateand3_gateand3_gateand3_gated_inverterd_inverterd_inverterd_inverterd_inverterd_inverternor_fourand3_gateand3_gateand3_gateand3_gated_inverterd_inverterd_inverterd_inverterd_inverterd_inverternor_fourand3_gateand3_gateand3_gateand3_gatenor_fourd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverteradc_bridgeadc_bridgedac_bridgeC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100nsnsns \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/analysis b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/analysis new file mode 100644 index 000000000..6e2c10bbf --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54112/analysis @@ -0,0 +1 @@ +.tran 10e-09 100e-09 0e-09 \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and.cir b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and.pro b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and.sch b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and.sub b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and-cache.lib new file mode 100644 index 000000000..60f1a83d4 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and-rescue.lib b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and-rescue.lib new file mode 100644 index 000000000..e38330518 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and.cir b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and.cir new file mode 100644 index 000000000..fdf2e1074 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and.cir.out new file mode 100644 index 000000000..f40e5bc62 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and.pro b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and.pro new file mode 100644 index 000000000..b13a0a825 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and.sch b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and.sch new file mode 100644 index 000000000..f5e8febdc --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and.sub b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and.sub new file mode 100644 index 000000000..8663f37e6 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and_Previous_Values.xml new file mode 100644 index 000000000..f2ba0130e --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190-cache.lib new file mode 100644 index 000000000..4c5d1a3fb --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190-cache.lib @@ -0,0 +1,169 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_jkff +# +DEF d_jkff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_jkff" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X J 1 -800 400 200 R 50 50 1 1 I +X K 2 -800 -450 200 R 50 50 1 1 I +X Clk 3 -800 0 200 R 50 50 1 1 I C +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190.cir b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190.cir new file mode 100644 index 000000000..ec473efd1 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190.cir @@ -0,0 +1,63 @@ +* C:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\SN54190\SN54190.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/17/26 20:44:06 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U4-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad7_ Net-_U17-Pad1_ 3_and +X2 Net-_U3-Pad1_ Net-_U32-Pad7_ Net-_U35-Pad7_ Net-_X2-Pad4_ 3_and +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U1-Pad12_ d_or +X3 Net-_X2-Pad4_ Net-_U38-Pad7_ Net-_U15-Pad2_ Net-_U17-Pad2_ 3_and +U10 Net-_U1-Pad15_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nand +U32 Net-_U22-Pad2_ Net-_U22-Pad2_ Net-_U26-Pad2_ Net-_U31-Pad2_ Net-_U32-Pad5_ Net-_U1-Pad3_ Net-_U32-Pad7_ d_jkff +U33 Net-_U16-Pad3_ Net-_U32-Pad5_ d_inverter +U31 Net-_U10-Pad3_ Net-_U31-Pad2_ d_inverter +U9 Net-_U1-Pad4_ Net-_U22-Pad2_ d_inverter +U16 Net-_U10-Pad3_ Net-_U10-Pad2_ Net-_U16-Pad3_ d_nand +U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_nand +U43 Net-_U30-Pad3_ Net-_U1-Pad12_ Net-_U1-Pad13_ d_nand +U30 Net-_U22-Pad3_ Net-_U22-Pad3_ Net-_U30-Pad3_ d_nand +U26 Net-_U22-Pad1_ Net-_U26-Pad2_ d_inverter +U5 Net-_U1-Pad14_ Net-_U22-Pad1_ d_inverter +U6 Net-_U1-Pad5_ Net-_U4-Pad2_ d_inverter +U7 Net-_U4-Pad2_ Net-_U3-Pad1_ d_inverter +U3 Net-_U3-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_nor +U4 Net-_U1-Pad4_ Net-_U4-Pad2_ Net-_U4-Pad3_ d_nor +U38 Net-_U19-Pad3_ Net-_U19-Pad3_ Net-_U28-Pad2_ Net-_U37-Pad2_ Net-_U38-Pad5_ Net-_U1-Pad6_ Net-_U38-Pad7_ d_jkff +U39 Net-_U24-Pad3_ Net-_U38-Pad5_ d_inverter +U37 Net-_U13-Pad3_ Net-_U37-Pad2_ d_inverter +U28 Net-_U22-Pad1_ Net-_U28-Pad2_ d_inverter +U24 Net-_U13-Pad3_ Net-_U10-Pad2_ Net-_U24-Pad3_ d_nand +U19 Net-_U19-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_or +U35 Net-_U18-Pad3_ Net-_U18-Pad3_ Net-_U27-Pad2_ Net-_U34-Pad2_ Net-_U35-Pad5_ Net-_U1-Pad2_ Net-_U35-Pad7_ d_jkff +U36 Net-_U23-Pad3_ Net-_U35-Pad5_ d_inverter +U34 Net-_U12-Pad3_ Net-_U34-Pad2_ d_inverter +U27 Net-_U22-Pad1_ Net-_U27-Pad2_ d_inverter +U23 Net-_U12-Pad3_ Net-_U10-Pad2_ Net-_U23-Pad3_ d_nand +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_or +U41 Net-_U20-Pad3_ Net-_U20-Pad3_ Net-_U29-Pad2_ Net-_U40-Pad2_ Net-_U41-Pad5_ Net-_U1-Pad7_ Net-_U15-Pad2_ d_jkff +U42 Net-_U25-Pad3_ Net-_U41-Pad5_ d_inverter +U40 Net-_U14-Pad3_ Net-_U40-Pad2_ d_inverter +U29 Net-_U22-Pad1_ Net-_U29-Pad2_ d_inverter +U25 Net-_U14-Pad3_ Net-_U10-Pad2_ Net-_U25-Pad3_ d_nand +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U20-Pad1_ d_or +U12 Net-_U1-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad3_ d_nand +X4 Net-_U4-Pad3_ Net-_U32-Pad7_ Net-_U15-Pad3_ Net-_U18-Pad1_ 3_and +X5 Net-_U1-Pad3_ Net-_U15-Pad2_ Net-_U3-Pad3_ Net-_U18-Pad2_ 3_and +U8 Net-_U35-Pad7_ Net-_U38-Pad7_ Net-_U11-Pad1_ d_nand +U15 Net-_U11-Pad3_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nand +U11 Net-_U11-Pad1_ Net-_U11-Pad1_ Net-_U11-Pad3_ d_nand +U13 Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U13-Pad3_ d_nand +X7 Net-_U15-Pad3_ Net-_U4-Pad3_ Net-_U32-Pad7_ Net-_U35-Pad7_ Net-_U19-Pad1_ 4_and +U14 Net-_U1-Pad9_ Net-_U10-Pad2_ Net-_U14-Pad3_ d_nand +X9 Net-_U4-Pad3_ Net-_U32-Pad7_ Net-_U35-Pad7_ Net-_U38-Pad7_ Net-_U21-Pad1_ 4_and +X6 Net-_U1-Pad3_ Net-_U1-Pad7_ Net-_U3-Pad3_ Net-_U21-Pad2_ 3_and +X10 Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U20-Pad2_ 4_and +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_or +U2 Net-_U1-Pad11_ Net-_U10-Pad2_ d_inverter +X8 Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U3-Pad3_ Net-_U19-Pad2_ 3_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190.cir.out new file mode 100644 index 000000000..b67f7dcb0 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190.cir.out @@ -0,0 +1,192 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn54190\sn54190.cir + +.include 3_and.sub +.include 4_and.sub +x1 net-_u4-pad2_ net-_u1-pad3_ net-_u1-pad7_ net-_u17-pad1_ 3_and +x2 net-_u3-pad1_ net-_u32-pad7_ net-_u35-pad7_ net-_x2-pad4_ 3_and +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u1-pad12_ d_or +x3 net-_x2-pad4_ net-_u38-pad7_ net-_u15-pad2_ net-_u17-pad2_ 3_and +* u10 net-_u1-pad15_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u32 net-_u22-pad2_ net-_u22-pad2_ net-_u26-pad2_ net-_u31-pad2_ net-_u32-pad5_ net-_u1-pad3_ net-_u32-pad7_ d_jkff +* u33 net-_u16-pad3_ net-_u32-pad5_ d_inverter +* u31 net-_u10-pad3_ net-_u31-pad2_ d_inverter +* u9 net-_u1-pad4_ net-_u22-pad2_ d_inverter +* u16 net-_u10-pad3_ net-_u10-pad2_ net-_u16-pad3_ d_nand +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_nand +* u43 net-_u30-pad3_ net-_u1-pad12_ net-_u1-pad13_ d_nand +* u30 net-_u22-pad3_ net-_u22-pad3_ net-_u30-pad3_ d_nand +* u26 net-_u22-pad1_ net-_u26-pad2_ d_inverter +* u5 net-_u1-pad14_ net-_u22-pad1_ d_inverter +* u6 net-_u1-pad5_ net-_u4-pad2_ d_inverter +* u7 net-_u4-pad2_ net-_u3-pad1_ d_inverter +* u3 net-_u3-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_nor +* u4 net-_u1-pad4_ net-_u4-pad2_ net-_u4-pad3_ d_nor +* u38 net-_u19-pad3_ net-_u19-pad3_ net-_u28-pad2_ net-_u37-pad2_ net-_u38-pad5_ net-_u1-pad6_ net-_u38-pad7_ d_jkff +* u39 net-_u24-pad3_ net-_u38-pad5_ d_inverter +* u37 net-_u13-pad3_ net-_u37-pad2_ d_inverter +* u28 net-_u22-pad1_ net-_u28-pad2_ d_inverter +* u24 net-_u13-pad3_ net-_u10-pad2_ net-_u24-pad3_ d_nand +* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_or +* u35 net-_u18-pad3_ net-_u18-pad3_ net-_u27-pad2_ net-_u34-pad2_ net-_u35-pad5_ net-_u1-pad2_ net-_u35-pad7_ d_jkff +* u36 net-_u23-pad3_ net-_u35-pad5_ d_inverter +* u34 net-_u12-pad3_ net-_u34-pad2_ d_inverter +* u27 net-_u22-pad1_ net-_u27-pad2_ d_inverter +* u23 net-_u12-pad3_ net-_u10-pad2_ net-_u23-pad3_ d_nand +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_or +* u41 net-_u20-pad3_ net-_u20-pad3_ net-_u29-pad2_ net-_u40-pad2_ net-_u41-pad5_ net-_u1-pad7_ net-_u15-pad2_ d_jkff +* u42 net-_u25-pad3_ net-_u41-pad5_ d_inverter +* u40 net-_u14-pad3_ net-_u40-pad2_ d_inverter +* u29 net-_u22-pad1_ net-_u29-pad2_ d_inverter +* u25 net-_u14-pad3_ net-_u10-pad2_ net-_u25-pad3_ d_nand +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u20-pad1_ d_or +* u12 net-_u1-pad1_ net-_u10-pad2_ net-_u12-pad3_ d_nand +x4 net-_u4-pad3_ net-_u32-pad7_ net-_u15-pad3_ net-_u18-pad1_ 3_and +x5 net-_u1-pad3_ net-_u15-pad2_ net-_u3-pad3_ net-_u18-pad2_ 3_and +* u8 net-_u35-pad7_ net-_u38-pad7_ net-_u11-pad1_ d_nand +* u15 net-_u11-pad3_ net-_u15-pad2_ net-_u15-pad3_ d_nand +* u11 net-_u11-pad1_ net-_u11-pad1_ net-_u11-pad3_ d_nand +* u13 net-_u1-pad10_ net-_u10-pad2_ net-_u13-pad3_ d_nand +x7 net-_u15-pad3_ net-_u4-pad3_ net-_u32-pad7_ net-_u35-pad7_ net-_u19-pad1_ 4_and +* u14 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ d_nand +x9 net-_u4-pad3_ net-_u32-pad7_ net-_u35-pad7_ net-_u38-pad7_ net-_u21-pad1_ 4_and +x6 net-_u1-pad3_ net-_u1-pad7_ net-_u3-pad3_ net-_u21-pad2_ 3_and +x10 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u3-pad3_ net-_u20-pad2_ 4_and +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u20-pad3_ d_or +* u2 net-_u1-pad11_ net-_u10-pad2_ d_inverter +x8 net-_u1-pad3_ net-_u1-pad2_ net-_u3-pad3_ net-_u19-pad2_ 3_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +a1 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u1-pad12_ u17 +a2 [net-_u1-pad15_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a3 net-_u22-pad2_ net-_u22-pad2_ net-_u26-pad2_ net-_u31-pad2_ net-_u32-pad5_ net-_u1-pad3_ net-_u32-pad7_ u32 +a4 net-_u16-pad3_ net-_u32-pad5_ u33 +a5 net-_u10-pad3_ net-_u31-pad2_ u31 +a6 net-_u1-pad4_ net-_u22-pad2_ u9 +a7 [net-_u10-pad3_ net-_u10-pad2_ ] net-_u16-pad3_ u16 +a8 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a9 [net-_u30-pad3_ net-_u1-pad12_ ] net-_u1-pad13_ u43 +a10 [net-_u22-pad3_ net-_u22-pad3_ ] net-_u30-pad3_ u30 +a11 net-_u22-pad1_ net-_u26-pad2_ u26 +a12 net-_u1-pad14_ net-_u22-pad1_ u5 +a13 net-_u1-pad5_ net-_u4-pad2_ u6 +a14 net-_u4-pad2_ net-_u3-pad1_ u7 +a15 [net-_u3-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a16 [net-_u1-pad4_ net-_u4-pad2_ ] net-_u4-pad3_ u4 +a17 net-_u19-pad3_ net-_u19-pad3_ net-_u28-pad2_ net-_u37-pad2_ net-_u38-pad5_ net-_u1-pad6_ net-_u38-pad7_ u38 +a18 net-_u24-pad3_ net-_u38-pad5_ u39 +a19 net-_u13-pad3_ net-_u37-pad2_ u37 +a20 net-_u22-pad1_ net-_u28-pad2_ u28 +a21 [net-_u13-pad3_ net-_u10-pad2_ ] net-_u24-pad3_ u24 +a22 [net-_u19-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a23 net-_u18-pad3_ net-_u18-pad3_ net-_u27-pad2_ net-_u34-pad2_ net-_u35-pad5_ net-_u1-pad2_ net-_u35-pad7_ u35 +a24 net-_u23-pad3_ net-_u35-pad5_ u36 +a25 net-_u12-pad3_ net-_u34-pad2_ u34 +a26 net-_u22-pad1_ net-_u27-pad2_ u27 +a27 [net-_u12-pad3_ net-_u10-pad2_ ] net-_u23-pad3_ u23 +a28 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a29 net-_u20-pad3_ net-_u20-pad3_ net-_u29-pad2_ net-_u40-pad2_ net-_u41-pad5_ net-_u1-pad7_ net-_u15-pad2_ u41 +a30 net-_u25-pad3_ net-_u41-pad5_ u42 +a31 net-_u14-pad3_ net-_u40-pad2_ u40 +a32 net-_u22-pad1_ net-_u29-pad2_ u29 +a33 [net-_u14-pad3_ net-_u10-pad2_ ] net-_u25-pad3_ u25 +a34 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u20-pad1_ u21 +a35 [net-_u1-pad1_ net-_u10-pad2_ ] net-_u12-pad3_ u12 +a36 [net-_u35-pad7_ net-_u38-pad7_ ] net-_u11-pad1_ u8 +a37 [net-_u11-pad3_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a38 [net-_u11-pad1_ net-_u11-pad1_ ] net-_u11-pad3_ u11 +a39 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u13-pad3_ u13 +a40 [net-_u1-pad9_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a41 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a42 net-_u1-pad11_ net-_u10-pad2_ u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u32 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u38 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u35 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u41 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190.pro b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190.sch b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190.sch new file mode 100644 index 000000000..518f28071 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190.sch @@ -0,0 +1,1415 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 1 1 699468DE +P 13850 4650 +F 0 "X1" H 13950 4600 60 0000 C CNN +F 1 "3_and" H 14000 4800 60 0000 C CNN +F 2 "" H 13850 4650 60 0000 C CNN +F 3 "" H 13850 4650 60 0000 C CNN + 1 13850 4650 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X2 +U 1 1 69946902 +P 13850 5200 +F 0 "X2" H 13950 5150 60 0000 C CNN +F 1 "3_and" H 14000 5350 60 0000 C CNN +F 2 "" H 13850 5200 60 0000 C CNN +F 3 "" H 13850 5200 60 0000 C CNN + 1 13850 5200 + 1 0 0 -1 +$EndComp +$Comp +L d_or U17 +U 1 1 6994696B +P 15300 4950 +F 0 "U17" H 15300 4950 60 0000 C CNN +F 1 "d_or" H 15300 5050 60 0000 C CNN +F 2 "" H 15300 4950 60 0000 C CNN +F 3 "" H 15300 4950 60 0000 C CNN + 1 15300 4950 + 1 0 0 -1 +$EndComp +$Comp +L 3_and X3 +U 1 1 699469D7 +P 13850 5650 +F 0 "X3" H 13950 5600 60 0000 C CNN +F 1 "3_and" H 14000 5800 60 0000 C CNN +F 2 "" H 13850 5650 60 0000 C CNN +F 3 "" H 13850 5650 60 0000 C CNN + 1 13850 5650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14350 5150 14350 5350 +Wire Wire Line + 14350 5350 13350 5350 +Wire Wire Line + 13350 5350 13350 5500 +Wire Wire Line + 13350 5500 13500 5500 +Wire Wire Line + 14850 4950 14850 5600 +Wire Wire Line + 14850 5600 14350 5600 +Wire Wire Line + 14350 4600 14850 4600 +Wire Wire Line + 14850 4600 14850 4850 +$Comp +L d_nand U10 +U 1 1 69946A99 +P 13900 6300 +F 0 "U10" H 13900 6300 60 0000 C CNN +F 1 "d_nand" H 13950 6400 60 0000 C CNN +F 2 "" H 13900 6300 60 0000 C CNN +F 3 "" H 13900 6300 60 0000 C CNN + 1 13900 6300 + 1 0 0 -1 +$EndComp +$Comp +L d_jkff U32 +U 1 1 69946C2C +P 19350 6000 +F 0 "U32" H 19350 6000 60 0000 C CNN +F 1 "d_jkff" H 19400 6150 60 0000 C CNN +F 2 "" H 19350 6000 60 0000 C CNN +F 3 "" H 19350 6000 60 0000 C CNN + 1 19350 6000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U33 +U 1 1 69946CCF +P 19350 7250 +F 0 "U33" H 19350 7150 60 0000 C CNN +F 1 "d_inverter" H 19350 7400 60 0000 C CNN +F 2 "" H 19400 7200 60 0000 C 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5200 60 0000 C CNN +F 3 "" H 2100 5200 60 0000 C CNN + 8 2100 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 69982EAD +P 7050 16050 +F 0 "U1" H 7100 16150 30 0000 C CNN +F 1 "PORT" H 7050 16050 30 0000 C CNN +F 2 "" H 7050 16050 60 0000 C CNN +F 3 "" H 7050 16050 60 0000 C CNN + 9 7050 16050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 69982F3C +P 9550 3650 +F 0 "U1" H 9600 3750 30 0000 C CNN +F 1 "PORT" H 9550 3650 30 0000 C CNN +F 2 "" H 9550 3650 60 0000 C CNN +F 3 "" H 9550 3650 60 0000 C CNN + 14 9550 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 69983181 +P 7700 12650 +F 0 "U1" H 7750 12750 30 0000 C CNN +F 1 "PORT" H 7700 12650 30 0000 C CNN +F 2 "" H 7700 12650 60 0000 C CNN +F 3 "" H 7700 12650 60 0000 C CNN + 10 7700 12650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 69983214 +P 7400 19450 +F 0 "U1" H 7450 19550 30 0000 C CNN +F 1 "PORT" H 7400 19450 30 0000 C CNN +F 2 "" H 7400 19450 60 0000 C CNN +F 3 "" H 7400 19450 60 0000 C CNN + 11 7400 19450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 699832A9 +P 21050 4350 +F 0 "U1" H 21100 4450 30 0000 C CNN +F 1 "PORT" H 21050 4350 30 0000 C CNN +F 2 "" H 21050 4350 60 0000 C CNN +F 3 "" H 21050 4350 60 0000 C CNN + 12 21050 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 699833C2 +P 8000 6500 +F 0 "U1" H 8050 6600 30 0000 C CNN +F 1 "PORT" H 8000 6500 30 0000 C CNN +F 2 "" H 8000 6500 60 0000 C CNN +F 3 "" H 8000 6500 60 0000 C CNN + 15 8000 6500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 699834F1 +P 21300 4200 +F 0 "U1" H 21350 4300 30 0000 C CNN +F 1 "PORT" H 21300 4200 30 0000 C CNN +F 2 "" H 21300 4200 60 0000 C CNN +F 3 "" H 21300 4200 60 0000 C CNN + 13 21300 4200 + -1 0 0 1 +$EndComp +Wire Wire Line + 7650 19450 7900 19450 +Wire Wire Line + 9800 3650 9900 3650 +Wire Wire Line + 9800 4300 9900 4300 +NoConn ~ 2350 5200 +$Comp +L PORT U1 +U 16 1 69994509 +P 4150 4300 +F 0 "U1" H 4200 4400 30 0000 C CNN +F 1 "PORT" H 4150 4300 30 0000 C CNN +F 2 "" H 4150 4300 60 0000 C CNN +F 3 "" H 4150 4300 60 0000 C CNN + 16 4150 4300 + 1 0 0 -1 +$EndComp +NoConn ~ 4400 4300 +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190.sub b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190.sub new file mode 100644 index 000000000..8b262d40e --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190.sub @@ -0,0 +1,186 @@ +* Subcircuit SN54190 +.subckt SN54190 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn54190\sn54190.cir +.include 3_and.sub +.include 4_and.sub +x1 net-_u4-pad2_ net-_u1-pad3_ net-_u1-pad7_ net-_u17-pad1_ 3_and +x2 net-_u3-pad1_ net-_u32-pad7_ net-_u35-pad7_ net-_x2-pad4_ 3_and +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u1-pad12_ d_or +x3 net-_x2-pad4_ net-_u38-pad7_ net-_u15-pad2_ net-_u17-pad2_ 3_and +* u10 net-_u1-pad15_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u32 net-_u22-pad2_ net-_u22-pad2_ net-_u26-pad2_ net-_u31-pad2_ net-_u32-pad5_ net-_u1-pad3_ net-_u32-pad7_ d_jkff +* u33 net-_u16-pad3_ net-_u32-pad5_ d_inverter +* u31 net-_u10-pad3_ net-_u31-pad2_ d_inverter +* u9 net-_u1-pad4_ net-_u22-pad2_ d_inverter +* u16 net-_u10-pad3_ net-_u10-pad2_ net-_u16-pad3_ d_nand +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_nand +* u43 net-_u30-pad3_ net-_u1-pad12_ net-_u1-pad13_ d_nand +* u30 net-_u22-pad3_ net-_u22-pad3_ net-_u30-pad3_ d_nand +* u26 net-_u22-pad1_ net-_u26-pad2_ d_inverter +* u5 net-_u1-pad14_ net-_u22-pad1_ d_inverter +* u6 net-_u1-pad5_ net-_u4-pad2_ d_inverter +* u7 net-_u4-pad2_ net-_u3-pad1_ d_inverter +* u3 net-_u3-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_nor +* u4 net-_u1-pad4_ net-_u4-pad2_ net-_u4-pad3_ d_nor +* u38 net-_u19-pad3_ net-_u19-pad3_ net-_u28-pad2_ net-_u37-pad2_ net-_u38-pad5_ net-_u1-pad6_ net-_u38-pad7_ d_jkff +* u39 net-_u24-pad3_ net-_u38-pad5_ d_inverter +* u37 net-_u13-pad3_ net-_u37-pad2_ d_inverter +* u28 net-_u22-pad1_ net-_u28-pad2_ d_inverter +* u24 net-_u13-pad3_ net-_u10-pad2_ net-_u24-pad3_ d_nand +* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_or +* u35 net-_u18-pad3_ net-_u18-pad3_ net-_u27-pad2_ net-_u34-pad2_ net-_u35-pad5_ net-_u1-pad2_ net-_u35-pad7_ d_jkff +* u36 net-_u23-pad3_ net-_u35-pad5_ d_inverter +* u34 net-_u12-pad3_ net-_u34-pad2_ d_inverter +* u27 net-_u22-pad1_ net-_u27-pad2_ d_inverter +* u23 net-_u12-pad3_ net-_u10-pad2_ net-_u23-pad3_ d_nand +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_or +* u41 net-_u20-pad3_ net-_u20-pad3_ net-_u29-pad2_ net-_u40-pad2_ net-_u41-pad5_ net-_u1-pad7_ net-_u15-pad2_ d_jkff +* u42 net-_u25-pad3_ net-_u41-pad5_ d_inverter +* u40 net-_u14-pad3_ net-_u40-pad2_ d_inverter +* u29 net-_u22-pad1_ net-_u29-pad2_ d_inverter +* u25 net-_u14-pad3_ net-_u10-pad2_ net-_u25-pad3_ d_nand +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u20-pad1_ d_or +* u12 net-_u1-pad1_ net-_u10-pad2_ net-_u12-pad3_ d_nand +x4 net-_u4-pad3_ net-_u32-pad7_ net-_u15-pad3_ net-_u18-pad1_ 3_and +x5 net-_u1-pad3_ net-_u15-pad2_ net-_u3-pad3_ net-_u18-pad2_ 3_and +* u8 net-_u35-pad7_ net-_u38-pad7_ net-_u11-pad1_ d_nand +* u15 net-_u11-pad3_ net-_u15-pad2_ net-_u15-pad3_ d_nand +* u11 net-_u11-pad1_ net-_u11-pad1_ net-_u11-pad3_ d_nand +* u13 net-_u1-pad10_ net-_u10-pad2_ net-_u13-pad3_ d_nand +x7 net-_u15-pad3_ net-_u4-pad3_ net-_u32-pad7_ net-_u35-pad7_ net-_u19-pad1_ 4_and +* u14 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ d_nand +x9 net-_u4-pad3_ net-_u32-pad7_ net-_u35-pad7_ net-_u38-pad7_ net-_u21-pad1_ 4_and +x6 net-_u1-pad3_ net-_u1-pad7_ net-_u3-pad3_ net-_u21-pad2_ 3_and +x10 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u3-pad3_ net-_u20-pad2_ 4_and +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u20-pad3_ d_or +* u2 net-_u1-pad11_ net-_u10-pad2_ d_inverter +x8 net-_u1-pad3_ net-_u1-pad2_ net-_u3-pad3_ net-_u19-pad2_ 3_and +a1 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u1-pad12_ u17 +a2 [net-_u1-pad15_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a3 net-_u22-pad2_ net-_u22-pad2_ net-_u26-pad2_ net-_u31-pad2_ net-_u32-pad5_ net-_u1-pad3_ net-_u32-pad7_ u32 +a4 net-_u16-pad3_ net-_u32-pad5_ u33 +a5 net-_u10-pad3_ net-_u31-pad2_ u31 +a6 net-_u1-pad4_ net-_u22-pad2_ u9 +a7 [net-_u10-pad3_ net-_u10-pad2_ ] net-_u16-pad3_ u16 +a8 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a9 [net-_u30-pad3_ net-_u1-pad12_ ] net-_u1-pad13_ u43 +a10 [net-_u22-pad3_ net-_u22-pad3_ ] net-_u30-pad3_ u30 +a11 net-_u22-pad1_ net-_u26-pad2_ u26 +a12 net-_u1-pad14_ net-_u22-pad1_ u5 +a13 net-_u1-pad5_ net-_u4-pad2_ u6 +a14 net-_u4-pad2_ net-_u3-pad1_ u7 +a15 [net-_u3-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a16 [net-_u1-pad4_ net-_u4-pad2_ ] net-_u4-pad3_ u4 +a17 net-_u19-pad3_ net-_u19-pad3_ net-_u28-pad2_ net-_u37-pad2_ net-_u38-pad5_ net-_u1-pad6_ net-_u38-pad7_ u38 +a18 net-_u24-pad3_ net-_u38-pad5_ u39 +a19 net-_u13-pad3_ net-_u37-pad2_ u37 +a20 net-_u22-pad1_ net-_u28-pad2_ u28 +a21 [net-_u13-pad3_ net-_u10-pad2_ ] net-_u24-pad3_ u24 +a22 [net-_u19-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a23 net-_u18-pad3_ net-_u18-pad3_ net-_u27-pad2_ net-_u34-pad2_ net-_u35-pad5_ net-_u1-pad2_ net-_u35-pad7_ u35 +a24 net-_u23-pad3_ net-_u35-pad5_ u36 +a25 net-_u12-pad3_ net-_u34-pad2_ u34 +a26 net-_u22-pad1_ net-_u27-pad2_ u27 +a27 [net-_u12-pad3_ net-_u10-pad2_ ] net-_u23-pad3_ u23 +a28 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a29 net-_u20-pad3_ net-_u20-pad3_ net-_u29-pad2_ net-_u40-pad2_ net-_u41-pad5_ net-_u1-pad7_ net-_u15-pad2_ u41 +a30 net-_u25-pad3_ net-_u41-pad5_ u42 +a31 net-_u14-pad3_ net-_u40-pad2_ u40 +a32 net-_u22-pad1_ net-_u29-pad2_ u29 +a33 [net-_u14-pad3_ net-_u10-pad2_ ] net-_u25-pad3_ u25 +a34 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u20-pad1_ u21 +a35 [net-_u1-pad1_ net-_u10-pad2_ ] net-_u12-pad3_ u12 +a36 [net-_u35-pad7_ net-_u38-pad7_ ] net-_u11-pad1_ u8 +a37 [net-_u11-pad3_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a38 [net-_u11-pad1_ net-_u11-pad1_ ] net-_u11-pad3_ u11 +a39 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u13-pad3_ u13 +a40 [net-_u1-pad9_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a41 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a42 net-_u1-pad11_ net-_u10-pad2_ u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u32 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u38 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u35 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u41 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN54190 \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190_Previous_Values.xml new file mode 100644 index 000000000..ac42ee323 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/SN54190_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_nandd_jkffd_inverterd_inverterd_inverterd_nandd_nandd_nandd_nandd_inverterd_inverterd_inverterd_inverterd_nord_nord_jkffd_inverterd_inverterd_inverterd_nandd_ord_jkffd_inverterd_inverterd_inverterd_nandd_ord_jkffd_inverterd_inverterd_inverterd_nandd_ord_nandd_nandd_nandd_nandd_nandd_nandd_ord_inverterC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/analysis b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN54190/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/NPN.lib b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189-cache.lib new file mode 100644 index 000000000..d900cc5d9 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189-cache.lib @@ -0,0 +1,128 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS capacitor_polarised +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189.cir b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189.cir new file mode 100644 index 000000000..47b81d862 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189.cir @@ -0,0 +1,87 @@ +* C:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\SN55189\SN55189.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/20/26 18:15:45 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_D4-Pad2_ Net-_D2-Pad2_ GND eSim_NPN +D4 Net-_D2-Pad2_ Net-_D4-Pad2_ eSim_Diode +Q4 Net-_D6-Pad2_ Net-_D4-Pad2_ GND eSim_NPN +D6 Net-_D4-Pad2_ Net-_D6-Pad2_ eSim_Diode +Q6 Net-_C2-Pad1_ Net-_D6-Pad2_ GND eSim_NPN +D8 Net-_D6-Pad2_ Net-_C2-Pad1_ eSim_Diode +R2 Net-_R2-Pad1_ Net-_D2-Pad2_ 4k +D2 GND Net-_D2-Pad2_ eSim_Diode +R5 Net-_D2-Pad2_ GND 10k +R6 Net-_D2-Pad2_ Net-_D6-Pad2_ 8.4k +R8 VCC Net-_D4-Pad2_ 9k +R10 VCC Net-_D6-Pad2_ 5k +R12 VCC Net-_C2-Pad1_ 1.66k +C2 Net-_C2-Pad1_ GND 15pF +D10 Net-_D10-Pad1_ Net-_C2-Pad1_ eSim_Diode +D12 Net-_D10-Pad1_ Net-_D12-Pad2_ eSim_Diode +D14 Net-_D12-Pad2_ Net-_D14-Pad2_ eSim_Diode +D17 Net-_D14-Pad2_ GND eSim_Diode +R14 VCC Net-_D10-Pad1_ 3.9k +Q1 Net-_D3-Pad2_ Net-_D1-Pad2_ GND eSim_NPN +D3 Net-_D1-Pad2_ Net-_D3-Pad2_ eSim_Diode +Q3 Net-_D5-Pad2_ Net-_D3-Pad2_ GND eSim_NPN +D5 Net-_D3-Pad2_ Net-_D5-Pad2_ eSim_Diode +Q5 Net-_C1-Pad1_ Net-_D5-Pad2_ GND eSim_NPN +D7 Net-_D5-Pad2_ Net-_C1-Pad1_ eSim_Diode +R1 Net-_R1-Pad1_ Net-_D1-Pad2_ 4k +D1 GND Net-_D1-Pad2_ eSim_Diode +R3 Net-_D1-Pad2_ GND 10k +R4 Net-_D1-Pad2_ Net-_D5-Pad2_ 8.4k +R7 VCC Net-_D3-Pad2_ 9k +R9 VCC Net-_D5-Pad2_ 5k +R11 VCC Net-_C1-Pad1_ 1.66k +C1 Net-_C1-Pad1_ GND 15pF +D9 Net-_D11-Pad1_ Net-_C1-Pad1_ eSim_Diode +D11 Net-_D11-Pad1_ Net-_D11-Pad2_ eSim_Diode +D13 Net-_D11-Pad2_ Net-_D13-Pad2_ eSim_Diode +D15 Net-_D13-Pad2_ GND eSim_Diode +R13 VCC Net-_D11-Pad1_ 3.9k +Q8 Net-_D20-Pad2_ Net-_D18-Pad2_ GND eSim_NPN +D20 Net-_D18-Pad2_ Net-_D20-Pad2_ eSim_Diode +Q10 Net-_D22-Pad2_ Net-_D20-Pad2_ GND eSim_NPN +D22 Net-_D20-Pad2_ Net-_D22-Pad2_ eSim_Diode +Q12 Net-_C4-Pad1_ Net-_D22-Pad2_ GND eSim_NPN +D24 Net-_D22-Pad2_ Net-_C4-Pad1_ eSim_Diode +R16 Net-_R16-Pad1_ Net-_D18-Pad2_ 4k +D18 GND Net-_D18-Pad2_ eSim_Diode +R19 Net-_D18-Pad2_ GND 10k +R20 Net-_D18-Pad2_ Net-_D22-Pad2_ 8.4k +R22 VCC Net-_D20-Pad2_ 9k +R24 VCC Net-_D22-Pad2_ 5k +R26 VCC Net-_C4-Pad1_ 1.66k +C4 Net-_C4-Pad1_ GND 15pF +D26 Net-_D26-Pad1_ Net-_C4-Pad1_ eSim_Diode +D28 Net-_D26-Pad1_ Net-_D28-Pad2_ eSim_Diode +D30 Net-_D28-Pad2_ Net-_D30-Pad2_ eSim_Diode +D32 Net-_D30-Pad2_ GND eSim_Diode +R28 VCC Net-_D26-Pad1_ 3.9k +Q7 Net-_D19-Pad2_ Net-_D16-Pad2_ GND eSim_NPN +D19 Net-_D16-Pad2_ Net-_D19-Pad2_ eSim_Diode +Q9 Net-_D21-Pad2_ Net-_D19-Pad2_ GND eSim_NPN +D21 Net-_D19-Pad2_ Net-_D21-Pad2_ eSim_Diode +Q11 Net-_C3-Pad1_ Net-_D21-Pad2_ GND eSim_NPN +D23 Net-_D21-Pad2_ Net-_C3-Pad1_ eSim_Diode +R15 Net-_R15-Pad1_ Net-_D16-Pad2_ 4k +D16 GND Net-_D16-Pad2_ eSim_Diode +R17 Net-_D16-Pad2_ GND 10k +R18 Net-_D16-Pad2_ Net-_D21-Pad2_ 8.4k +R21 VCC Net-_D19-Pad2_ 9k +R23 VCC Net-_D21-Pad2_ 5k +R25 VCC Net-_C3-Pad1_ 1.66k +C3 Net-_C3-Pad1_ GND 15pF +D25 Net-_D25-Pad1_ Net-_C3-Pad1_ eSim_Diode +D27 Net-_D25-Pad1_ Net-_D27-Pad2_ eSim_Diode +D29 Net-_D27-Pad2_ Net-_D29-Pad2_ eSim_Diode +D31 Net-_D29-Pad2_ GND eSim_Diode +R27 VCC Net-_D25-Pad1_ 3.9k +U1 Net-_R2-Pad1_ ? Net-_C2-Pad1_ Net-_R1-Pad1_ ? Net-_C1-Pad1_ GND Net-_C4-Pad1_ ? Net-_R16-Pad1_ Net-_C3-Pad1_ ? Net-_R15-Pad1_ VCC PORT + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189.cir.out new file mode 100644 index 000000000..762e48679 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189.cir.out @@ -0,0 +1,90 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn55189\sn55189.cir + +.include NPN.lib +.include schottky.lib +q2 net-_d4-pad2_ net-_d2-pad2_ gnd Q2N2222 +d4 net-_d2-pad2_ net-_d4-pad2_ 1N5819 +q4 net-_d6-pad2_ net-_d4-pad2_ gnd Q2N2222 +d6 net-_d4-pad2_ net-_d6-pad2_ 1N5819 +q6 net-_c2-pad1_ net-_d6-pad2_ gnd Q2N2222 +d8 net-_d6-pad2_ net-_c2-pad1_ 1N5819 +r2 net-_r2-pad1_ net-_d2-pad2_ 4k +d2 gnd net-_d2-pad2_ 1N5819 +r5 net-_d2-pad2_ gnd 10k +r6 net-_d2-pad2_ net-_d6-pad2_ 8.4k +r8 vcc net-_d4-pad2_ 9k +r10 vcc net-_d6-pad2_ 5k +r12 vcc net-_c2-pad1_ 1.66k +c2 net-_c2-pad1_ gnd 15pf +d10 net-_d10-pad1_ net-_c2-pad1_ 1N5819 +d12 net-_d10-pad1_ net-_d12-pad2_ 1N5819 +d14 net-_d12-pad2_ net-_d14-pad2_ 1N5819 +d17 net-_d14-pad2_ gnd 1N5819 +r14 vcc net-_d10-pad1_ 3.9k +q1 net-_d3-pad2_ net-_d1-pad2_ gnd Q2N2222 +d3 net-_d1-pad2_ net-_d3-pad2_ 1N5819 +q3 net-_d5-pad2_ net-_d3-pad2_ gnd Q2N2222 +d5 net-_d3-pad2_ net-_d5-pad2_ 1N5819 +q5 net-_c1-pad1_ net-_d5-pad2_ gnd Q2N2222 +d7 net-_d5-pad2_ net-_c1-pad1_ 1N5819 +r1 net-_r1-pad1_ net-_d1-pad2_ 4k +d1 gnd net-_d1-pad2_ 1N5819 +r3 net-_d1-pad2_ gnd 10k +r4 net-_d1-pad2_ net-_d5-pad2_ 8.4k +r7 vcc net-_d3-pad2_ 9k +r9 vcc net-_d5-pad2_ 5k +r11 vcc net-_c1-pad1_ 1.66k +c1 net-_c1-pad1_ gnd 15pf +d9 net-_d11-pad1_ net-_c1-pad1_ 1N5819 +d11 net-_d11-pad1_ net-_d11-pad2_ 1N5819 +d13 net-_d11-pad2_ net-_d13-pad2_ 1N5819 +d15 net-_d13-pad2_ gnd 1N5819 +r13 vcc net-_d11-pad1_ 3.9k +q8 net-_d20-pad2_ net-_d18-pad2_ gnd Q2N2222 +d20 net-_d18-pad2_ net-_d20-pad2_ 1N5819 +q10 net-_d22-pad2_ net-_d20-pad2_ gnd Q2N2222 +d22 net-_d20-pad2_ net-_d22-pad2_ 1N5819 +q12 net-_c4-pad1_ net-_d22-pad2_ gnd Q2N2222 +d24 net-_d22-pad2_ net-_c4-pad1_ 1N5819 +r16 net-_r16-pad1_ net-_d18-pad2_ 4k +d18 gnd net-_d18-pad2_ 1N5819 +r19 net-_d18-pad2_ gnd 10k +r20 net-_d18-pad2_ net-_d22-pad2_ 8.4k +r22 vcc net-_d20-pad2_ 9k +r24 vcc net-_d22-pad2_ 5k +r26 vcc net-_c4-pad1_ 1.66k +c4 net-_c4-pad1_ gnd 15pf +d26 net-_d26-pad1_ net-_c4-pad1_ 1N5819 +d28 net-_d26-pad1_ net-_d28-pad2_ 1N5819 +d30 net-_d28-pad2_ net-_d30-pad2_ 1N5819 +d32 net-_d30-pad2_ gnd 1N5819 +r28 vcc net-_d26-pad1_ 3.9k +q7 net-_d19-pad2_ net-_d16-pad2_ gnd Q2N2222 +d19 net-_d16-pad2_ net-_d19-pad2_ 1N5819 +q9 net-_d21-pad2_ net-_d19-pad2_ gnd Q2N2222 +d21 net-_d19-pad2_ net-_d21-pad2_ 1N5819 +q11 net-_c3-pad1_ net-_d21-pad2_ gnd Q2N2222 +d23 net-_d21-pad2_ net-_c3-pad1_ 1N5819 +r15 net-_r15-pad1_ net-_d16-pad2_ 4k +d16 gnd net-_d16-pad2_ 1N5819 +r17 net-_d16-pad2_ gnd 10k +r18 net-_d16-pad2_ net-_d21-pad2_ 8.4k +r21 vcc net-_d19-pad2_ 9k +r23 vcc net-_d21-pad2_ 5k +r25 vcc net-_c3-pad1_ 1.66k +c3 net-_c3-pad1_ gnd 15pf +d25 net-_d25-pad1_ net-_c3-pad1_ 1N5819 +d27 net-_d25-pad1_ net-_d27-pad2_ 1N5819 +d29 net-_d27-pad2_ net-_d29-pad2_ 1N5819 +d31 net-_d29-pad2_ gnd 1N5819 +r27 vcc net-_d25-pad1_ 3.9k +* u1 net-_r2-pad1_ ? net-_c2-pad1_ net-_r1-pad1_ ? net-_c1-pad1_ gnd net-_c4-pad1_ ? net-_r16-pad1_ net-_c3-pad1_ ? net-_r15-pad1_ vcc port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189.pro b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189.sch b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189.sch new file mode 100644 index 000000000..c1c096665 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189.sch @@ -0,0 +1,1598 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q2 +U 1 1 6998530F +P 6900 5200 +F 0 "Q2" H 6800 5250 50 0000 R CNN +F 1 "eSim_NPN" H 6850 5350 50 0000 R CNN +F 2 "" H 7100 5300 29 0000 C CNN +F 3 "" H 6900 5200 60 0000 C CNN + 1 6900 5200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 6998536D +P 6350 5050 +F 0 "D4" H 6350 5150 50 0000 C CNN +F 1 "eSim_Diode" H 6350 4950 50 0000 C CNN +F 2 "" H 6350 5050 60 0000 C CNN +F 3 "" H 6350 5050 60 0000 C CNN + 1 6350 5050 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6350 4900 6350 4850 +Wire Wire Line + 6350 4850 7000 4850 +Wire Wire Line + 7000 3450 7000 5000 +Wire Wire Line + 6350 5200 6350 5250 +Wire Wire Line + 5300 5250 6700 5250 +Wire Wire Line + 6700 5250 6700 5200 +Connection ~ 6350 5250 +Connection ~ 7000 4850 +$Comp +L eSim_NPN Q4 +U 1 1 69985459 +P 8200 4400 +F 0 "Q4" H 8100 4450 50 0000 R CNN +F 1 "eSim_NPN" H 8150 4550 50 0000 R CNN +F 2 "" H 8400 4500 29 0000 C CNN +F 3 "" H 8200 4400 60 0000 C CNN + 1 8200 4400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 6998545F +P 7650 4250 +F 0 "D6" H 7650 4350 50 0000 C CNN +F 1 "eSim_Diode" H 7650 4150 50 0000 C CNN +F 2 "" H 7650 4250 60 0000 C CNN +F 3 "" H 7650 4250 60 0000 C CNN + 1 7650 4250 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7650 4100 7650 4050 +Wire Wire Line + 7650 4050 8300 4050 +Wire Wire Line + 8300 3650 8300 4200 +Wire Wire Line + 7650 4400 7650 4450 +Wire Wire Line + 7000 4450 8000 4450 +Wire Wire Line + 8000 4450 8000 4400 +Connection ~ 7650 4450 +Connection ~ 8300 4050 +$Comp +L eSim_NPN Q6 +U 1 1 699854A7 +P 9550 3650 +F 0 "Q6" H 9450 3700 50 0000 R CNN +F 1 "eSim_NPN" H 9500 3800 50 0000 R CNN +F 2 "" H 9750 3750 29 0000 C CNN +F 3 "" H 9550 3650 60 0000 C CNN + 1 9550 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D8 +U 1 1 699854AD +P 9000 3500 +F 0 "D8" H 9000 3600 50 0000 C CNN +F 1 "eSim_Diode" H 9000 3400 50 0000 C CNN +F 2 "" H 9000 3500 60 0000 C CNN +F 3 "" H 9000 3500 60 0000 C CNN + 1 9000 3500 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 9000 3350 9000 3300 +Wire Wire Line + 9000 3300 9650 3300 +Wire Wire Line + 9650 3150 9650 3450 +Wire Wire Line + 9000 3650 9000 3700 +Wire Wire Line + 8750 3700 9350 3700 +Wire Wire Line + 9350 3700 9350 3650 +Connection ~ 9000 3700 +Connection ~ 9650 3300 +$Comp +L resistor R2 +U 1 1 699854F9 +P 5100 5300 +F 0 "R2" H 5150 5430 50 0000 C CNN +F 1 "4k" H 5150 5250 50 0000 C CNN +F 2 "" H 5150 5280 30 0000 C CNN +F 3 "" V 5150 5350 30 0000 C CNN + 1 5100 5300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 699855A7 +P 5450 5600 +F 0 "D2" H 5450 5700 50 0000 C CNN +F 1 "eSim_Diode" H 5450 5500 50 0000 C CNN +F 2 "" H 5450 5600 60 0000 C CNN +F 3 "" H 5450 5600 60 0000 C CNN + 1 5450 5600 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 699855E1 +P 5800 5550 +F 0 "R5" H 5850 5680 50 0000 C CNN +F 1 "10k" H 5850 5500 50 0000 C CNN +F 2 "" H 5850 5530 30 0000 C CNN +F 3 "" V 5850 5600 30 0000 C CNN + 1 5800 5550 + 0 1 1 0 +$EndComp +Wire Wire Line + 5450 5450 5450 5250 +Connection ~ 5450 5250 +Wire Wire Line + 5850 5450 5850 5250 +Connection ~ 5850 5250 +$Comp +L resistor R6 +U 1 1 699856A5 +P 6100 3700 +F 0 "R6" H 6150 3830 50 0000 C CNN +F 1 "8.4k" H 6150 3650 50 0000 C CNN +F 2 "" H 6150 3680 30 0000 C CNN +F 3 "" V 6150 3750 30 0000 C CNN + 1 6100 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8750 3650 8750 3700 +Connection ~ 8300 3650 +Wire Wire Line + 6300 3650 8750 3650 +Wire Wire Line + 6000 3650 5700 3650 +Wire Wire Line + 5700 3650 5700 5250 +Connection ~ 5700 5250 +$Comp +L resistor R8 +U 1 1 69985AA2 +P 6950 3250 +F 0 "R8" H 7000 3380 50 0000 C CNN +F 1 "9k" H 7000 3200 50 0000 C CNN +F 2 "" H 7000 3230 30 0000 C CNN +F 3 "" V 7000 3300 30 0000 C CNN + 1 6950 3250 + 0 1 1 0 +$EndComp +Connection ~ 7000 4450 +$Comp +L resistor R10 +U 1 1 69985C6D +P 7550 3250 +F 0 "R10" H 7600 3380 50 0000 C CNN +F 1 "5k" H 7600 3200 50 0000 C CNN +F 2 "" H 7600 3230 30 0000 C CNN +F 3 "" V 7600 3300 30 0000 C CNN + 1 7550 3250 + 0 1 1 0 +$EndComp +Wire Wire Line + 7600 3450 7600 3650 +Connection ~ 7600 3650 +$Comp +L resistor R12 +U 1 1 69985CF0 +P 9600 2950 +F 0 "R12" H 9650 3080 50 0000 C CNN +F 1 "1.66k" H 9650 2900 50 0000 C CNN +F 2 "" H 9650 2930 30 0000 C CNN +F 3 "" V 9650 3000 30 0000 C CNN + 1 9600 2950 + 0 1 1 0 +$EndComp +Wire Wire Line + 7000 3150 7000 2700 +Wire Wire Line + 7000 2700 10300 2700 +Wire Wire Line + 9650 2850 9650 2700 +Connection ~ 9650 2700 +Wire Wire Line + 7600 3150 7600 2700 +Connection ~ 7600 2700 +Wire Wire Line + 9650 3400 10250 3400 +Connection ~ 9650 3400 +Wire Wire Line + 5450 5750 5450 5900 +Wire Wire Line + 5450 5900 9600 5900 +Wire Wire Line + 9600 5900 9600 3850 +Wire Wire Line + 9600 3850 9650 3850 +Wire Wire Line + 8300 4600 8300 5900 +Connection ~ 8300 5900 +Wire Wire Line + 7000 5400 7000 5900 +Connection ~ 7000 5900 +Wire Wire Line + 5850 5750 5850 5900 +Connection ~ 5850 5900 +Wire Wire Line + 5000 5250 4700 5250 +$Comp +L capacitor_polarised C2 +U 1 1 699866AB +P 10050 3700 +F 0 "C2" H 10075 3800 50 0000 L CNN +F 1 "15pF" H 10075 3600 50 0000 L CNN +F 2 "" H 10050 3700 50 0001 C CNN +F 3 "" H 10050 3700 50 0001 C CNN + 1 10050 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10050 3550 10050 3400 +Connection ~ 10050 3400 +$Comp +L eSim_Diode D10 +U 1 1 699867A2 +P 10400 3400 +F 0 "D10" H 10400 3500 50 0000 C CNN +F 1 "eSim_Diode" H 10400 3300 50 0000 C CNN +F 2 "" H 10400 3400 60 0000 C CNN +F 3 "" H 10400 3400 60 0000 C CNN + 1 10400 3400 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D12 +U 1 1 69986840 +P 11000 3400 +F 0 "D12" H 11000 3500 50 0000 C CNN +F 1 "eSim_Diode" H 11000 3300 50 0000 C CNN +F 2 "" H 11000 3400 60 0000 C CNN +F 3 "" H 11000 3400 60 0000 C CNN + 1 11000 3400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D14 +U 1 1 6998688C +P 11450 3400 +F 0 "D14" H 11450 3500 50 0000 C CNN +F 1 "eSim_Diode" H 11450 3300 50 0000 C CNN +F 2 "" H 11450 3400 60 0000 C CNN +F 3 "" H 11450 3400 60 0000 C CNN + 1 11450 3400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D17 +U 1 1 699868D7 +P 11900 3400 +F 0 "D17" H 11900 3500 50 0000 C CNN +F 1 "eSim_Diode" H 11900 3300 50 0000 C CNN +F 2 "" H 11900 3400 60 0000 C CNN +F 3 "" H 11900 3400 60 0000 C CNN + 1 11900 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11150 3400 11300 3400 +Wire Wire Line + 11600 3400 11750 3400 +Wire Wire Line + 12050 3400 12300 3400 +Wire Wire Line + 12300 3400 12300 3800 +Wire Wire Line + 10550 3400 10850 3400 +Wire Wire Line + 10050 2700 10050 2950 +Wire Wire Line + 10050 2950 10700 2950 +Connection ~ 10050 2700 +$Comp +L resistor R14 +U 1 1 69986C1D +P 10650 3100 +F 0 "R14" H 10700 3230 50 0000 C CNN +F 1 "3.9k" H 10700 3050 50 0000 C CNN +F 2 "" H 10700 3080 30 0000 C CNN +F 3 "" V 10700 3150 30 0000 C CNN + 1 10650 3100 + 0 1 1 0 +$EndComp +Wire Wire Line + 10700 2950 10700 3000 +Wire Wire Line + 10700 3300 10700 3400 +Connection ~ 10700 3400 +Wire Wire Line + 7650 6000 7650 5900 +Connection ~ 7650 5900 +Wire Wire Line + 10050 3850 10050 3950 +Wire Wire Line + 9850 3400 9850 4150 +Wire Wire Line + 9850 4150 10300 4150 +Connection ~ 9850 3400 +$Comp +L eSim_NPN Q1 +U 1 1 69987A24 +P 6450 9900 +F 0 "Q1" H 6350 9950 50 0000 R CNN +F 1 "eSim_NPN" H 6400 10050 50 0000 R CNN +F 2 "" H 6650 10000 29 0000 C CNN +F 3 "" H 6450 9900 60 0000 C CNN + 1 6450 9900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 69987A2A +P 5900 9750 +F 0 "D3" H 5900 9850 50 0000 C CNN +F 1 "eSim_Diode" H 5900 9650 50 0000 C CNN +F 2 "" H 5900 9750 60 0000 C CNN +F 3 "" H 5900 9750 60 0000 C CNN + 1 5900 9750 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5900 9600 5900 9550 +Wire Wire Line + 5900 9550 6550 9550 +Wire Wire Line + 6550 8150 6550 9700 +Wire Wire Line + 5900 9900 5900 9950 +Wire Wire Line + 4850 9950 6250 9950 +Wire Wire Line + 6250 9950 6250 9900 +Connection ~ 5900 9950 +Connection ~ 6550 9550 +$Comp +L eSim_NPN Q3 +U 1 1 69987A38 +P 7750 9100 +F 0 "Q3" H 7650 9150 50 0000 R CNN +F 1 "eSim_NPN" H 7700 9250 50 0000 R CNN +F 2 "" H 7950 9200 29 0000 C CNN +F 3 "" H 7750 9100 60 0000 C CNN + 1 7750 9100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 69987A3E +P 7200 8950 +F 0 "D5" H 7200 9050 50 0000 C CNN +F 1 "eSim_Diode" H 7200 8850 50 0000 C CNN +F 2 "" H 7200 8950 60 0000 C CNN +F 3 "" H 7200 8950 60 0000 C CNN + 1 7200 8950 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7200 8800 7200 8750 +Wire Wire Line + 7200 8750 7850 8750 +Wire Wire Line + 7850 8350 7850 8900 +Wire Wire Line + 7200 9100 7200 9150 +Wire Wire Line + 6550 9150 7550 9150 +Wire Wire Line + 7550 9150 7550 9100 +Connection ~ 7200 9150 +Connection ~ 7850 8750 +$Comp +L eSim_NPN Q5 +U 1 1 69987A4C +P 9100 8350 +F 0 "Q5" H 9000 8400 50 0000 R CNN +F 1 "eSim_NPN" H 9050 8500 50 0000 R CNN +F 2 "" H 9300 8450 29 0000 C CNN +F 3 "" H 9100 8350 60 0000 C CNN + 1 9100 8350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 69987A52 +P 8550 8200 +F 0 "D7" H 8550 8300 50 0000 C CNN +F 1 "eSim_Diode" H 8550 8100 50 0000 C CNN +F 2 "" H 8550 8200 60 0000 C CNN +F 3 "" H 8550 8200 60 0000 C CNN + 1 8550 8200 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8550 8050 8550 8000 +Wire Wire Line + 8550 8000 9200 8000 +Wire Wire Line + 9200 7850 9200 8150 +Wire Wire Line + 8550 8350 8550 8400 +Wire Wire Line + 8300 8400 8900 8400 +Wire Wire Line + 8900 8400 8900 8350 +Connection ~ 8550 8400 +Connection ~ 9200 8000 +$Comp +L resistor R1 +U 1 1 69987A60 +P 4650 10000 +F 0 "R1" H 4700 10130 50 0000 C CNN +F 1 "4k" H 4700 9950 50 0000 C CNN +F 2 "" H 4700 9980 30 0000 C CNN +F 3 "" V 4700 10050 30 0000 C CNN + 1 4650 10000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 69987A66 +P 5000 10300 +F 0 "D1" H 5000 10400 50 0000 C CNN +F 1 "eSim_Diode" H 5000 10200 50 0000 C CNN +F 2 "" H 5000 10300 60 0000 C CNN +F 3 "" H 5000 10300 60 0000 C CNN + 1 5000 10300 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 69987A6C +P 5350 10250 +F 0 "R3" H 5400 10380 50 0000 C CNN +F 1 "10k" H 5400 10200 50 0000 C CNN +F 2 "" H 5400 10230 30 0000 C CNN +F 3 "" V 5400 10300 30 0000 C CNN + 1 5350 10250 + 0 1 1 0 +$EndComp +Wire Wire Line + 5000 10150 5000 9950 +Connection ~ 5000 9950 +Wire Wire Line + 5400 10150 5400 9950 +Connection ~ 5400 9950 +$Comp +L resistor R4 +U 1 1 69987A76 +P 5650 8400 +F 0 "R4" H 5700 8530 50 0000 C CNN +F 1 "8.4k" H 5700 8350 50 0000 C CNN +F 2 "" H 5700 8380 30 0000 C CNN +F 3 "" V 5700 8450 30 0000 C CNN + 1 5650 8400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8300 8350 8300 8400 +Connection ~ 7850 8350 +Wire Wire Line + 5850 8350 8300 8350 +Wire Wire Line + 5550 8350 5250 8350 +Wire Wire Line + 5250 8350 5250 9950 +Connection ~ 5250 9950 +$Comp +L resistor R7 +U 1 1 69987A82 +P 6500 7950 +F 0 "R7" H 6550 8080 50 0000 C CNN +F 1 "9k" H 6550 7900 50 0000 C CNN +F 2 "" H 6550 7930 30 0000 C CNN +F 3 "" V 6550 8000 30 0000 C CNN + 1 6500 7950 + 0 1 1 0 +$EndComp +Connection ~ 6550 9150 +$Comp +L resistor R9 +U 1 1 69987A89 +P 7100 7950 +F 0 "R9" H 7150 8080 50 0000 C CNN +F 1 "5k" H 7150 7900 50 0000 C CNN +F 2 "" H 7150 7930 30 0000 C CNN +F 3 "" V 7150 8000 30 0000 C CNN + 1 7100 7950 + 0 1 1 0 +$EndComp +Wire Wire Line + 7150 8150 7150 8350 +Connection ~ 7150 8350 +$Comp +L resistor R11 +U 1 1 69987A91 +P 9150 7650 +F 0 "R11" H 9200 7780 50 0000 C CNN +F 1 "1.66k" H 9200 7600 50 0000 C CNN +F 2 "" H 9200 7630 30 0000 C CNN +F 3 "" V 9200 7700 30 0000 C CNN + 1 9150 7650 + 0 1 1 0 +$EndComp +Wire Wire Line + 6550 7850 6550 7400 +Wire Wire Line + 6550 7400 9850 7400 +Wire Wire Line + 9200 7550 9200 7400 +Connection ~ 9200 7400 +Wire Wire Line + 7150 7850 7150 7400 +Connection ~ 7150 7400 +Wire Wire Line + 9200 8100 9800 8100 +Connection ~ 9200 8100 +Wire Wire Line + 5000 10450 5000 10600 +Wire Wire Line + 5000 10600 9150 10600 +Wire Wire Line + 9150 10600 9150 8550 +Wire Wire Line + 9150 8550 9200 8550 +Wire Wire Line + 7850 9300 7850 10600 +Connection ~ 7850 10600 +Wire Wire Line + 6550 10100 6550 10600 +Connection ~ 6550 10600 +Wire Wire Line + 5400 10450 5400 10600 +Connection ~ 5400 10600 +Wire Wire Line + 4550 9950 4250 9950 +$Comp +L capacitor_polarised C1 +U 1 1 69987AAA +P 9600 8400 +F 0 "C1" H 9625 8500 50 0000 L CNN +F 1 "15pF" H 9625 8300 50 0000 L CNN +F 2 "" H 9600 8400 50 0001 C CNN +F 3 "" H 9600 8400 50 0001 C CNN + 1 9600 8400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9600 8250 9600 8100 +Connection ~ 9600 8100 +$Comp +L eSim_Diode D9 +U 1 1 69987AB2 +P 9950 8100 +F 0 "D9" H 9950 8200 50 0000 C CNN +F 1 "eSim_Diode" H 9950 8000 50 0000 C CNN +F 2 "" H 9950 8100 60 0000 C CNN +F 3 "" H 9950 8100 60 0000 C CNN + 1 9950 8100 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D11 +U 1 1 69987AB8 +P 10550 8100 +F 0 "D11" H 10550 8200 50 0000 C CNN +F 1 "eSim_Diode" H 10550 8000 50 0000 C CNN +F 2 "" H 10550 8100 60 0000 C CNN +F 3 "" H 10550 8100 60 0000 C CNN + 1 10550 8100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D13 +U 1 1 69987ABE +P 11000 8100 +F 0 "D13" H 11000 8200 50 0000 C CNN +F 1 "eSim_Diode" H 11000 8000 50 0000 C CNN +F 2 "" H 11000 8100 60 0000 C CNN +F 3 "" H 11000 8100 60 0000 C CNN + 1 11000 8100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D15 +U 1 1 69987AC4 +P 11450 8100 +F 0 "D15" H 11450 8200 50 0000 C CNN +F 1 "eSim_Diode" H 11450 8000 50 0000 C CNN +F 2 "" H 11450 8100 60 0000 C CNN +F 3 "" H 11450 8100 60 0000 C CNN + 1 11450 8100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10700 8100 10850 8100 +Wire Wire Line + 11150 8100 11300 8100 +Wire Wire Line + 11600 8100 11850 8100 +Wire Wire Line + 11850 8100 11850 8500 +Wire Wire Line + 10100 8100 10400 8100 +Wire Wire Line + 9600 7400 9600 7650 +Wire Wire Line + 9600 7650 10250 7650 +Connection ~ 9600 7400 +$Comp +L resistor R13 +U 1 1 69987AD2 +P 10200 7800 +F 0 "R13" H 10250 7930 50 0000 C CNN +F 1 "3.9k" H 10250 7750 50 0000 C CNN +F 2 "" H 10250 7780 30 0000 C CNN +F 3 "" V 10250 7850 30 0000 C CNN + 1 10200 7800 + 0 1 1 0 +$EndComp +Wire Wire Line + 10250 7650 10250 7700 +Wire Wire Line + 10250 8000 10250 8100 +Connection ~ 10250 8100 +Wire Wire Line + 7200 10700 7200 10600 +Connection ~ 7200 10600 +Wire Wire Line + 9600 8550 9600 8650 +Wire Wire Line + 9400 8100 9400 8850 +Wire Wire Line + 9400 8850 9850 8850 +Connection ~ 9400 8100 +$Comp +L eSim_NPN Q8 +U 1 1 6998830B +P 13700 6600 +F 0 "Q8" H 13600 6650 50 0000 R CNN +F 1 "eSim_NPN" H 13650 6750 50 0000 R CNN +F 2 "" H 13900 6700 29 0000 C CNN +F 3 "" H 13700 6600 60 0000 C CNN + 1 13700 6600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D20 +U 1 1 69988311 +P 13150 6450 +F 0 "D20" H 13150 6550 50 0000 C CNN +F 1 "eSim_Diode" H 13150 6350 50 0000 C CNN +F 2 "" H 13150 6450 60 0000 C CNN +F 3 "" H 13150 6450 60 0000 C CNN + 1 13150 6450 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 13150 6300 13150 6250 +Wire Wire Line + 13150 6250 13800 6250 +Wire Wire Line + 13800 4850 13800 6400 +Wire Wire Line + 13150 6600 13150 6650 +Wire Wire Line + 12100 6650 13500 6650 +Wire Wire Line + 13500 6650 13500 6600 +Connection ~ 13150 6650 +Connection ~ 13800 6250 +$Comp +L eSim_NPN Q10 +U 1 1 6998831F +P 15000 5800 +F 0 "Q10" H 14900 5850 50 0000 R CNN +F 1 "eSim_NPN" H 14950 5950 50 0000 R CNN +F 2 "" H 15200 5900 29 0000 C CNN +F 3 "" H 15000 5800 60 0000 C CNN + 1 15000 5800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D22 +U 1 1 69988325 +P 14450 5650 +F 0 "D22" H 14450 5750 50 0000 C CNN +F 1 "eSim_Diode" H 14450 5550 50 0000 C CNN +F 2 "" H 14450 5650 60 0000 C CNN +F 3 "" H 14450 5650 60 0000 C CNN + 1 14450 5650 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 14450 5500 14450 5450 +Wire Wire Line + 14450 5450 15100 5450 +Wire Wire Line + 15100 5050 15100 5600 +Wire Wire Line + 14450 5800 14450 5850 +Wire Wire Line + 13800 5850 14800 5850 +Wire Wire Line + 14800 5850 14800 5800 +Connection ~ 14450 5850 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1 11900 6700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D18 +U 1 1 6998834D +P 12250 7000 +F 0 "D18" H 12250 7100 50 0000 C CNN +F 1 "eSim_Diode" H 12250 6900 50 0000 C CNN +F 2 "" H 12250 7000 60 0000 C CNN +F 3 "" H 12250 7000 60 0000 C CNN + 1 12250 7000 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R19 +U 1 1 69988353 +P 12600 6950 +F 0 "R19" H 12650 7080 50 0000 C CNN +F 1 "10k" H 12650 6900 50 0000 C CNN +F 2 "" H 12650 6930 30 0000 C CNN +F 3 "" V 12650 7000 30 0000 C CNN + 1 12600 6950 + 0 1 1 0 +$EndComp +Wire Wire Line + 12250 6850 12250 6650 +Connection ~ 12250 6650 +Wire Wire Line + 12650 6850 12650 6650 +Connection ~ 12650 6650 +$Comp +L resistor R20 +U 1 1 6998835D +P 12900 5100 +F 0 "R20" H 12950 5230 50 0000 C CNN +F 1 "8.4k" H 12950 5050 50 0000 C CNN +F 2 "" H 12950 5080 30 0000 C CNN +F 3 "" V 12950 5150 30 0000 C CNN + 1 12900 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15550 5050 15550 5100 +Connection ~ 15100 5050 +Wire Wire Line + 13100 5050 15550 5050 +Wire Wire Line + 12800 5050 12500 5050 +Wire Wire Line + 12500 5050 12500 6650 +Connection ~ 12500 6650 +$Comp +L resistor R22 +U 1 1 69988369 +P 13750 4650 +F 0 "R22" H 13800 4780 50 0000 C CNN +F 1 "9k" H 13800 4600 50 0000 C CNN +F 2 "" H 13800 4630 30 0000 C CNN +F 3 "" V 13800 4700 30 0000 C CNN + 1 13750 4650 + 0 1 1 0 +$EndComp +Connection ~ 13800 5850 +$Comp +L resistor R24 +U 1 1 69988370 +P 14350 4650 +F 0 "R24" H 14400 4780 50 0000 C CNN +F 1 "5k" H 14400 4600 50 0000 C CNN +F 2 "" H 14400 4630 30 0000 C CNN +F 3 "" V 14400 4700 30 0000 C CNN + 1 14350 4650 + 0 1 1 0 +$EndComp +Wire Wire Line + 14400 4850 14400 5050 +Connection ~ 14400 5050 +$Comp +L resistor R26 +U 1 1 69988378 +P 16400 4350 +F 0 "R26" H 16450 4480 50 0000 C CNN +F 1 "1.66k" H 16450 4300 50 0000 C CNN +F 2 "" H 16450 4330 30 0000 C CNN +F 3 "" V 16450 4400 30 0000 C CNN + 1 16400 4350 + 0 1 1 0 +$EndComp +Wire Wire Line + 13800 4550 13800 4100 +Wire Wire Line + 13800 4100 17100 4100 +Wire Wire Line + 16450 4250 16450 4100 +Connection ~ 16450 4100 +Wire Wire Line + 14400 4550 14400 4100 +Connection ~ 14400 4100 +Wire Wire Line + 16450 4800 17050 4800 +Connection ~ 16450 4800 +Wire Wire Line + 12250 7150 12250 7300 +Wire Wire Line + 12250 7300 16400 7300 +Wire Wire Line + 16400 7300 16400 5250 +Wire Wire Line + 16400 5250 16450 5250 +Wire Wire Line + 15100 6000 15100 7300 +Connection ~ 15100 7300 +Wire Wire Line + 13800 6800 13800 7300 +Connection ~ 13800 7300 +Wire Wire Line + 12650 7150 12650 7300 +Connection ~ 12650 7300 +Wire Wire Line + 11800 6650 11500 6650 +$Comp +L capacitor_polarised C4 +U 1 1 69988391 +P 16850 5100 +F 0 "C4" H 16875 5200 50 0000 L CNN +F 1 "15pF" H 16875 5000 50 0000 L CNN +F 2 "" H 16850 5100 50 0001 C CNN +F 3 "" H 16850 5100 50 0001 C CNN + 1 16850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16850 4950 16850 4800 +Connection ~ 16850 4800 +$Comp +L eSim_Diode D26 +U 1 1 69988399 +P 17200 4800 +F 0 "D26" H 17200 4900 50 0000 C CNN +F 1 "eSim_Diode" H 17200 4700 50 0000 C CNN +F 2 "" H 17200 4800 60 0000 C CNN +F 3 "" H 17200 4800 60 0000 C CNN + 1 17200 4800 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D28 +U 1 1 6998839F +P 17800 4800 +F 0 "D28" H 17800 4900 50 0000 C CNN +F 1 "eSim_Diode" H 17800 4700 50 0000 C CNN +F 2 "" H 17800 4800 60 0000 C CNN +F 3 "" H 17800 4800 60 0000 C CNN + 1 17800 4800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D30 +U 1 1 699883A5 +P 18250 4800 +F 0 "D30" H 18250 4900 50 0000 C CNN +F 1 "eSim_Diode" H 18250 4700 50 0000 C CNN +F 2 "" H 18250 4800 60 0000 C CNN +F 3 "" H 18250 4800 60 0000 C CNN + 1 18250 4800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D32 +U 1 1 699883AB +P 18700 4800 +F 0 "D32" H 18700 4900 50 0000 C CNN +F 1 "eSim_Diode" H 18700 4700 50 0000 C CNN +F 2 "" H 18700 4800 60 0000 C CNN +F 3 "" H 18700 4800 60 0000 C CNN + 1 18700 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 17950 4800 18100 4800 +Wire Wire Line + 18400 4800 18550 4800 +Wire Wire Line + 18850 4800 19100 4800 +Wire Wire Line + 19100 4800 19100 5200 +Wire Wire Line + 17350 4800 17650 4800 +Wire Wire Line + 16850 4100 16850 4350 +Wire Wire Line + 16850 4350 17500 4350 +Connection ~ 16850 4100 +$Comp +L resistor R28 +U 1 1 699883B9 +P 17450 4500 +F 0 "R28" H 17500 4630 50 0000 C CNN +F 1 "3.9k" H 17500 4450 50 0000 C CNN +F 2 "" H 17500 4480 30 0000 C CNN +F 3 "" V 17500 4550 30 0000 C CNN + 1 17450 4500 + 0 1 1 0 +$EndComp +Wire Wire Line + 17500 4350 17500 4400 +Wire Wire Line + 17500 4700 17500 4800 +Connection ~ 17500 4800 +Wire Wire Line + 14450 7400 14450 7300 +Connection ~ 14450 7300 +Wire Wire Line + 16850 5250 16850 5350 +Wire Wire Line + 16650 4800 16650 5550 +Wire Wire Line + 16650 5550 17100 5550 +Connection ~ 16650 4800 +$Comp +L eSim_NPN Q7 +U 1 1 699883C8 +P 13250 11300 +F 0 "Q7" H 13150 11350 50 0000 R CNN +F 1 "eSim_NPN" H 13200 11450 50 0000 R CNN +F 2 "" H 13450 11400 29 0000 C CNN +F 3 "" H 13250 11300 60 0000 C CNN + 1 13250 11300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D19 +U 1 1 699883CE +P 12700 11150 +F 0 "D19" H 12700 11250 50 0000 C CNN +F 1 "eSim_Diode" H 12700 11050 50 0000 C CNN +F 2 "" H 12700 11150 60 0000 C CNN +F 3 "" H 12700 11150 60 0000 C CNN + 1 12700 11150 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 12700 11000 12700 10950 +Wire Wire Line + 12700 10950 13350 10950 +Wire Wire Line + 13350 9550 13350 11100 +Wire Wire Line + 12700 11300 12700 11350 +Wire Wire Line + 11650 11350 13050 11350 +Wire Wire Line + 13050 11350 13050 11300 +Connection ~ 12700 11350 +Connection ~ 13350 10950 +$Comp +L eSim_NPN Q9 +U 1 1 699883DC +P 14550 10500 +F 0 "Q9" H 14450 10550 50 0000 R CNN +F 1 "eSim_NPN" H 14500 10650 50 0000 R CNN +F 2 "" H 14750 10600 29 0000 C CNN +F 3 "" H 14550 10500 60 0000 C CNN + 1 14550 10500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D21 +U 1 1 699883E2 +P 14000 10350 +F 0 "D21" H 14000 10450 50 0000 C CNN +F 1 "eSim_Diode" H 14000 10250 50 0000 C CNN +F 2 "" H 14000 10350 60 0000 C CNN +F 3 "" H 14000 10350 60 0000 C CNN + 1 14000 10350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 14000 10200 14000 10150 +Wire Wire Line + 14000 10150 14650 10150 +Wire Wire Line + 14650 9750 14650 10300 +Wire Wire Line + 14000 10500 14000 10550 +Wire Wire Line + 13350 10550 14350 10550 +Wire Wire Line + 14350 10550 14350 10500 +Connection ~ 14000 10550 +Connection ~ 14650 10150 +$Comp +L eSim_NPN Q11 +U 1 1 699883F0 +P 15900 9750 +F 0 "Q11" H 15800 9800 50 0000 R CNN +F 1 "eSim_NPN" H 15850 9900 50 0000 R CNN +F 2 "" H 16100 9850 29 0000 C CNN +F 3 "" H 15900 9750 60 0000 C CNN + 1 15900 9750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D23 +U 1 1 699883F6 +P 15350 9600 +F 0 "D23" H 15350 9700 50 0000 C CNN +F 1 "eSim_Diode" H 15350 9500 50 0000 C CNN +F 2 "" H 15350 9600 60 0000 C CNN +F 3 "" H 15350 9600 60 0000 C CNN + 1 15350 9600 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 15350 9450 15350 9400 +Wire Wire Line + 15350 9400 16000 9400 +Wire Wire Line + 16000 9250 16000 9550 +Wire Wire Line + 15350 9750 15350 9800 +Wire Wire Line + 15100 9800 15700 9800 +Wire Wire Line + 15700 9800 15700 9750 +Connection ~ 15350 9800 +Connection ~ 16000 9400 +$Comp +L resistor R15 +U 1 1 69988404 +P 11450 11400 +F 0 "R15" H 11500 11530 50 0000 C CNN +F 1 "4k" H 11500 11350 50 0000 C CNN +F 2 "" H 11500 11380 30 0000 C CNN +F 3 "" V 11500 11450 30 0000 C CNN + 1 11450 11400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D16 +U 1 1 6998840A +P 11800 11700 +F 0 "D16" H 11800 11800 50 0000 C CNN +F 1 "eSim_Diode" H 11800 11600 50 0000 C CNN +F 2 "" H 11800 11700 60 0000 C CNN +F 3 "" H 11800 11700 60 0000 C CNN + 1 11800 11700 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R17 +U 1 1 69988410 +P 12150 11650 +F 0 "R17" H 12200 11780 50 0000 C CNN +F 1 "10k" H 12200 11600 50 0000 C CNN +F 2 "" H 12200 11630 30 0000 C CNN +F 3 "" V 12200 11700 30 0000 C CNN + 1 12150 11650 + 0 1 1 0 +$EndComp +Wire Wire Line + 11800 11550 11800 11350 +Connection ~ 11800 11350 +Wire Wire Line + 12200 11550 12200 11350 +Connection ~ 12200 11350 +$Comp +L resistor R18 +U 1 1 6998841A +P 12450 9800 +F 0 "R18" H 12500 9930 50 0000 C CNN +F 1 "8.4k" H 12500 9750 50 0000 C CNN +F 2 "" H 12500 9780 30 0000 C CNN +F 3 "" V 12500 9850 30 0000 C CNN + 1 12450 9800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15100 9750 15100 9800 +Connection ~ 14650 9750 +Wire Wire Line + 12650 9750 15100 9750 +Wire Wire Line + 12350 9750 12050 9750 +Wire Wire Line + 12050 9750 12050 11350 +Connection ~ 12050 11350 +$Comp +L resistor R21 +U 1 1 69988426 +P 13300 9350 +F 0 "R21" H 13350 9480 50 0000 C CNN +F 1 "9k" H 13350 9300 50 0000 C CNN +F 2 "" H 13350 9330 30 0000 C CNN +F 3 "" V 13350 9400 30 0000 C CNN + 1 13300 9350 + 0 1 1 0 +$EndComp +Connection ~ 13350 10550 +$Comp +L resistor R23 +U 1 1 6998842D +P 13900 9350 +F 0 "R23" H 13950 9480 50 0000 C CNN +F 1 "5k" H 13950 9300 50 0000 C CNN +F 2 "" H 13950 9330 30 0000 C CNN +F 3 "" V 13950 9400 30 0000 C CNN + 1 13900 9350 + 0 1 1 0 +$EndComp +Wire Wire Line + 13950 9550 13950 9750 +Connection ~ 13950 9750 +$Comp +L resistor R25 +U 1 1 69988435 +P 15950 9050 +F 0 "R25" H 16000 9180 50 0000 C CNN +F 1 "1.66k" H 16000 9000 50 0000 C CNN +F 2 "" H 16000 9030 30 0000 C CNN +F 3 "" V 16000 9100 30 0000 C CNN + 1 15950 9050 + 0 1 1 0 +$EndComp +Wire Wire Line + 13350 9250 13350 8800 +Wire Wire Line + 13350 8800 16650 8800 +Wire Wire Line + 16000 8950 16000 8800 +Connection ~ 16000 8800 +Wire Wire Line + 13950 9250 13950 8800 +Connection ~ 13950 8800 +Wire Wire Line + 16000 9500 16600 9500 +Connection ~ 16000 9500 +Wire Wire Line + 11800 11850 11800 12000 +Wire Wire Line + 11800 12000 15950 12000 +Wire Wire Line + 15950 12000 15950 9950 +Wire Wire Line + 15950 9950 16000 9950 +Wire Wire Line + 14650 10700 14650 12000 +Connection ~ 14650 12000 +Wire Wire Line + 13350 11500 13350 12000 +Connection ~ 13350 12000 +Wire Wire Line + 12200 11850 12200 12000 +Connection ~ 12200 12000 +Wire Wire Line + 11350 11350 11050 11350 +$Comp +L capacitor_polarised C3 +U 1 1 6998844E +P 16400 9800 +F 0 "C3" H 16425 9900 50 0000 L CNN +F 1 "15pF" H 16425 9700 50 0000 L CNN +F 2 "" H 16400 9800 50 0001 C CNN +F 3 "" H 16400 9800 50 0001 C CNN + 1 16400 9800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16400 9650 16400 9500 +Connection ~ 16400 9500 +$Comp +L eSim_Diode D25 +U 1 1 69988456 +P 16750 9500 +F 0 "D25" H 16750 9600 50 0000 C CNN +F 1 "eSim_Diode" H 16750 9400 50 0000 C CNN +F 2 "" H 16750 9500 60 0000 C CNN +F 3 "" H 16750 9500 60 0000 C CNN + 1 16750 9500 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D27 +U 1 1 6998845C +P 17350 9500 +F 0 "D27" H 17350 9600 50 0000 C CNN +F 1 "eSim_Diode" H 17350 9400 50 0000 C CNN +F 2 "" H 17350 9500 60 0000 C CNN +F 3 "" H 17350 9500 60 0000 C CNN + 1 17350 9500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D29 +U 1 1 69988462 +P 17800 9500 +F 0 "D29" H 17800 9600 50 0000 C CNN +F 1 "eSim_Diode" H 17800 9400 50 0000 C CNN +F 2 "" H 17800 9500 60 0000 C CNN +F 3 "" H 17800 9500 60 0000 C CNN + 1 17800 9500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D31 +U 1 1 69988468 +P 18250 9500 +F 0 "D31" H 18250 9600 50 0000 C CNN +F 1 "eSim_Diode" H 18250 9400 50 0000 C CNN +F 2 "" H 18250 9500 60 0000 C CNN +F 3 "" H 18250 9500 60 0000 C CNN + 1 18250 9500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 17500 9500 17650 9500 +Wire Wire Line + 17950 9500 18100 9500 +Wire Wire Line + 18400 9500 18650 9500 +Wire Wire Line + 18650 9500 18650 9900 +Wire Wire Line + 16900 9500 17200 9500 +Wire Wire Line + 16400 8800 16400 9050 +Wire Wire Line + 16400 9050 17050 9050 +Connection ~ 16400 8800 +$Comp +L resistor R27 +U 1 1 69988476 +P 17000 9200 +F 0 "R27" H 17050 9330 50 0000 C CNN +F 1 "3.9k" H 17050 9150 50 0000 C CNN +F 2 "" H 17050 9180 30 0000 C CNN +F 3 "" V 17050 9250 30 0000 C CNN + 1 17000 9200 + 0 1 1 0 +$EndComp +Wire Wire Line + 17050 9050 17050 9100 +Wire Wire Line + 17050 9400 17050 9500 +Connection ~ 17050 9500 +Wire Wire Line + 14000 12100 14000 12000 +Connection ~ 14000 12000 +Wire Wire Line + 16400 9950 16400 10050 +Wire Wire Line + 16200 9500 16200 10250 +Wire Wire Line + 16200 10250 16650 10250 +Connection ~ 16200 9500 +$Comp +L PORT U1 +U 10 1 69988C3F +P 11250 6650 +F 0 "U1" H 11300 6750 30 0000 C CNN +F 1 "PORT" H 11250 6650 30 0000 C CNN +F 2 "" H 11250 6650 60 0000 C CNN +F 3 "" H 11250 6650 60 0000 C CNN + 10 11250 6650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 69988D18 +P 16900 10250 +F 0 "U1" H 16950 10350 30 0000 C CNN +F 1 "PORT" H 16900 10250 30 0000 C CNN +F 2 "" H 16900 10250 60 0000 C CNN +F 3 "" H 16900 10250 60 0000 C CNN + 11 16900 10250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 69988DCD +P 3200 3300 +F 0 "U1" H 3250 3400 30 0000 C CNN +F 1 "PORT" H 3200 3300 30 0000 C CNN +F 2 "" H 3200 3300 60 0000 C CNN +F 3 "" H 3200 3300 60 0000 C CNN + 12 3200 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 69988E80 +P 3150 3750 +F 0 "U1" H 3200 3850 30 0000 C CNN +F 1 "PORT" H 3150 3750 30 0000 C CNN +F 2 "" H 3150 3750 60 0000 C CNN +F 3 "" H 3150 3750 60 0000 C CNN + 7 3150 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 69988F3D +P 17350 5550 +F 0 "U1" H 17400 5650 30 0000 C CNN +F 1 "PORT" H 17350 5550 30 0000 C CNN +F 2 "" H 17350 5550 60 0000 C CNN +F 3 "" H 17350 5550 60 0000 C CNN + 8 17350 5550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 699891E8 +P 10800 11350 +F 0 "U1" H 10850 11450 30 0000 C CNN +F 1 "PORT" H 10800 11350 30 0000 C CNN +F 2 "" H 10800 11350 60 0000 C CNN +F 3 "" H 10800 11350 60 0000 C CNN + 13 10800 11350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 699892AB +P 3150 5000 +F 0 "U1" H 3200 5100 30 0000 C CNN +F 1 "PORT" H 3150 5000 30 0000 C CNN +F 2 "" H 3150 5000 60 0000 C CNN +F 3 "" H 3150 5000 60 0000 C CNN + 9 3150 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 69989374 +P 3200 5350 +F 0 "U1" H 3250 5450 30 0000 C CNN +F 1 "PORT" H 3200 5350 30 0000 C CNN +F 2 "" H 3200 5350 60 0000 C CNN +F 3 "" H 3200 5350 60 0000 C CNN + 14 3200 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 69989443 +P 3050 5700 +F 0 "U1" H 3100 5800 30 0000 C CNN +F 1 "PORT" H 3050 5700 30 0000 C CNN +F 2 "" H 3050 5700 60 0000 C CNN +F 3 "" H 3050 5700 60 0000 C CNN + 2 3050 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 69989504 +P 10550 4150 +F 0 "U1" H 10600 4250 30 0000 C CNN +F 1 "PORT" H 10550 4150 30 0000 C CNN +F 2 "" H 10550 4150 60 0000 C CNN +F 3 "" H 10550 4150 60 0000 C CNN + 3 10550 4150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 699895C5 +P 4450 5250 +F 0 "U1" H 4500 5350 30 0000 C CNN +F 1 "PORT" H 4450 5250 30 0000 C CNN +F 2 "" H 4450 5250 60 0000 C CNN +F 3 "" H 4450 5250 60 0000 C CNN + 1 4450 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 69989841 +P 4000 9950 +F 0 "U1" H 4050 10050 30 0000 C CNN +F 1 "PORT" H 4000 9950 30 0000 C CNN +F 2 "" H 4000 9950 60 0000 C CNN +F 3 "" H 4000 9950 60 0000 C CNN + 4 4000 9950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 69989910 +P 3050 7100 +F 0 "U1" H 3100 7200 30 0000 C CNN +F 1 "PORT" H 3050 7100 30 0000 C CNN +F 2 "" H 3050 7100 60 0000 C CNN +F 3 "" H 3050 7100 60 0000 C CNN + 5 3050 7100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 699899DD +P 10100 8850 +F 0 "U1" H 10150 8950 30 0000 C CNN +F 1 "PORT" H 10100 8850 30 0000 C CNN +F 2 "" H 10100 8850 60 0000 C CNN +F 3 "" H 10100 8850 60 0000 C CNN + 6 10100 8850 + -1 0 0 1 +$EndComp +Text GLabel 3550 5350 2 60 Input ~ 0 +VCC +Text GLabel 3700 3750 2 60 Input ~ 0 +GND +Wire Wire Line + 3400 3750 3700 3750 +Wire Wire Line + 3450 5350 3550 5350 +Text GLabel 10300 2700 2 60 Input ~ 0 +VCC +Text GLabel 17100 4100 2 60 Input ~ 0 +VCC +Text GLabel 9850 7400 2 60 Input ~ 0 +VCC +Text GLabel 16650 8800 2 60 Input ~ 0 +VCC +Text GLabel 7650 6000 3 60 Input ~ 0 +GND +Text GLabel 14450 7400 3 60 Input ~ 0 +GND +Text GLabel 14000 12100 3 60 Input ~ 0 +GND +Text GLabel 7200 10700 3 60 Input ~ 0 +GND +Text GLabel 9600 8650 2 60 Input ~ 0 +GND +Text GLabel 11850 8500 2 60 Input ~ 0 +GND +Text GLabel 10050 3950 2 60 Input ~ 0 +GND +Text GLabel 12300 3800 2 60 Input ~ 0 +GND +Text GLabel 16850 5350 2 60 Input ~ 0 +GND +Text GLabel 19100 5200 2 60 Input ~ 0 +GND +Text GLabel 16400 10050 2 60 Input ~ 0 +GND +Text GLabel 18650 9900 2 60 Input ~ 0 +GND +NoConn ~ 3300 7100 +NoConn ~ 3300 5700 +NoConn ~ 3400 5000 +NoConn ~ 3450 3300 +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189.sub b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189.sub new file mode 100644 index 000000000..b077d8b26 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189.sub @@ -0,0 +1,84 @@ +* Subcircuit SN55189 +.subckt SN55189 net-_r2-pad1_ ? net-_c2-pad1_ net-_r1-pad1_ ? net-_c1-pad1_ gnd net-_c4-pad1_ ? net-_r16-pad1_ net-_c3-pad1_ ? net-_r15-pad1_ vcc +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn55189\sn55189.cir +.include NPN.lib +.include schottky.lib +q2 net-_d4-pad2_ net-_d2-pad2_ gnd Q2N2222 +d4 net-_d2-pad2_ net-_d4-pad2_ 1N5819 +q4 net-_d6-pad2_ net-_d4-pad2_ gnd Q2N2222 +d6 net-_d4-pad2_ net-_d6-pad2_ 1N5819 +q6 net-_c2-pad1_ net-_d6-pad2_ gnd Q2N2222 +d8 net-_d6-pad2_ net-_c2-pad1_ 1N5819 +r2 net-_r2-pad1_ net-_d2-pad2_ 4k +d2 gnd net-_d2-pad2_ 1N5819 +r5 net-_d2-pad2_ gnd 10k +r6 net-_d2-pad2_ net-_d6-pad2_ 8.4k +r8 vcc net-_d4-pad2_ 9k +r10 vcc net-_d6-pad2_ 5k +r12 vcc net-_c2-pad1_ 1.66k +c2 net-_c2-pad1_ gnd 15pf +d10 net-_d10-pad1_ net-_c2-pad1_ 1N5819 +d12 net-_d10-pad1_ net-_d12-pad2_ 1N5819 +d14 net-_d12-pad2_ net-_d14-pad2_ 1N5819 +d17 net-_d14-pad2_ gnd 1N5819 +r14 vcc net-_d10-pad1_ 3.9k +q1 net-_d3-pad2_ net-_d1-pad2_ gnd Q2N2222 +d3 net-_d1-pad2_ net-_d3-pad2_ 1N5819 +q3 net-_d5-pad2_ net-_d3-pad2_ gnd Q2N2222 +d5 net-_d3-pad2_ net-_d5-pad2_ 1N5819 +q5 net-_c1-pad1_ net-_d5-pad2_ gnd Q2N2222 +d7 net-_d5-pad2_ net-_c1-pad1_ 1N5819 +r1 net-_r1-pad1_ net-_d1-pad2_ 4k +d1 gnd net-_d1-pad2_ 1N5819 +r3 net-_d1-pad2_ gnd 10k +r4 net-_d1-pad2_ net-_d5-pad2_ 8.4k +r7 vcc net-_d3-pad2_ 9k +r9 vcc net-_d5-pad2_ 5k +r11 vcc net-_c1-pad1_ 1.66k +c1 net-_c1-pad1_ gnd 15pf +d9 net-_d11-pad1_ net-_c1-pad1_ 1N5819 +d11 net-_d11-pad1_ net-_d11-pad2_ 1N5819 +d13 net-_d11-pad2_ net-_d13-pad2_ 1N5819 +d15 net-_d13-pad2_ gnd 1N5819 +r13 vcc net-_d11-pad1_ 3.9k +q8 net-_d20-pad2_ net-_d18-pad2_ gnd Q2N2222 +d20 net-_d18-pad2_ net-_d20-pad2_ 1N5819 +q10 net-_d22-pad2_ net-_d20-pad2_ gnd Q2N2222 +d22 net-_d20-pad2_ net-_d22-pad2_ 1N5819 +q12 net-_c4-pad1_ net-_d22-pad2_ gnd Q2N2222 +d24 net-_d22-pad2_ net-_c4-pad1_ 1N5819 +r16 net-_r16-pad1_ net-_d18-pad2_ 4k +d18 gnd net-_d18-pad2_ 1N5819 +r19 net-_d18-pad2_ gnd 10k +r20 net-_d18-pad2_ net-_d22-pad2_ 8.4k +r22 vcc net-_d20-pad2_ 9k +r24 vcc net-_d22-pad2_ 5k +r26 vcc net-_c4-pad1_ 1.66k +c4 net-_c4-pad1_ gnd 15pf +d26 net-_d26-pad1_ net-_c4-pad1_ 1N5819 +d28 net-_d26-pad1_ net-_d28-pad2_ 1N5819 +d30 net-_d28-pad2_ net-_d30-pad2_ 1N5819 +d32 net-_d30-pad2_ gnd 1N5819 +r28 vcc net-_d26-pad1_ 3.9k +q7 net-_d19-pad2_ net-_d16-pad2_ gnd Q2N2222 +d19 net-_d16-pad2_ net-_d19-pad2_ 1N5819 +q9 net-_d21-pad2_ net-_d19-pad2_ gnd Q2N2222 +d21 net-_d19-pad2_ net-_d21-pad2_ 1N5819 +q11 net-_c3-pad1_ net-_d21-pad2_ gnd Q2N2222 +d23 net-_d21-pad2_ net-_c3-pad1_ 1N5819 +r15 net-_r15-pad1_ net-_d16-pad2_ 4k +d16 gnd net-_d16-pad2_ 1N5819 +r17 net-_d16-pad2_ gnd 10k +r18 net-_d16-pad2_ net-_d21-pad2_ 8.4k +r21 vcc net-_d19-pad2_ 9k +r23 vcc net-_d21-pad2_ 5k +r25 vcc net-_c3-pad1_ 1.66k +c3 net-_c3-pad1_ gnd 15pf +d25 net-_d25-pad1_ net-_c3-pad1_ 1N5819 +d27 net-_d25-pad1_ net-_d27-pad2_ 1N5819 +d29 net-_d27-pad2_ net-_d29-pad2_ 1N5819 +d31 net-_d29-pad2_ gnd 1N5819 +r27 vcc net-_d25-pad1_ 3.9k +* Control Statements + +.ends SN55189 \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189_Previous_Values.xml new file mode 100644 index 000000000..af199556e --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/SN55189_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperessecsecsecC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.lib \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/analysis b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/schottky.lib b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/schottky.lib new file mode 100644 index 000000000..9579f7352 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN55189/schottky.lib @@ -0,0 +1 @@ +.model 1N5819 D(IS=390n RS=0.115 BV=40.0 IBV=1.00m CJO=203p M=0.333 N=1.70 TT=4.32u) diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and.cir b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and.pro b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and.pro new file mode 100644 index 000000000..da3e199e2 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 20:00:16 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and.sch b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and.sub b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and-cache.lib new file mode 100644 index 000000000..fc177c1f9 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and-rescue.lib b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and-rescue.lib new file mode 100644 index 000000000..483b8efb8 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and.cir b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and.cir new file mode 100644 index 000000000..6a05b9b5d --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and.cir.out new file mode 100644 index 000000000..6a6b126a7 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and.pro b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and.pro new file mode 100644 index 000000000..c16a3f858 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and.pro @@ -0,0 +1,49 @@ +update=Wed Mar 18 19:59:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_User +LibName15=eSim_Sources +LibName16=eSim_Subckt diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and.sch b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and.sch new file mode 100644 index 000000000..aef3c0436 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:5_and-rescue +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_User +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-5_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and.sub b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and.sub new file mode 100644 index 000000000..35b10e173 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and_Previous_Values.xml new file mode 100644 index 000000000..ae2c08a7f --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/5_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251-cache.lib new file mode 100644 index 000000000..ca315d6e0 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251-cache.lib @@ -0,0 +1,115 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# nor8_enable +# +DEF nor8_enable U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "nor8_enable" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 900 0 1 0 N +X a7 1 2150 1900 200 R 50 50 1 1 I +X a6 2 2150 1800 200 R 50 50 1 1 I +X a5 3 2150 1700 200 R 50 50 1 1 I +X a4 4 2150 1600 200 R 50 50 1 1 I +X a3 5 2150 1500 200 R 50 50 1 1 I +X a2 6 2150 1400 200 R 50 50 1 1 I +X a1 7 2150 1300 200 R 50 50 1 1 I +X a0 8 2150 1200 200 R 50 50 1 1 I +X en0 9 2150 1100 200 R 50 50 1 1 I +X y0 10 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# one_input_tristate_buffer +# +DEF one_input_tristate_buffer U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "one_input_tristate_buffer" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1600 0 1 0 N +X A0 1 2150 1900 200 R 50 50 1 1 I +X EN0 2 2150 1800 200 R 50 50 1 1 I +X Y0 3 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251.cir b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251.cir new file mode 100644 index 000000000..9a6e3f3a2 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251.cir @@ -0,0 +1,29 @@ +* C:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\SN74S251\SN74S251.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/21/26 22:51:22 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad4_ Net-_U3-Pad2_ Net-_U5-Pad2_ Net-_U4-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad8_ 5_and +X2 Net-_U1-Pad3_ Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U4-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad7_ 5_and +X3 Net-_U1-Pad2_ Net-_U3-Pad2_ Net-_U7-Pad2_ Net-_U4-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad6_ 5_and +X4 Net-_U1-Pad1_ Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U4-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad5_ 5_and +X5 Net-_U1-Pad15_ Net-_U3-Pad2_ Net-_U5-Pad2_ Net-_U8-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad4_ 5_and +X6 Net-_U1-Pad14_ Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U8-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad3_ 5_and +X7 Net-_U1-Pad13_ Net-_U3-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad2_ 5_and +X8 Net-_U1-Pad12_ Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad1_ 5_and +U2 Net-_U1-Pad7_ Net-_U10-Pad2_ d_inverter +U8 Net-_U4-Pad2_ Net-_U8-Pad2_ d_inverter +U4 Net-_U1-Pad9_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad10_ Net-_U5-Pad2_ d_inverter +U7 Net-_U5-Pad2_ Net-_U7-Pad2_ d_inverter +U6 Net-_U3-Pad2_ Net-_U6-Pad2_ d_inverter +U3 Net-_U1-Pad11_ Net-_U3-Pad2_ d_inverter +U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U9-Pad3_ Net-_U9-Pad4_ Net-_U9-Pad5_ Net-_U9-Pad6_ Net-_U9-Pad7_ Net-_U9-Pad8_ Net-_U10-Pad2_ Net-_U1-Pad6_ nor8_enable +U10 Net-_U1-Pad6_ Net-_U10-Pad2_ Net-_U10-Pad3_ one_input_tristate_buffer +U11 Net-_U10-Pad3_ Net-_U1-Pad5_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251.cir.out new file mode 100644 index 000000000..96cafe374 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251.cir.out @@ -0,0 +1,61 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74s251\sn74s251.cir + +.include 5_and.sub +x1 net-_u1-pad4_ net-_u3-pad2_ net-_u5-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad8_ 5_and +x2 net-_u1-pad3_ net-_u6-pad2_ net-_u5-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad7_ 5_and +x3 net-_u1-pad2_ net-_u3-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad6_ 5_and +x4 net-_u1-pad1_ net-_u6-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad5_ 5_and +x5 net-_u1-pad15_ net-_u3-pad2_ net-_u5-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad4_ 5_and +x6 net-_u1-pad14_ net-_u6-pad2_ net-_u5-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad3_ 5_and +x7 net-_u1-pad13_ net-_u3-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad2_ 5_and +x8 net-_u1-pad12_ net-_u6-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad1_ 5_and +* u2 net-_u1-pad7_ net-_u10-pad2_ d_inverter +* u8 net-_u4-pad2_ net-_u8-pad2_ d_inverter +* u4 net-_u1-pad9_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad10_ net-_u5-pad2_ d_inverter +* u7 net-_u5-pad2_ net-_u7-pad2_ d_inverter +* u6 net-_u3-pad2_ net-_u6-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u9-pad3_ net-_u9-pad4_ net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ net-_u10-pad2_ net-_u1-pad6_ nor8_enable +* u10 net-_u1-pad6_ net-_u10-pad2_ net-_u10-pad3_ one_input_tristate_buffer +* u11 net-_u10-pad3_ net-_u1-pad5_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +a1 net-_u1-pad7_ net-_u10-pad2_ u2 +a2 net-_u4-pad2_ net-_u8-pad2_ u8 +a3 net-_u1-pad9_ net-_u4-pad2_ u4 +a4 net-_u1-pad10_ net-_u5-pad2_ u5 +a5 net-_u5-pad2_ net-_u7-pad2_ u7 +a6 net-_u3-pad2_ net-_u6-pad2_ u6 +a7 net-_u1-pad11_ net-_u3-pad2_ u3 +a8 [net-_u9-pad1_ net-_u9-pad2_ net-_u9-pad3_ net-_u9-pad4_ net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ ] [net-_u10-pad2_ ] [net-_u1-pad6_ ] u9 +a9 [net-_u1-pad6_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] u10 +a10 net-_u10-pad3_ net-_u1-pad5_ u11 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: nor8_enable, NgSpice Name: nor8_enable +.model u9 nor8_enable(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u10 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251.pro b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251.sch b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251.sch new file mode 100644 index 000000000..6a9c3e3c0 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251.sch @@ -0,0 +1,656 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74S251-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 6999DFBD +P 11550 4000 +F 0 "X1" H 11600 3900 60 0000 C CNN +F 1 "5_and" H 11650 4150 60 0000 C CNN +F 2 "" H 11550 4000 60 0000 C CNN +F 3 "" H 11550 4000 60 0000 C CNN + 1 11550 4000 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X2 +U 1 1 6999E02D +P 11550 5000 +F 0 "X2" H 11600 4900 60 0000 C CNN +F 1 "5_and" H 11650 5150 60 0000 C CNN +F 2 "" H 11550 5000 60 0000 C CNN +F 3 "" H 11550 5000 60 0000 C CNN + 1 11550 5000 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X3 +U 1 1 6999E0B7 +P 11550 5900 +F 0 "X3" H 11600 5800 60 0000 C CNN +F 1 "5_and" H 11650 6050 60 0000 C CNN +F 2 "" H 11550 5900 60 0000 C CNN +F 3 "" H 11550 5900 60 0000 C CNN + 1 11550 5900 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X4 +U 1 1 6999E0BD +P 11550 6900 +F 0 "X4" H 11600 6800 60 0000 C CNN +F 1 "5_and" H 11650 7050 60 0000 C CNN +F 2 "" H 11550 6900 60 0000 C CNN +F 3 "" H 11550 6900 60 0000 C CNN + 1 11550 6900 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X5 +U 1 1 6999E217 +P 11600 7950 +F 0 "X5" H 11650 7850 60 0000 C CNN +F 1 "5_and" H 11700 8100 60 0000 C CNN +F 2 "" H 11600 7950 60 0000 C CNN +F 3 "" H 11600 7950 60 0000 C CNN + 1 11600 7950 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X6 +U 1 1 6999E21D +P 11600 8950 +F 0 "X6" H 11650 8850 60 0000 C CNN +F 1 "5_and" H 11700 9100 60 0000 C CNN +F 2 "" H 11600 8950 60 0000 C CNN +F 3 "" H 11600 8950 60 0000 C CNN + 1 11600 8950 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X7 +U 1 1 6999E223 +P 11600 9850 +F 0 "X7" H 11650 9750 60 0000 C CNN +F 1 "5_and" H 11700 10000 60 0000 C CNN +F 2 "" H 11600 9850 60 0000 C CNN +F 3 "" H 11600 9850 60 0000 C CNN + 1 11600 9850 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X8 +U 1 1 6999E229 +P 11600 10850 +F 0 "X8" H 11650 10750 60 0000 C CNN +F 1 "5_and" H 11700 11000 60 0000 C CNN +F 2 "" H 11600 10850 60 0000 C CNN +F 3 "" H 11600 10850 60 0000 C CNN + 1 11600 10850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 6999E92E +P 7300 2850 +F 0 "U2" H 7300 2750 60 0000 C CNN +F 1 "d_inverter" H 7300 3000 60 0000 C CNN +F 2 "" H 7350 2800 60 0000 C CNN +F 3 "" H 7350 2800 60 0000 C CNN + 1 7300 2850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 6999F3F0 +P 8600 12650 +F 0 "U8" H 8600 12550 60 0000 C CNN +F 1 "d_inverter" H 8600 12800 60 0000 C CNN +F 2 "" H 8650 12600 60 0000 C CNN +F 3 "" H 8650 12600 60 0000 C CNN + 1 8600 12650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 6999F463 +P 7650 12650 +F 0 "U4" H 7650 12550 60 0000 C CNN +F 1 "d_inverter" H 7650 12800 60 0000 C CNN +F 2 "" H 7700 12600 60 0000 C CNN +F 3 "" H 7700 12600 60 0000 C CNN + 1 7650 12650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6999F9D7 +P 7700 12100 +F 0 "U5" H 7700 12000 60 0000 C CNN +F 1 "d_inverter" H 7700 12250 60 0000 C CNN +F 2 "" H 7750 12050 60 0000 C CNN +F 3 "" H 7750 12050 60 0000 C CNN + 1 7700 12100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 6999FA1D +P 8550 12100 +F 0 "U7" H 8550 12000 60 0000 C CNN +F 1 "d_inverter" H 8550 12250 60 0000 C CNN +F 2 "" H 8600 12050 60 0000 C CNN +F 3 "" H 8600 12050 60 0000 C CNN + 1 8550 12100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 699A059C +P 8400 11450 +F 0 "U6" H 8400 11350 60 0000 C CNN +F 1 "d_inverter" H 8400 11600 60 0000 C CNN +F 2 "" H 8450 11400 60 0000 C CNN +F 3 "" H 8450 11400 60 0000 C CNN + 1 8400 11450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 699A05E8 +P 7500 11450 +F 0 "U3" H 7500 11350 60 0000 C CNN +F 1 "d_inverter" H 7500 11600 60 0000 C CNN +F 2 "" H 7550 11400 60 0000 C CNN +F 3 "" H 7550 11400 60 0000 C CNN + 1 7500 11450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11100 3800 6050 3800 +Wire Wire Line + 11100 4800 6100 4800 +Wire Wire Line + 11100 5700 6150 5700 +Wire Wire Line + 11100 6700 6150 6700 +Wire Wire Line + 11150 7750 6000 7750 +Wire Wire Line + 11150 8750 6000 8750 +Wire Wire Line + 11150 9650 5950 9650 +Wire Wire Line + 11150 10650 5700 10650 +Wire Wire Line + 7600 2850 16700 2850 +Wire Wire Line + 10650 2850 10650 11050 +Wire Wire Line + 10650 11050 11150 11050 +Connection ~ 10650 2850 +Wire Wire Line + 11150 10050 10650 10050 +Connection ~ 10650 10050 +Wire Wire Line + 11150 9150 10650 9150 +Connection ~ 10650 9150 +Wire Wire Line + 11150 8150 10650 8150 +Connection ~ 10650 8150 +Wire Wire Line + 11100 7100 10650 7100 +Connection ~ 10650 7100 +Wire Wire Line + 11100 6100 10650 6100 +Connection ~ 10650 6100 +Wire Wire Line + 11100 5200 10650 5200 +Connection ~ 10650 5200 +Wire Wire Line + 11100 4200 10650 4200 +Connection ~ 10650 4200 +Wire Wire Line + 11150 8050 10450 8050 +Wire Wire Line + 10450 8050 10450 12650 +Wire Wire Line + 10450 12650 8900 12650 +Wire Wire Line + 11150 9050 10450 9050 +Connection ~ 10450 9050 +Wire Wire Line + 11150 9950 10450 9950 +Connection ~ 10450 9950 +Wire Wire Line + 11150 10950 10450 10950 +Connection ~ 10450 10950 +Wire Wire Line + 10100 4100 11100 4100 +Wire Wire Line + 10100 12400 10100 4100 +Wire Wire Line + 8150 12400 10100 12400 +Wire Wire Line + 7950 12650 8300 12650 +Wire Wire Line + 8150 12400 8150 12650 +Connection ~ 8150 12650 +Wire Wire Line + 7350 12650 6550 12650 +Wire Wire Line + 11100 5100 10100 5100 +Connection ~ 10100 5100 +Wire Wire Line + 11100 6000 10100 6000 +Connection ~ 10100 6000 +Wire Wire Line + 11100 7000 10100 7000 +Connection ~ 10100 7000 +Wire Wire Line + 11100 5900 9800 5900 +Wire Wire Line + 9800 5900 9800 12100 +Wire Wire Line + 9800 12100 8850 12100 +Wire Wire Line + 8000 12100 8250 12100 +Wire Wire Line + 11100 6900 9800 6900 +Connection ~ 9800 6900 +Wire Wire Line + 11150 10850 9800 10850 +Connection ~ 9800 10850 +Wire Wire Line + 11150 9850 9800 9850 +Connection ~ 9800 9850 +Wire Wire Line + 11100 4000 9400 4000 +Wire Wire Line + 9400 4000 9400 11700 +Wire Wire Line + 9400 11700 8150 11700 +Wire Wire Line + 8150 11700 8150 12100 +Connection ~ 8150 12100 +Wire Wire Line + 11100 5000 9400 5000 +Connection ~ 9400 5000 +Wire Wire Line + 11150 8950 9400 8950 +Connection ~ 9400 8950 +Wire Wire Line + 11150 7950 9400 7950 +Connection ~ 9400 7950 +Wire Wire Line + 11100 4900 9100 4900 +Wire Wire Line + 9100 4900 9100 11450 +Wire Wire Line + 9100 11450 8700 11450 +Wire Wire Line + 7800 11450 8100 11450 +Wire Wire Line + 11150 10750 9100 10750 +Connection ~ 9100 10750 +Wire Wire Line + 11150 8850 9100 8850 +Connection ~ 9100 8850 +Wire Wire Line + 11100 6800 9100 6800 +Connection ~ 9100 6800 +Wire Wire Line + 11100 3900 8650 3900 +Wire Wire Line + 8650 3900 8650 11050 +Wire Wire Line + 8650 11050 7950 11050 +Wire Wire Line + 7950 11050 7950 11450 +Connection ~ 7950 11450 +Wire Wire Line + 7400 12100 6900 12100 +Wire Wire Line + 7200 11450 6700 11450 +Wire Wire Line + 11100 5800 8650 5800 +Connection ~ 8650 5800 +Wire Wire Line + 11150 7850 8650 7850 +Connection ~ 8650 7850 +Wire Wire Line + 11150 9750 8650 9750 +Connection ~ 8650 9750 +$Comp +L nor8_enable U9 +U 1 1 6999E6D2 +P 12950 5700 +F 0 "U9" H 15800 7500 60 0000 C CNN +F 1 "nor8_enable" H 15800 7700 60 0000 C CNN +F 2 "" H 15800 7650 60 0000 C CNN +F 3 "" H 15800 7650 60 0000 C CNN + 1 12950 5700 + 1 0 0 1 +$EndComp +Wire Wire Line + 15100 6800 14700 6800 +Wire Wire Line + 14700 6800 14700 2850 +Wire Wire Line + 12100 4000 14400 4000 +Wire Wire Line + 14400 4000 14400 6900 +Wire Wire Line + 14400 6900 15100 6900 +Wire Wire Line + 14050 7000 15100 7000 +Wire Wire Line + 14050 7000 14050 5000 +Wire Wire Line + 14050 5000 12100 5000 +Wire Wire Line + 12100 5900 13750 5900 +Wire Wire Line + 13750 5900 13750 7100 +Wire Wire Line + 13750 7100 15100 7100 +Wire Wire Line + 13500 7200 15100 7200 +Wire Wire Line + 13500 7200 13500 6900 +Wire Wire Line + 13500 6900 12100 6900 +Wire Wire Line + 15100 7300 12600 7300 +Wire Wire Line + 12600 7300 12600 7950 +Wire Wire Line + 12600 7950 12150 7950 +Wire Wire Line + 15100 7400 12800 7400 +Wire Wire Line + 12800 7400 12800 8950 +Wire Wire Line + 12800 8950 12150 8950 +Wire Wire Line + 12150 9850 13250 9850 +Wire Wire Line + 13250 9850 13250 7500 +Wire Wire Line + 13250 7500 15100 7500 +Wire Wire Line + 15100 7600 13750 7600 +Wire Wire Line + 13750 7600 13750 10850 +Wire Wire Line + 13750 10850 12150 10850 +$Comp +L one_input_tristate_buffer U10 +U 1 1 6999F63E +P 14800 5200 +F 0 "U10" H 17650 7000 60 0000 C CNN +F 1 "one_input_tristate_buffer" H 17650 7200 60 0000 C CNN +F 2 "" H 17650 7150 60 0000 C CNN +F 3 "" H 17650 7150 60 0000 C CNN + 1 14800 5200 + 1 0 0 1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 6999F785 +P 18750 7100 +F 0 "U11" H 18750 7000 60 0000 C CNN +F 1 "d_inverter" H 18750 7250 60 0000 C CNN +F 2 "" H 18800 7050 60 0000 C CNN +F 3 "" H 18800 7050 60 0000 C CNN + 1 18750 7100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 18350 7100 18450 7100 +Wire Wire Line + 19050 7100 19250 7100 +Wire Wire Line + 16950 7100 16950 7600 +Wire Wire Line + 16500 7600 19250 7600 +Wire Wire Line + 16950 7000 16700 7000 +Wire Wire Line + 16700 7000 16700 2850 +Connection ~ 14700 2850 +Connection ~ 16950 7600 +Wire Wire Line + 7000 2850 6250 2850 +$Comp +L PORT U1 +U 11 1 699A06DA +P 6450 11450 +F 0 "U1" H 6500 11550 30 0000 C CNN +F 1 "PORT" H 6450 11450 30 0000 C CNN +F 2 "" H 6450 11450 60 0000 C CNN +F 3 "" H 6450 11450 60 0000 C CNN + 11 6450 11450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 699A082F +P 5450 10650 +F 0 "U1" H 5500 10750 30 0000 C CNN +F 1 "PORT" H 5450 10650 30 0000 C CNN +F 2 "" H 5450 10650 60 0000 C CNN +F 3 "" H 5450 10650 60 0000 C CNN + 12 5450 10650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 699A0872 +P 5700 9650 +F 0 "U1" H 5750 9750 30 0000 C CNN +F 1 "PORT" H 5700 9650 30 0000 C CNN +F 2 "" H 5700 9650 60 0000 C CNN +F 3 "" H 5700 9650 60 0000 C CNN + 13 5700 9650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 699A08B9 +P 5750 8750 +F 0 "U1" H 5800 8850 30 0000 C CNN +F 1 "PORT" H 5750 8750 30 0000 C CNN +F 2 "" H 5750 8750 60 0000 C CNN +F 3 "" H 5750 8750 60 0000 C CNN + 14 5750 8750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 699A08FA +P 19500 7600 +F 0 "U1" H 19550 7700 30 0000 C CNN +F 1 "PORT" H 19500 7600 30 0000 C CNN +F 2 "" H 19500 7600 60 0000 C CNN +F 3 "" H 19500 7600 60 0000 C CNN + 6 19500 7600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 699A09A9 +P 6000 2850 +F 0 "U1" H 6050 2950 30 0000 C CNN +F 1 "PORT" H 6000 2850 30 0000 C CNN +F 2 "" H 6000 2850 60 0000 C CNN +F 3 "" H 6000 2850 60 0000 C CNN + 7 6000 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 699A09F2 +P 5850 4800 +F 0 "U1" H 5900 4900 30 0000 C CNN +F 1 "PORT" H 5850 4800 30 0000 C CNN +F 2 "" H 5850 4800 60 0000 C CNN +F 3 "" H 5850 4800 60 0000 C CNN + 3 5850 4800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 699A0A41 +P 1550 3800 +F 0 "U1" H 1600 3900 30 0000 C CNN +F 1 "PORT" H 1550 3800 30 0000 C CNN +F 2 "" H 1550 3800 60 0000 C CNN +F 3 "" H 1550 3800 60 0000 C CNN + 8 1550 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 699A0A8E +P 6300 12650 +F 0 "U1" H 6350 12750 30 0000 C CNN +F 1 "PORT" H 6300 12650 30 0000 C CNN +F 2 "" H 6300 12650 60 0000 C CNN +F 3 "" H 6300 12650 60 0000 C CNN + 9 6300 12650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 699A0BD0 +P 6650 12100 +F 0 "U1" H 6700 12200 30 0000 C CNN +F 1 "PORT" H 6650 12100 30 0000 C CNN +F 2 "" H 6650 12100 60 0000 C CNN +F 3 "" H 6650 12100 60 0000 C CNN + 10 6650 12100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 699A0CAB +P 5750 7750 +F 0 "U1" H 5800 7850 30 0000 C CNN +F 1 "PORT" H 5750 7750 30 0000 C CNN +F 2 "" H 5750 7750 60 0000 C CNN +F 3 "" H 5750 7750 60 0000 C CNN + 15 5750 7750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 699A0D61 +P 1600 5200 +F 0 "U1" H 1650 5300 30 0000 C CNN +F 1 "PORT" H 1600 5200 30 0000 C CNN +F 2 "" H 1600 5200 60 0000 C CNN +F 3 "" H 1600 5200 60 0000 C CNN + 16 1600 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 699A0EAC +P 5800 3800 +F 0 "U1" H 5850 3900 30 0000 C CNN +F 1 "PORT" H 5800 3800 30 0000 C CNN +F 2 "" H 5800 3800 60 0000 C CNN +F 3 "" H 5800 3800 60 0000 C CNN + 4 5800 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 699A0FE2 +P 5900 5700 +F 0 "U1" H 5950 5800 30 0000 C CNN +F 1 "PORT" H 5900 5700 30 0000 C CNN +F 2 "" H 5900 5700 60 0000 C CNN +F 3 "" H 5900 5700 60 0000 C CNN + 2 5900 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 699A103D +P 5900 6700 +F 0 "U1" H 5950 6800 30 0000 C CNN +F 1 "PORT" H 5900 6700 30 0000 C CNN +F 2 "" H 5900 6700 60 0000 C CNN +F 3 "" H 5900 6700 60 0000 C CNN + 1 5900 6700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 699A109E +P 19500 7100 +F 0 "U1" H 19550 7200 30 0000 C CNN +F 1 "PORT" H 19500 7100 30 0000 C CNN +F 2 "" H 19500 7100 60 0000 C CNN +F 3 "" H 19500 7100 60 0000 C CNN + 5 19500 7100 + -1 0 0 1 +$EndComp +NoConn ~ 1850 5200 +NoConn ~ 1800 3800 +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251.sub b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251.sub new file mode 100644 index 000000000..472f1a4a6 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251.sub @@ -0,0 +1,55 @@ +* Subcircuit SN74S251 +.subckt SN74S251 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74s251\sn74s251.cir +.include 5_and.sub +x1 net-_u1-pad4_ net-_u3-pad2_ net-_u5-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad8_ 5_and +x2 net-_u1-pad3_ net-_u6-pad2_ net-_u5-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad7_ 5_and +x3 net-_u1-pad2_ net-_u3-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad6_ 5_and +x4 net-_u1-pad1_ net-_u6-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad5_ 5_and +x5 net-_u1-pad15_ net-_u3-pad2_ net-_u5-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad4_ 5_and +x6 net-_u1-pad14_ net-_u6-pad2_ net-_u5-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad3_ 5_and +x7 net-_u1-pad13_ net-_u3-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad2_ 5_and +x8 net-_u1-pad12_ net-_u6-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad1_ 5_and +* u2 net-_u1-pad7_ net-_u10-pad2_ d_inverter +* u8 net-_u4-pad2_ net-_u8-pad2_ d_inverter +* u4 net-_u1-pad9_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad10_ net-_u5-pad2_ d_inverter +* u7 net-_u5-pad2_ net-_u7-pad2_ d_inverter +* u6 net-_u3-pad2_ net-_u6-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u9-pad3_ net-_u9-pad4_ net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ net-_u10-pad2_ net-_u1-pad6_ nor8_enable +* u10 net-_u1-pad6_ net-_u10-pad2_ net-_u10-pad3_ one_input_tristate_buffer +* u11 net-_u10-pad3_ net-_u1-pad5_ d_inverter +a1 net-_u1-pad7_ net-_u10-pad2_ u2 +a2 net-_u4-pad2_ net-_u8-pad2_ u8 +a3 net-_u1-pad9_ net-_u4-pad2_ u4 +a4 net-_u1-pad10_ net-_u5-pad2_ u5 +a5 net-_u5-pad2_ net-_u7-pad2_ u7 +a6 net-_u3-pad2_ net-_u6-pad2_ u6 +a7 net-_u1-pad11_ net-_u3-pad2_ u3 +a8 [net-_u9-pad1_ net-_u9-pad2_ net-_u9-pad3_ net-_u9-pad4_ net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ ] [net-_u10-pad2_ ] [net-_u1-pad6_ ] u9 +a9 [net-_u1-pad6_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] u10 +a10 net-_u10-pad3_ net-_u1-pad5_ u11 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: nor8_enable, NgSpice Name: nor8_enable +.model u9 nor8_enable(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u10 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74S251 \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251_Previous_Values.xml new file mode 100644 index 000000000..979386599 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/SN74S251_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverternor8_enableone_input_tristate_bufferd_inverterC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_and \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/analysis b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/SN74S251/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/D.lib b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/NPN.lib b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804-cache.lib b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804-cache.lib new file mode 100644 index 000000000..d900cc5d9 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804-cache.lib @@ -0,0 +1,128 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS capacitor_polarised +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804.cir b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804.cir new file mode 100644 index 000000000..5add33a31 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804.cir @@ -0,0 +1,75 @@ +* C:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\ULN2804\ULN2804.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/21/26 13:13:00 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_C1-Pad1_ Net-_Q1-Pad3_ GND eSim_NPN +Q1 Net-_C1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R2 Net-_Q1-Pad3_ Net-_Q1-Pad2_ 7.2k +R3 GND Net-_Q1-Pad3_ 3k +R1 Net-_Q1-Pad2_ Net-_R1-Pad2_ 10.5k +C1 Net-_C1-Pad1_ GND 15pF +D1 GND Net-_C1-Pad1_ eSim_Diode +R4 VCC Net-_C1-Pad1_ 1k +U1 Net-_R1-Pad2_ Net-_R9-Pad2_ Net-_R17-Pad2_ Net-_R25-Pad2_ Net-_R5-Pad2_ Net-_R12-Pad2_ Net-_R20-Pad2_ Net-_R28-Pad2_ GND VCC Net-_C8-Pad1_ Net-_C6-Pad1_ Net-_C4-Pad1_ Net-_C2-Pad1_ Net-_C7-Pad1_ Net-_C5-Pad1_ Net-_C3-Pad1_ Net-_C1-Pad1_ PORT +Q7 Net-_C3-Pad1_ Net-_Q5-Pad3_ GND eSim_NPN +Q5 Net-_C3-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_NPN +R10 Net-_Q5-Pad3_ Net-_Q5-Pad2_ 7.2k +R11 GND Net-_Q5-Pad3_ 3k +R9 Net-_Q5-Pad2_ Net-_R9-Pad2_ 10.5k +C3 Net-_C3-Pad1_ GND 15pF +D3 GND Net-_C3-Pad1_ eSim_Diode +R15 VCC Net-_C3-Pad1_ 1k +Q11 Net-_C5-Pad1_ Net-_Q11-Pad2_ GND eSim_NPN +Q9 Net-_C5-Pad1_ Net-_Q9-Pad2_ Net-_Q11-Pad2_ eSim_NPN +R18 Net-_Q11-Pad2_ Net-_Q9-Pad2_ 7.2k +R19 GND Net-_Q11-Pad2_ 3k +R17 Net-_Q9-Pad2_ Net-_R17-Pad2_ 10.5k +C5 Net-_C5-Pad1_ GND 15pF +D5 GND Net-_C5-Pad1_ eSim_Diode +R23 VCC Net-_C5-Pad1_ 1k +Q15 Net-_C7-Pad1_ Net-_Q13-Pad3_ GND eSim_NPN +Q13 Net-_C7-Pad1_ Net-_Q13-Pad2_ Net-_Q13-Pad3_ eSim_NPN +R26 Net-_Q13-Pad3_ Net-_Q13-Pad2_ 7.2k +R27 GND Net-_Q13-Pad3_ 3k +R25 Net-_Q13-Pad2_ Net-_R25-Pad2_ 10.5k +C7 Net-_C7-Pad1_ GND 15pF +D7 GND Net-_C7-Pad1_ eSim_Diode +R31 VCC Net-_C7-Pad1_ 1k +Q4 Net-_C2-Pad1_ Net-_Q3-Pad3_ GND eSim_NPN +Q3 Net-_C2-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +R6 Net-_Q3-Pad3_ Net-_Q3-Pad2_ 7.2k +R7 GND Net-_Q3-Pad3_ 3k +R5 Net-_Q3-Pad2_ Net-_R5-Pad2_ 10.5k +C2 Net-_C2-Pad1_ GND 15pF +D2 GND Net-_C2-Pad1_ eSim_Diode +R8 VCC Net-_C2-Pad1_ 1k +Q8 Net-_C4-Pad1_ Net-_Q6-Pad3_ GND eSim_NPN +Q6 Net-_C4-Pad1_ Net-_Q6-Pad2_ Net-_Q6-Pad3_ eSim_NPN +R13 Net-_Q6-Pad3_ Net-_Q6-Pad2_ 7.2k +R14 GND Net-_Q6-Pad3_ 3k +R12 Net-_Q6-Pad2_ Net-_R12-Pad2_ 10.5k +C4 Net-_C4-Pad1_ GND 15pF +D4 GND Net-_C4-Pad1_ eSim_Diode +R16 VCC Net-_C4-Pad1_ 1k +Q12 Net-_C6-Pad1_ Net-_Q10-Pad3_ GND eSim_NPN +Q10 Net-_C6-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R21 Net-_Q10-Pad3_ Net-_Q10-Pad2_ 7.2k +R22 GND Net-_Q10-Pad3_ 3k +R20 Net-_Q10-Pad2_ Net-_R20-Pad2_ 10.5k +C6 Net-_C6-Pad1_ GND 15pF +D6 GND Net-_C6-Pad1_ eSim_Diode +R24 VCC Net-_C6-Pad1_ 1k +Q16 Net-_C8-Pad1_ Net-_Q14-Pad3_ GND eSim_NPN +Q14 Net-_C8-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R29 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.2k +R30 GND Net-_Q14-Pad3_ 3k +R28 Net-_Q14-Pad2_ Net-_R28-Pad2_ 10.5k +C8 Net-_C8-Pad1_ GND 15pF +D8 GND Net-_C8-Pad1_ eSim_Diode +R32 VCC Net-_C8-Pad1_ 1k + +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804.cir.out b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804.cir.out new file mode 100644 index 000000000..f0c531f04 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804.cir.out @@ -0,0 +1,78 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\uln2804\uln2804.cir + +.include D.lib +.include NPN.lib +q2 net-_c1-pad1_ net-_q1-pad3_ gnd Q2N2222 +q1 net-_c1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r2 net-_q1-pad3_ net-_q1-pad2_ 7.2k +r3 gnd net-_q1-pad3_ 3k +r1 net-_q1-pad2_ net-_r1-pad2_ 10.5k +c1 net-_c1-pad1_ gnd 15pf +d1 gnd net-_c1-pad1_ 1N4148 +r4 vcc net-_c1-pad1_ 1k +* u1 net-_r1-pad2_ net-_r9-pad2_ net-_r17-pad2_ net-_r25-pad2_ net-_r5-pad2_ net-_r12-pad2_ net-_r20-pad2_ net-_r28-pad2_ gnd vcc net-_c8-pad1_ net-_c6-pad1_ net-_c4-pad1_ net-_c2-pad1_ net-_c7-pad1_ net-_c5-pad1_ net-_c3-pad1_ net-_c1-pad1_ port +q7 net-_c3-pad1_ net-_q5-pad3_ gnd Q2N2222 +q5 net-_c3-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222 +r10 net-_q5-pad3_ net-_q5-pad2_ 7.2k +r11 gnd net-_q5-pad3_ 3k +r9 net-_q5-pad2_ net-_r9-pad2_ 10.5k +c3 net-_c3-pad1_ gnd 15pf +d3 gnd net-_c3-pad1_ 1N4148 +r15 vcc net-_c3-pad1_ 1k +q11 net-_c5-pad1_ net-_q11-pad2_ gnd Q2N2222 +q9 net-_c5-pad1_ net-_q9-pad2_ net-_q11-pad2_ Q2N2222 +r18 net-_q11-pad2_ net-_q9-pad2_ 7.2k +r19 gnd net-_q11-pad2_ 3k +r17 net-_q9-pad2_ net-_r17-pad2_ 10.5k +c5 net-_c5-pad1_ gnd 15pf +d5 gnd net-_c5-pad1_ 1N4148 +r23 vcc net-_c5-pad1_ 1k +q15 net-_c7-pad1_ net-_q13-pad3_ gnd Q2N2222 +q13 net-_c7-pad1_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222 +r26 net-_q13-pad3_ net-_q13-pad2_ 7.2k +r27 gnd net-_q13-pad3_ 3k +r25 net-_q13-pad2_ net-_r25-pad2_ 10.5k +c7 net-_c7-pad1_ gnd 15pf +d7 gnd net-_c7-pad1_ 1N4148 +r31 vcc net-_c7-pad1_ 1k +q4 net-_c2-pad1_ net-_q3-pad3_ gnd Q2N2222 +q3 net-_c2-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +r6 net-_q3-pad3_ net-_q3-pad2_ 7.2k +r7 gnd net-_q3-pad3_ 3k +r5 net-_q3-pad2_ net-_r5-pad2_ 10.5k +c2 net-_c2-pad1_ gnd 15pf +d2 gnd net-_c2-pad1_ 1N4148 +r8 vcc net-_c2-pad1_ 1k +q8 net-_c4-pad1_ net-_q6-pad3_ gnd Q2N2222 +q6 net-_c4-pad1_ net-_q6-pad2_ net-_q6-pad3_ Q2N2222 +r13 net-_q6-pad3_ net-_q6-pad2_ 7.2k +r14 gnd net-_q6-pad3_ 3k +r12 net-_q6-pad2_ net-_r12-pad2_ 10.5k +c4 net-_c4-pad1_ gnd 15pf +d4 gnd net-_c4-pad1_ 1N4148 +r16 vcc net-_c4-pad1_ 1k +q12 net-_c6-pad1_ net-_q10-pad3_ gnd Q2N2222 +q10 net-_c6-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +r21 net-_q10-pad3_ net-_q10-pad2_ 7.2k +r22 gnd net-_q10-pad3_ 3k +r20 net-_q10-pad2_ net-_r20-pad2_ 10.5k +c6 net-_c6-pad1_ gnd 15pf +d6 gnd net-_c6-pad1_ 1N4148 +r24 vcc net-_c6-pad1_ 1k +q16 net-_c8-pad1_ net-_q14-pad3_ gnd Q2N2222 +q14 net-_c8-pad1_ net-_q14-pad2_ net-_q14-pad3_ Q2N2222 +r29 net-_q14-pad3_ net-_q14-pad2_ 7.2k +r30 gnd net-_q14-pad3_ 3k +r28 net-_q14-pad2_ net-_r28-pad2_ 10.5k +c8 net-_c8-pad1_ gnd 15pf +d8 gnd net-_c8-pad1_ 1N4148 +r32 vcc net-_c8-pad1_ 1k +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804.pro b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804.sch b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804.sch new file mode 100644 index 000000000..2afcdd071 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804.sch @@ -0,0 +1,1430 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q2 +U 1 1 69993468 +P 7050 5650 +F 0 "Q2" H 6950 5700 50 0000 R CNN +F 1 "eSim_NPN" H 7000 5800 50 0000 R CNN +F 2 "" H 7250 5750 29 0000 C CNN +F 3 "" H 7050 5650 60 0000 C CNN + 1 7050 5650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 69994EE6 +P 6150 5150 +F 0 "Q1" H 6050 5200 50 0000 R CNN +F 1 "eSim_NPN" H 6100 5300 50 0000 R CNN +F 2 "" H 6350 5250 29 0000 C CNN +F 3 "" H 6150 5150 60 0000 C CNN + 1 6150 5150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 69994F60 +P 5650 5900 +F 0 "R2" H 5700 6030 50 0000 C CNN +F 1 "7.2k" H 5700 5850 50 0000 C CNN +F 2 "" H 5700 5880 30 0000 C CNN +F 3 "" V 5700 5950 30 0000 C CNN + 1 5650 5900 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 69994FD3 +P 5650 6350 +F 0 "R3" H 5700 6480 50 0000 C CNN +F 1 "3k" H 5700 6300 50 0000 C CNN +F 2 "" H 5700 6330 30 0000 C CNN +F 3 "" V 5700 6400 30 0000 C CNN + 1 5650 6350 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 69995054 +P 5650 4850 +F 0 "R1" H 5700 4980 50 0000 C CNN +F 1 "10.5k" H 5700 4800 50 0000 C CNN +F 2 "" H 5700 4830 30 0000 C CNN +F 3 "" V 5700 4900 30 0000 C CNN + 1 5650 4850 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C1 +U 1 1 6999523F +P 7500 5150 +F 0 "C1" H 7525 5250 50 0000 L CNN +F 1 "15pF" H 7525 5050 50 0000 L CNN +F 2 "" H 7500 5150 50 0001 C CNN +F 3 "" H 7500 5150 50 0001 C CNN + 1 7500 5150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 6999526D +P 8000 5150 +F 0 "D1" H 8000 5250 50 0000 C CNN +F 1 "eSim_Diode" H 8000 5050 50 0000 C CNN +F 2 "" H 8000 5150 60 0000 C CNN +F 3 "" H 8000 5150 60 0000 C CNN + 1 8000 5150 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 6999529F +P 7350 4350 +F 0 "R4" H 7400 4480 50 0000 C CNN +F 1 "1k" H 7400 4300 50 0000 C CNN +F 2 "" H 7400 4330 30 0000 C CNN +F 3 "" V 7400 4400 30 0000 C CNN + 1 7350 4350 + 0 -1 1 0 +$EndComp +Text GLabel 7500 5550 3 60 Input ~ 0 +GND +Text GLabel 8000 5600 3 60 Input ~ 0 +GND +Text GLabel 6350 6700 3 60 Input ~ 0 +GND +$Comp +L PORT U1 +U 9 1 699956C6 +P 1550 1650 +F 0 "U1" H 1600 1750 30 0000 C CNN +F 1 "PORT" H 1550 1650 30 0000 C CNN +F 2 "" H 1550 1650 60 0000 C CNN +F 3 "" H 1550 1650 60 0000 C CNN + 9 1550 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 69995703 +P 1600 2150 +F 0 "U1" H 1650 2250 30 0000 C CNN +F 1 "PORT" H 1600 2150 30 0000 C CNN +F 2 "" H 1600 2150 60 0000 C CNN +F 3 "" H 1600 2150 60 0000 C CNN + 10 1600 2150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6999572C +P 18500 8600 +F 0 "U1" H 18550 8700 30 0000 C CNN +F 1 "PORT" H 18500 8600 30 0000 C CNN +F 2 "" H 18500 8600 60 0000 C CNN +F 3 "" H 18500 8600 60 0000 C CNN + 11 18500 8600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 17 1 6999577F +P 11800 4900 +F 0 "U1" H 11850 5000 30 0000 C CNN +F 1 "PORT" H 11800 4900 30 0000 C CNN +F 2 "" H 11800 4900 60 0000 C CNN +F 3 "" H 11800 4900 60 0000 C CNN + 17 11800 4900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 699957A2 +P 15100 8500 +F 0 "U1" H 15150 8600 30 0000 C CNN +F 1 "PORT" H 15100 8500 30 0000 C CNN +F 2 "" H 15100 8500 60 0000 C CNN +F 3 "" H 15100 8500 60 0000 C CNN + 12 15100 8500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 699957E1 +P 15000 4800 +F 0 "U1" H 15050 4900 30 0000 C CNN +F 1 "PORT" H 15000 4800 30 0000 C CNN +F 2 "" H 15000 4800 60 0000 C CNN +F 3 "" H 15000 4800 60 0000 C CNN + 16 15000 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 69995808 +P 11900 8600 +F 0 "U1" H 11950 8700 30 0000 C CNN +F 1 "PORT" H 11900 8600 30 0000 C CNN +F 2 "" H 11900 8600 60 0000 C CNN +F 3 "" H 11900 8600 60 0000 C CNN + 13 11900 8600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 6999582E +P 9000 4300 +F 0 "U1" H 9050 4400 30 0000 C CNN +F 1 "PORT" H 9000 4300 30 0000 C CNN +F 2 "" H 9000 4300 60 0000 C CNN +F 3 "" H 9000 4300 60 0000 C CNN + 2 9000 4300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 18 1 69995855 +P 8400 4800 +F 0 "U1" H 8450 4900 30 0000 C CNN +F 1 "PORT" H 8400 4800 30 0000 C CNN +F 2 "" H 8400 4800 60 0000 C CNN +F 3 "" H 8400 4800 60 0000 C CNN + 18 8400 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 6999587D +P 18400 4900 +F 0 "U1" H 18450 5000 30 0000 C CNN +F 1 "PORT" H 18400 4900 30 0000 C CNN +F 2 "" H 18400 4900 60 0000 C CNN +F 3 "" H 18400 4900 60 0000 C CNN + 15 18400 4900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 699958A6 +P 5700 7900 +F 0 "U1" H 5750 8000 30 0000 C CNN +F 1 "PORT" H 5700 7900 30 0000 C CNN +F 2 "" H 5700 7900 60 0000 C CNN +F 3 "" H 5700 7900 60 0000 C CNN + 5 5700 7900 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 699958D0 +P 8500 8500 +F 0 "U1" H 8550 8600 30 0000 C CNN +F 1 "PORT" H 8500 8500 30 0000 C CNN +F 2 "" H 8500 8500 60 0000 C CNN +F 3 "" H 8500 8500 60 0000 C CNN + 14 8500 8500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 699958FB +P 9100 8000 +F 0 "U1" H 9150 8100 30 0000 C CNN +F 1 "PORT" H 9100 8000 30 0000 C CNN +F 2 "" H 9100 8000 60 0000 C CNN +F 3 "" H 9100 8000 60 0000 C CNN + 6 9100 8000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 69995970 +P 12300 7900 +F 0 "U1" H 12350 8000 30 0000 C CNN +F 1 "PORT" H 12300 7900 30 0000 C CNN +F 2 "" H 12300 7900 60 0000 C CNN +F 3 "" H 12300 7900 60 0000 C CNN + 7 12300 7900 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 699959D3 +P 15700 8000 +F 0 "U1" H 15750 8100 30 0000 C CNN +F 1 "PORT" H 15700 8000 30 0000 C CNN +F 2 "" H 15700 8000 60 0000 C CNN +F 3 "" H 15700 8000 60 0000 C CNN + 8 15700 8000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 69995A34 +P 12200 4200 +F 0 "U1" H 12250 4300 30 0000 C CNN +F 1 "PORT" H 12200 4200 30 0000 C CNN +F 2 "" H 12200 4200 60 0000 C CNN +F 3 "" H 12200 4200 60 0000 C CNN + 3 12200 4200 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 69995A91 +P 15600 4300 +F 0 "U1" H 15650 4400 30 0000 C CNN +F 1 "PORT" H 15600 4300 30 0000 C CNN +F 2 "" H 15600 4300 60 0000 C CNN +F 3 "" H 15600 4300 60 0000 C CNN + 4 15600 4300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 69995AEA +P 5600 4200 +F 0 "U1" H 5650 4300 30 0000 C CNN +F 1 "PORT" H 5600 4200 30 0000 C CNN +F 2 "" H 5600 4200 60 0000 C CNN +F 3 "" H 5600 4200 60 0000 C CNN + 1 5600 4200 + 0 1 1 0 +$EndComp +Text GLabel 1950 2150 2 60 Input ~ 0 +VCC +Text GLabel 7300 3950 1 60 Input ~ 0 +VCC +Wire Wire Line + 6250 5350 6250 5650 +Wire Wire Line + 6250 5650 6850 5650 +Wire Wire Line + 6250 4950 6250 4800 +Connection ~ 7150 4800 +Wire Wire Line + 7150 5850 7150 6550 +Wire Wire Line + 5600 4950 5600 5700 +Connection ~ 5600 5150 +Wire Wire Line + 5600 6000 5600 6150 +Wire Wire Line + 5600 6450 5600 6550 +Wire Wire Line + 5600 6550 7150 6550 +Wire Wire Line + 5600 6100 6450 6100 +Wire Wire Line + 6450 6100 6450 5650 +Connection ~ 6450 5650 +Connection ~ 5600 6100 +Wire Wire Line + 7300 4550 7300 4800 +Wire Wire Line + 8000 5000 8000 4800 +Wire Wire Line + 7500 5000 7500 4800 +Connection ~ 7500 4800 +Wire Wire Line + 5600 4650 5600 4450 +Wire Wire Line + 5600 5150 5950 5150 +Wire Wire Line + 7500 5300 7500 5550 +Wire Wire Line + 8000 5300 8000 5600 +Wire Wire Line + 7300 4250 7300 3950 +Wire Wire Line + 6350 6700 6350 6550 +Connection ~ 6350 6550 +Wire Wire Line + 7150 4800 7150 5450 +Wire Wire Line + 6250 4800 8150 4800 +Connection ~ 7300 4800 +Connection ~ 8000 4800 +Wire Wire Line + 1850 2150 1950 2150 +$Comp +L eSim_NPN Q7 +U 1 1 699A89B0 +P 10450 5750 +F 0 "Q7" H 10350 5800 50 0000 R CNN +F 1 "eSim_NPN" H 10400 5900 50 0000 R CNN +F 2 "" H 10650 5850 29 0000 C CNN +F 3 "" H 10450 5750 60 0000 C CNN + 1 10450 5750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 699A89B6 +P 9550 5250 +F 0 "Q5" H 9450 5300 50 0000 R CNN +F 1 "eSim_NPN" H 9500 5400 50 0000 R CNN +F 2 "" H 9750 5350 29 0000 C CNN +F 3 "" H 9550 5250 60 0000 C CNN + 1 9550 5250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R10 +U 1 1 699A89BC +P 9050 6000 +F 0 "R10" H 9100 6130 50 0000 C CNN +F 1 "7.2k" H 9100 5950 50 0000 C CNN +F 2 "" H 9100 5980 30 0000 C CNN +F 3 "" V 9100 6050 30 0000 C CNN + 1 9050 6000 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 699A89C2 +P 9050 6450 +F 0 "R11" H 9100 6580 50 0000 C CNN +F 1 "3k" H 9100 6400 50 0000 C CNN +F 2 "" H 9100 6430 30 0000 C CNN +F 3 "" V 9100 6500 30 0000 C CNN + 1 9050 6450 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R9 +U 1 1 699A89C8 +P 9050 4950 +F 0 "R9" H 9100 5080 50 0000 C CNN +F 1 "10.5k" H 9100 4900 50 0000 C CNN +F 2 "" H 9100 4930 30 0000 C CNN +F 3 "" V 9100 5000 30 0000 C CNN + 1 9050 4950 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C3 +U 1 1 699A89CE +P 10900 5250 +F 0 "C3" H 10925 5350 50 0000 L CNN +F 1 "15pF" H 10925 5150 50 0000 L CNN +F 2 "" H 10900 5250 50 0001 C CNN +F 3 "" H 10900 5250 50 0001 C CNN + 1 10900 5250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 699A89D4 +P 11400 5250 +F 0 "D3" H 11400 5350 50 0000 C CNN +F 1 "eSim_Diode" H 11400 5150 50 0000 C CNN +F 2 "" H 11400 5250 60 0000 C CNN +F 3 "" H 11400 5250 60 0000 C CNN + 1 11400 5250 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R15 +U 1 1 699A89DA +P 10750 4450 +F 0 "R15" H 10800 4580 50 0000 C CNN +F 1 "1k" H 10800 4400 50 0000 C CNN +F 2 "" H 10800 4430 30 0000 C CNN +F 3 "" V 10800 4500 30 0000 C CNN + 1 10750 4450 + 0 -1 1 0 +$EndComp +Text GLabel 10900 5650 3 60 Input ~ 0 +GND +Text GLabel 11400 5700 3 60 Input ~ 0 +GND +Text GLabel 9750 6800 3 60 Input ~ 0 +GND +Text GLabel 10700 4050 1 60 Input ~ 0 +VCC +Wire Wire Line + 9650 5450 9650 5750 +Wire Wire Line + 9650 5750 10250 5750 +Wire Wire Line + 9650 5050 9650 4900 +Connection ~ 10550 4900 +Wire Wire Line + 10550 5950 10550 6650 +Wire Wire Line + 9000 5050 9000 5800 +Connection ~ 9000 5250 +Wire Wire Line + 9000 6100 9000 6250 +Wire Wire Line + 9000 6550 9000 6650 +Wire Wire Line + 9000 6650 10550 6650 +Wire Wire Line + 9000 6200 9850 6200 +Wire Wire Line + 9850 6200 9850 5750 +Connection ~ 9850 5750 +Connection ~ 9000 6200 +Wire Wire Line + 10700 4650 10700 4900 +Wire Wire Line + 11400 5100 11400 4900 +Wire Wire Line + 10900 5100 10900 4900 +Connection ~ 10900 4900 +Wire Wire Line + 9000 4750 9000 4550 +Wire Wire Line + 9000 5250 9350 5250 +Wire Wire Line + 10900 5400 10900 5650 +Wire Wire Line + 11400 5400 11400 5700 +Wire Wire Line + 10700 4350 10700 4050 +Wire Wire Line + 9750 6800 9750 6650 +Connection ~ 9750 6650 +Wire Wire Line + 10550 4900 10550 5550 +Wire Wire Line + 9650 4900 11550 4900 +Connection ~ 10700 4900 +Connection ~ 11400 4900 +$Comp +L eSim_NPN Q11 +U 1 1 699A8BB9 +P 13650 5650 +F 0 "Q11" H 13550 5700 50 0000 R CNN +F 1 "eSim_NPN" H 13600 5800 50 0000 R CNN +F 2 "" H 13850 5750 29 0000 C CNN +F 3 "" H 13650 5650 60 0000 C CNN + 1 13650 5650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 699A8BBF +P 12750 5150 +F 0 "Q9" H 12650 5200 50 0000 R CNN +F 1 "eSim_NPN" H 12700 5300 50 0000 R CNN +F 2 "" H 12950 5250 29 0000 C CNN +F 3 "" H 12750 5150 60 0000 C CNN + 1 12750 5150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R18 +U 1 1 699A8BC5 +P 12250 5900 +F 0 "R18" H 12300 6030 50 0000 C CNN +F 1 "7.2k" H 12300 5850 50 0000 C CNN +F 2 "" H 12300 5880 30 0000 C CNN +F 3 "" V 12300 5950 30 0000 C CNN + 1 12250 5900 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R19 +U 1 1 699A8BCB +P 12250 6350 +F 0 "R19" H 12300 6480 50 0000 C CNN +F 1 "3k" H 12300 6300 50 0000 C CNN +F 2 "" H 12300 6330 30 0000 C CNN +F 3 "" V 12300 6400 30 0000 C CNN + 1 12250 6350 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R17 +U 1 1 699A8BD1 +P 12250 4850 +F 0 "R17" H 12300 4980 50 0000 C CNN +F 1 "10.5k" H 12300 4800 50 0000 C CNN +F 2 "" H 12300 4830 30 0000 C CNN +F 3 "" V 12300 4900 30 0000 C CNN + 1 12250 4850 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C5 +U 1 1 699A8BD7 +P 14100 5150 +F 0 "C5" H 14125 5250 50 0000 L CNN +F 1 "15pF" H 14125 5050 50 0000 L CNN +F 2 "" H 14100 5150 50 0001 C CNN +F 3 "" H 14100 5150 50 0001 C CNN + 1 14100 5150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 699A8BDD +P 14600 5150 +F 0 "D5" H 14600 5250 50 0000 C CNN +F 1 "eSim_Diode" H 14600 5050 50 0000 C CNN +F 2 "" H 14600 5150 60 0000 C CNN +F 3 "" H 14600 5150 60 0000 C CNN + 1 14600 5150 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R23 +U 1 1 699A8BE3 +P 13950 4350 +F 0 "R23" H 14000 4480 50 0000 C CNN +F 1 "1k" H 14000 4300 50 0000 C CNN +F 2 "" H 14000 4330 30 0000 C CNN +F 3 "" V 14000 4400 30 0000 C CNN + 1 13950 4350 + 0 -1 1 0 +$EndComp +Text GLabel 14100 5550 3 60 Input ~ 0 +GND +Text GLabel 14600 5600 3 60 Input ~ 0 +GND +Text GLabel 12950 6700 3 60 Input ~ 0 +GND +Text GLabel 13900 3950 1 60 Input ~ 0 +VCC +Wire Wire Line + 12850 5350 12850 5650 +Wire Wire Line + 12850 5650 13450 5650 +Wire Wire Line + 12850 4950 12850 4800 +Connection ~ 13750 4800 +Wire Wire Line + 13750 5850 13750 6550 +Wire Wire Line + 12200 4950 12200 5700 +Connection ~ 12200 5150 +Wire Wire Line + 12200 6000 12200 6150 +Wire Wire Line + 12200 6450 12200 6550 +Wire Wire Line + 12200 6550 13750 6550 +Wire Wire Line + 12200 6100 13050 6100 +Wire Wire Line + 13050 6100 13050 5650 +Connection ~ 13050 5650 +Connection ~ 12200 6100 +Wire Wire Line + 13900 4550 13900 4800 +Wire Wire Line + 14600 5000 14600 4800 +Wire Wire Line + 14100 5000 14100 4800 +Connection ~ 14100 4800 +Wire Wire Line + 12200 4650 12200 4450 +Wire Wire Line + 12200 5150 12550 5150 +Wire Wire Line + 14100 5300 14100 5550 +Wire Wire Line + 14600 5300 14600 5600 +Wire Wire Line + 13900 4250 13900 3950 +Wire Wire Line + 12950 6700 12950 6550 +Connection ~ 12950 6550 +Wire Wire Line + 13750 4800 13750 5450 +Wire Wire Line + 12850 4800 14750 4800 +Connection ~ 13900 4800 +Connection ~ 14600 4800 +$Comp +L eSim_NPN Q15 +U 1 1 699A8C0A +P 17050 5750 +F 0 "Q15" H 16950 5800 50 0000 R CNN +F 1 "eSim_NPN" H 17000 5900 50 0000 R CNN +F 2 "" H 17250 5850 29 0000 C CNN +F 3 "" H 17050 5750 60 0000 C CNN + 1 17050 5750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 699A8C10 +P 16150 5250 +F 0 "Q13" H 16050 5300 50 0000 R CNN +F 1 "eSim_NPN" H 16100 5400 50 0000 R CNN +F 2 "" H 16350 5350 29 0000 C CNN +F 3 "" H 16150 5250 60 0000 C CNN + 1 16150 5250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R26 +U 1 1 699A8C16 +P 15650 6000 +F 0 "R26" H 15700 6130 50 0000 C CNN +F 1 "7.2k" H 15700 5950 50 0000 C CNN +F 2 "" H 15700 5980 30 0000 C CNN +F 3 "" V 15700 6050 30 0000 C CNN + 1 15650 6000 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R27 +U 1 1 699A8C1C +P 15650 6450 +F 0 "R27" H 15700 6580 50 0000 C CNN +F 1 "3k" H 15700 6400 50 0000 C CNN +F 2 "" H 15700 6430 30 0000 C CNN +F 3 "" V 15700 6500 30 0000 C CNN + 1 15650 6450 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R25 +U 1 1 699A8C22 +P 15650 4950 +F 0 "R25" H 15700 5080 50 0000 C CNN +F 1 "10.5k" H 15700 4900 50 0000 C CNN +F 2 "" H 15700 4930 30 0000 C CNN +F 3 "" V 15700 5000 30 0000 C CNN + 1 15650 4950 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C7 +U 1 1 699A8C28 +P 17500 5250 +F 0 "C7" H 17525 5350 50 0000 L CNN +F 1 "15pF" H 17525 5150 50 0000 L CNN +F 2 "" H 17500 5250 50 0001 C CNN +F 3 "" H 17500 5250 50 0001 C CNN + 1 17500 5250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 699A8C2E +P 18000 5250 +F 0 "D7" H 18000 5350 50 0000 C CNN +F 1 "eSim_Diode" H 18000 5150 50 0000 C CNN +F 2 "" H 18000 5250 60 0000 C CNN +F 3 "" H 18000 5250 60 0000 C CNN + 1 18000 5250 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R31 +U 1 1 699A8C34 +P 17350 4450 +F 0 "R31" H 17400 4580 50 0000 C CNN +F 1 "1k" H 17400 4400 50 0000 C CNN +F 2 "" H 17400 4430 30 0000 C CNN +F 3 "" V 17400 4500 30 0000 C CNN + 1 17350 4450 + 0 -1 1 0 +$EndComp +Text GLabel 17500 5650 3 60 Input ~ 0 +GND +Text GLabel 18000 5700 3 60 Input ~ 0 +GND +Text GLabel 16350 6800 3 60 Input ~ 0 +GND +Text GLabel 17300 4050 1 60 Input ~ 0 +VCC +Wire Wire Line + 16250 5450 16250 5750 +Wire Wire Line + 16250 5750 16850 5750 +Wire Wire Line + 16250 5050 16250 4900 +Connection ~ 17150 4900 +Wire Wire Line + 17150 5950 17150 6650 +Wire Wire Line + 15600 5050 15600 5800 +Connection ~ 15600 5250 +Wire Wire Line + 15600 6100 15600 6250 +Wire Wire Line + 15600 6550 15600 6650 +Wire Wire Line + 15600 6650 17150 6650 +Wire Wire Line + 15600 6200 16450 6200 +Wire Wire Line + 16450 6200 16450 5750 +Connection ~ 16450 5750 +Connection ~ 15600 6200 +Wire Wire Line + 17300 4650 17300 4900 +Wire Wire Line + 18000 5100 18000 4900 +Wire Wire Line + 17500 5100 17500 4900 +Connection ~ 17500 4900 +Wire Wire Line + 15600 4750 15600 4550 +Wire Wire Line + 15600 5250 15950 5250 +Wire Wire Line + 17500 5400 17500 5650 +Wire Wire Line + 18000 5400 18000 5700 +Wire Wire Line + 17300 4350 17300 4050 +Wire Wire Line + 16350 6800 16350 6650 +Connection ~ 16350 6650 +Wire Wire Line + 17150 4900 17150 5550 +Wire Wire Line + 16250 4900 18150 4900 +Connection ~ 17300 4900 +Connection ~ 18000 4900 +$Comp +L eSim_NPN Q4 +U 1 1 699A90B5 +P 7150 9350 +F 0 "Q4" H 7050 9400 50 0000 R CNN +F 1 "eSim_NPN" H 7100 9500 50 0000 R CNN +F 2 "" H 7350 9450 29 0000 C CNN +F 3 "" H 7150 9350 60 0000 C CNN + 1 7150 9350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 699A90BB +P 6250 8850 +F 0 "Q3" H 6150 8900 50 0000 R CNN +F 1 "eSim_NPN" H 6200 9000 50 0000 R CNN +F 2 "" H 6450 8950 29 0000 C CNN +F 3 "" H 6250 8850 60 0000 C CNN + 1 6250 8850 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 699A90C1 +P 5750 9600 +F 0 "R6" H 5800 9730 50 0000 C CNN +F 1 "7.2k" H 5800 9550 50 0000 C CNN +F 2 "" H 5800 9580 30 0000 C CNN +F 3 "" V 5800 9650 30 0000 C CNN + 1 5750 9600 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 699A90C7 +P 5750 10050 +F 0 "R7" H 5800 10180 50 0000 C CNN +F 1 "3k" H 5800 10000 50 0000 C CNN +F 2 "" H 5800 10030 30 0000 C CNN +F 3 "" V 5800 10100 30 0000 C CNN + 1 5750 10050 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 699A90CD +P 5750 8550 +F 0 "R5" H 5800 8680 50 0000 C CNN +F 1 "10.5k" H 5800 8500 50 0000 C CNN +F 2 "" H 5800 8530 30 0000 C CNN +F 3 "" V 5800 8600 30 0000 C CNN + 1 5750 8550 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C2 +U 1 1 699A90D3 +P 7600 8850 +F 0 "C2" H 7625 8950 50 0000 L CNN +F 1 "15pF" H 7625 8750 50 0000 L CNN +F 2 "" H 7600 8850 50 0001 C CNN +F 3 "" H 7600 8850 50 0001 C CNN + 1 7600 8850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 699A90D9 +P 8100 8850 +F 0 "D2" H 8100 8950 50 0000 C CNN +F 1 "eSim_Diode" H 8100 8750 50 0000 C CNN +F 2 "" H 8100 8850 60 0000 C CNN +F 3 "" H 8100 8850 60 0000 C CNN + 1 8100 8850 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 699A90DF +P 7450 8050 +F 0 "R8" H 7500 8180 50 0000 C CNN +F 1 "1k" H 7500 8000 50 0000 C CNN +F 2 "" H 7500 8030 30 0000 C CNN +F 3 "" V 7500 8100 30 0000 C CNN + 1 7450 8050 + 0 -1 1 0 +$EndComp +Text GLabel 7600 9250 3 60 Input ~ 0 +GND +Text GLabel 8100 9300 3 60 Input ~ 0 +GND +Text GLabel 6450 10400 3 60 Input ~ 0 +GND +Text GLabel 7400 7650 1 60 Input ~ 0 +VCC +Wire Wire Line + 6350 9050 6350 9350 +Wire Wire Line + 6350 9350 6950 9350 +Wire Wire Line + 6350 8650 6350 8500 +Connection ~ 7250 8500 +Wire Wire Line + 7250 9550 7250 10250 +Wire Wire Line + 5700 8650 5700 9400 +Connection ~ 5700 8850 +Wire Wire Line + 5700 9700 5700 9850 +Wire Wire Line + 5700 10150 5700 10250 +Wire Wire Line + 5700 10250 7250 10250 +Wire Wire Line + 5700 9800 6550 9800 +Wire Wire Line + 6550 9800 6550 9350 +Connection ~ 6550 9350 +Connection ~ 5700 9800 +Wire Wire Line + 7400 8250 7400 8500 +Wire Wire Line + 8100 8700 8100 8500 +Wire Wire Line + 7600 8700 7600 8500 +Connection ~ 7600 8500 +Wire Wire Line + 5700 8350 5700 8150 +Wire Wire Line + 5700 8850 6050 8850 +Wire Wire Line + 7600 9000 7600 9250 +Wire Wire Line + 8100 9000 8100 9300 +Wire Wire Line + 7400 7950 7400 7650 +Wire Wire Line + 6450 10400 6450 10250 +Connection ~ 6450 10250 +Wire Wire Line + 7250 8500 7250 9150 +Wire Wire Line + 6350 8500 8250 8500 +Connection ~ 7400 8500 +Connection ~ 8100 8500 +$Comp +L eSim_NPN Q8 +U 1 1 699A9106 +P 10550 9450 +F 0 "Q8" H 10450 9500 50 0000 R CNN +F 1 "eSim_NPN" H 10500 9600 50 0000 R CNN +F 2 "" H 10750 9550 29 0000 C CNN +F 3 "" H 10550 9450 60 0000 C CNN + 1 10550 9450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 699A910C +P 9650 8950 +F 0 "Q6" H 9550 9000 50 0000 R CNN +F 1 "eSim_NPN" H 9600 9100 50 0000 R CNN +F 2 "" H 9850 9050 29 0000 C CNN +F 3 "" H 9650 8950 60 0000 C CNN + 1 9650 8950 + 1 0 0 -1 +$EndComp +$Comp +L resistor R13 +U 1 1 699A9112 +P 9150 9700 +F 0 "R13" H 9200 9830 50 0000 C CNN +F 1 "7.2k" H 9200 9650 50 0000 C CNN +F 2 "" H 9200 9680 30 0000 C CNN +F 3 "" V 9200 9750 30 0000 C CNN + 1 9150 9700 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R14 +U 1 1 699A9118 +P 9150 10150 +F 0 "R14" H 9200 10280 50 0000 C CNN +F 1 "3k" H 9200 10100 50 0000 C CNN +F 2 "" H 9200 10130 30 0000 C CNN +F 3 "" V 9200 10200 30 0000 C CNN + 1 9150 10150 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 699A911E +P 9150 8650 +F 0 "R12" H 9200 8780 50 0000 C CNN +F 1 "10.5k" H 9200 8600 50 0000 C CNN +F 2 "" H 9200 8630 30 0000 C CNN +F 3 "" V 9200 8700 30 0000 C CNN + 1 9150 8650 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C4 +U 1 1 699A9124 +P 11000 8950 +F 0 "C4" H 11025 9050 50 0000 L CNN +F 1 "15pF" H 11025 8850 50 0000 L CNN +F 2 "" H 11000 8950 50 0001 C CNN +F 3 "" H 11000 8950 50 0001 C CNN + 1 11000 8950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 699A912A +P 11500 8950 +F 0 "D4" H 11500 9050 50 0000 C CNN +F 1 "eSim_Diode" H 11500 8850 50 0000 C CNN +F 2 "" H 11500 8950 60 0000 C CNN +F 3 "" H 11500 8950 60 0000 C CNN + 1 11500 8950 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R16 +U 1 1 699A9130 +P 10850 8150 +F 0 "R16" H 10900 8280 50 0000 C CNN +F 1 "1k" H 10900 8100 50 0000 C CNN +F 2 "" H 10900 8130 30 0000 C CNN +F 3 "" V 10900 8200 30 0000 C CNN + 1 10850 8150 + 0 -1 1 0 +$EndComp +Text GLabel 11000 9350 3 60 Input ~ 0 +GND +Text GLabel 11500 9400 3 60 Input ~ 0 +GND +Text GLabel 9850 10500 3 60 Input ~ 0 +GND +Text GLabel 10800 7750 1 60 Input ~ 0 +VCC +Wire Wire Line + 9750 9150 9750 9450 +Wire Wire Line + 9750 9450 10350 9450 +Wire Wire Line + 9750 8750 9750 8600 +Connection ~ 10650 8600 +Wire Wire Line + 10650 9650 10650 10350 +Wire Wire Line + 9100 8750 9100 9500 +Connection ~ 9100 8950 +Wire Wire Line + 9100 9800 9100 9950 +Wire Wire Line + 9100 10250 9100 10350 +Wire Wire Line + 9100 10350 10650 10350 +Wire Wire Line + 9100 9900 9950 9900 +Wire Wire Line + 9950 9900 9950 9450 +Connection ~ 9950 9450 +Connection ~ 9100 9900 +Wire Wire Line + 10800 8350 10800 8600 +Wire Wire Line + 11500 8800 11500 8600 +Wire Wire Line + 11000 8800 11000 8600 +Connection ~ 11000 8600 +Wire Wire Line + 9100 8450 9100 8250 +Wire Wire Line + 9100 8950 9450 8950 +Wire Wire Line + 11000 9100 11000 9350 +Wire Wire Line + 11500 9100 11500 9400 +Wire Wire Line + 10800 8050 10800 7750 +Wire Wire Line + 9850 10500 9850 10350 +Connection ~ 9850 10350 +Wire Wire Line + 10650 8600 10650 9250 +Wire Wire Line + 9750 8600 11650 8600 +Connection ~ 10800 8600 +Connection ~ 11500 8600 +$Comp +L eSim_NPN Q12 +U 1 1 699A9157 +P 13750 9350 +F 0 "Q12" H 13650 9400 50 0000 R CNN +F 1 "eSim_NPN" H 13700 9500 50 0000 R CNN +F 2 "" H 13950 9450 29 0000 C CNN +F 3 "" H 13750 9350 60 0000 C CNN + 1 13750 9350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 699A915D +P 12850 8850 +F 0 "Q10" H 12750 8900 50 0000 R CNN +F 1 "eSim_NPN" H 12800 9000 50 0000 R CNN +F 2 "" H 13050 8950 29 0000 C CNN +F 3 "" H 12850 8850 60 0000 C CNN + 1 12850 8850 + 1 0 0 -1 +$EndComp +$Comp +L resistor R21 +U 1 1 699A9163 +P 12350 9600 +F 0 "R21" H 12400 9730 50 0000 C CNN +F 1 "7.2k" H 12400 9550 50 0000 C CNN +F 2 "" H 12400 9580 30 0000 C CNN +F 3 "" V 12400 9650 30 0000 C CNN + 1 12350 9600 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R22 +U 1 1 699A9169 +P 12350 10050 +F 0 "R22" H 12400 10180 50 0000 C CNN +F 1 "3k" H 12400 10000 50 0000 C CNN +F 2 "" H 12400 10030 30 0000 C CNN +F 3 "" V 12400 10100 30 0000 C CNN + 1 12350 10050 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R20 +U 1 1 699A916F +P 12350 8550 +F 0 "R20" H 12400 8680 50 0000 C CNN +F 1 "10.5k" H 12400 8500 50 0000 C CNN +F 2 "" H 12400 8530 30 0000 C CNN +F 3 "" V 12400 8600 30 0000 C CNN + 1 12350 8550 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C6 +U 1 1 699A9175 +P 14200 8850 +F 0 "C6" H 14225 8950 50 0000 L CNN +F 1 "15pF" H 14225 8750 50 0000 L CNN +F 2 "" H 14200 8850 50 0001 C CNN +F 3 "" H 14200 8850 50 0001 C CNN + 1 14200 8850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 699A917B +P 14700 8850 +F 0 "D6" H 14700 8950 50 0000 C CNN +F 1 "eSim_Diode" H 14700 8750 50 0000 C CNN +F 2 "" H 14700 8850 60 0000 C CNN +F 3 "" H 14700 8850 60 0000 C CNN + 1 14700 8850 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R24 +U 1 1 699A9181 +P 14050 8050 +F 0 "R24" H 14100 8180 50 0000 C CNN +F 1 "1k" H 14100 8000 50 0000 C CNN +F 2 "" H 14100 8030 30 0000 C CNN +F 3 "" V 14100 8100 30 0000 C CNN + 1 14050 8050 + 0 -1 1 0 +$EndComp +Text GLabel 14200 9250 3 60 Input ~ 0 +GND +Text GLabel 14700 9300 3 60 Input ~ 0 +GND +Text GLabel 13050 10400 3 60 Input ~ 0 +GND +Text GLabel 14000 7650 1 60 Input ~ 0 +VCC +Wire Wire Line + 12950 9050 12950 9350 +Wire Wire Line + 12950 9350 13550 9350 +Wire Wire Line + 12950 8650 12950 8500 +Connection ~ 13850 8500 +Wire Wire Line + 13850 9550 13850 10250 +Wire Wire Line + 12300 8650 12300 9400 +Connection ~ 12300 8850 +Wire Wire Line + 12300 9700 12300 9850 +Wire Wire Line + 12300 10150 12300 10250 +Wire Wire Line + 12300 10250 13850 10250 +Wire Wire Line + 12300 9800 13150 9800 +Wire Wire Line + 13150 9800 13150 9350 +Connection ~ 13150 9350 +Connection ~ 12300 9800 +Wire Wire Line + 14000 8250 14000 8500 +Wire Wire Line + 14700 8700 14700 8500 +Wire Wire Line + 14200 8700 14200 8500 +Connection ~ 14200 8500 +Wire Wire Line + 12300 8350 12300 8150 +Wire Wire Line + 12300 8850 12650 8850 +Wire Wire Line + 14200 9000 14200 9250 +Wire Wire Line + 14700 9000 14700 9300 +Wire Wire Line + 14000 7950 14000 7650 +Wire Wire Line + 13050 10400 13050 10250 +Connection ~ 13050 10250 +Wire Wire Line + 13850 8500 13850 9150 +Wire Wire Line + 12950 8500 14850 8500 +Connection ~ 14000 8500 +Connection ~ 14700 8500 +$Comp +L eSim_NPN Q16 +U 1 1 699A91A8 +P 17150 9450 +F 0 "Q16" H 17050 9500 50 0000 R CNN +F 1 "eSim_NPN" H 17100 9600 50 0000 R CNN +F 2 "" H 17350 9550 29 0000 C CNN +F 3 "" H 17150 9450 60 0000 C CNN + 1 17150 9450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 699A91AE +P 16250 8950 +F 0 "Q14" H 16150 9000 50 0000 R CNN +F 1 "eSim_NPN" H 16200 9100 50 0000 R CNN +F 2 "" H 16450 9050 29 0000 C CNN +F 3 "" H 16250 8950 60 0000 C CNN + 1 16250 8950 + 1 0 0 -1 +$EndComp +$Comp +L resistor R29 +U 1 1 699A91B4 +P 15750 9700 +F 0 "R29" H 15800 9830 50 0000 C CNN +F 1 "7.2k" H 15800 9650 50 0000 C CNN +F 2 "" H 15800 9680 30 0000 C CNN +F 3 "" V 15800 9750 30 0000 C CNN + 1 15750 9700 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R30 +U 1 1 699A91BA +P 15750 10150 +F 0 "R30" H 15800 10280 50 0000 C CNN +F 1 "3k" H 15800 10100 50 0000 C CNN +F 2 "" H 15800 10130 30 0000 C CNN +F 3 "" V 15800 10200 30 0000 C CNN + 1 15750 10150 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R28 +U 1 1 699A91C0 +P 15750 8650 +F 0 "R28" H 15800 8780 50 0000 C CNN +F 1 "10.5k" H 15800 8600 50 0000 C CNN +F 2 "" H 15800 8630 30 0000 C CNN +F 3 "" V 15800 8700 30 0000 C CNN + 1 15750 8650 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C8 +U 1 1 699A91C6 +P 17600 8950 +F 0 "C8" H 17625 9050 50 0000 L CNN +F 1 "15pF" H 17625 8850 50 0000 L CNN +F 2 "" H 17600 8950 50 0001 C CNN +F 3 "" H 17600 8950 50 0001 C CNN + 1 17600 8950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D8 +U 1 1 699A91CC +P 18100 8950 +F 0 "D8" H 18100 9050 50 0000 C CNN +F 1 "eSim_Diode" H 18100 8850 50 0000 C CNN +F 2 "" H 18100 8950 60 0000 C CNN +F 3 "" H 18100 8950 60 0000 C CNN + 1 18100 8950 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R32 +U 1 1 699A91D2 +P 17450 8150 +F 0 "R32" H 17500 8280 50 0000 C CNN +F 1 "1k" H 17500 8100 50 0000 C CNN +F 2 "" H 17500 8130 30 0000 C CNN +F 3 "" V 17500 8200 30 0000 C CNN + 1 17450 8150 + 0 -1 1 0 +$EndComp +Text GLabel 17600 9350 3 60 Input ~ 0 +GND +Text GLabel 18100 9400 3 60 Input ~ 0 +GND +Text GLabel 16450 10500 3 60 Input ~ 0 +GND +Text GLabel 17400 7750 1 60 Input ~ 0 +VCC +Wire Wire Line + 16350 9150 16350 9450 +Wire Wire Line + 16350 9450 16950 9450 +Wire Wire Line + 16350 8750 16350 8600 +Connection ~ 17250 8600 +Wire Wire Line + 17250 9650 17250 10350 +Wire Wire Line + 15700 8750 15700 9500 +Connection ~ 15700 8950 +Wire Wire Line + 15700 9800 15700 9950 +Wire Wire Line + 15700 10250 15700 10350 +Wire Wire Line + 15700 10350 17250 10350 +Wire Wire Line + 15700 9900 16550 9900 +Wire Wire Line + 16550 9900 16550 9450 +Connection ~ 16550 9450 +Connection ~ 15700 9900 +Wire Wire Line + 17400 8350 17400 8600 +Wire Wire Line + 18100 8800 18100 8600 +Wire Wire Line + 17600 8800 17600 8600 +Connection ~ 17600 8600 +Wire Wire Line + 15700 8450 15700 8250 +Wire Wire Line + 15700 8950 16050 8950 +Wire Wire Line + 17600 9100 17600 9350 +Wire Wire Line + 18100 9100 18100 9400 +Wire Wire Line + 17400 8050 17400 7750 +Wire Wire Line + 16450 10500 16450 10350 +Connection ~ 16450 10350 +Wire Wire Line + 17250 8600 17250 9250 +Wire Wire Line + 16350 8600 18250 8600 +Connection ~ 17400 8600 +Connection ~ 18100 8600 +Text GLabel 1900 1650 2 60 Input ~ 0 +GND +Wire Wire Line + 1800 1650 1900 1650 +$EndSCHEMATC diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804.sub b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804.sub new file mode 100644 index 000000000..f950d7fd1 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804.sub @@ -0,0 +1,72 @@ +* Subcircuit ULN2804 +.subckt ULN2804 net-_r1-pad2_ net-_r9-pad2_ net-_r17-pad2_ net-_r25-pad2_ net-_r5-pad2_ net-_r12-pad2_ net-_r20-pad2_ net-_r28-pad2_ gnd vcc net-_c8-pad1_ net-_c6-pad1_ net-_c4-pad1_ net-_c2-pad1_ net-_c7-pad1_ net-_c5-pad1_ net-_c3-pad1_ net-_c1-pad1_ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\uln2804\uln2804.cir +.include D.lib +.include NPN.lib +q2 net-_c1-pad1_ net-_q1-pad3_ gnd Q2N2222 +q1 net-_c1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r2 net-_q1-pad3_ net-_q1-pad2_ 7.2k +r3 gnd net-_q1-pad3_ 3k +r1 net-_q1-pad2_ net-_r1-pad2_ 10.5k +c1 net-_c1-pad1_ gnd 15pf +d1 gnd net-_c1-pad1_ 1N4148 +r4 vcc net-_c1-pad1_ 1k +q7 net-_c3-pad1_ net-_q5-pad3_ gnd Q2N2222 +q5 net-_c3-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222 +r10 net-_q5-pad3_ net-_q5-pad2_ 7.2k +r11 gnd net-_q5-pad3_ 3k +r9 net-_q5-pad2_ net-_r9-pad2_ 10.5k +c3 net-_c3-pad1_ gnd 15pf +d3 gnd net-_c3-pad1_ 1N4148 +r15 vcc net-_c3-pad1_ 1k +q11 net-_c5-pad1_ net-_q11-pad2_ gnd Q2N2222 +q9 net-_c5-pad1_ net-_q9-pad2_ net-_q11-pad2_ Q2N2222 +r18 net-_q11-pad2_ net-_q9-pad2_ 7.2k +r19 gnd net-_q11-pad2_ 3k +r17 net-_q9-pad2_ net-_r17-pad2_ 10.5k +c5 net-_c5-pad1_ gnd 15pf +d5 gnd net-_c5-pad1_ 1N4148 +r23 vcc net-_c5-pad1_ 1k +q15 net-_c7-pad1_ net-_q13-pad3_ gnd Q2N2222 +q13 net-_c7-pad1_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222 +r26 net-_q13-pad3_ net-_q13-pad2_ 7.2k +r27 gnd net-_q13-pad3_ 3k +r25 net-_q13-pad2_ net-_r25-pad2_ 10.5k +c7 net-_c7-pad1_ gnd 15pf +d7 gnd net-_c7-pad1_ 1N4148 +r31 vcc net-_c7-pad1_ 1k +q4 net-_c2-pad1_ net-_q3-pad3_ gnd Q2N2222 +q3 net-_c2-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +r6 net-_q3-pad3_ net-_q3-pad2_ 7.2k +r7 gnd net-_q3-pad3_ 3k +r5 net-_q3-pad2_ net-_r5-pad2_ 10.5k +c2 net-_c2-pad1_ gnd 15pf +d2 gnd net-_c2-pad1_ 1N4148 +r8 vcc net-_c2-pad1_ 1k +q8 net-_c4-pad1_ net-_q6-pad3_ gnd Q2N2222 +q6 net-_c4-pad1_ net-_q6-pad2_ net-_q6-pad3_ Q2N2222 +r13 net-_q6-pad3_ net-_q6-pad2_ 7.2k +r14 gnd net-_q6-pad3_ 3k +r12 net-_q6-pad2_ net-_r12-pad2_ 10.5k +c4 net-_c4-pad1_ gnd 15pf +d4 gnd net-_c4-pad1_ 1N4148 +r16 vcc net-_c4-pad1_ 1k +q12 net-_c6-pad1_ net-_q10-pad3_ gnd Q2N2222 +q10 net-_c6-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +r21 net-_q10-pad3_ net-_q10-pad2_ 7.2k +r22 gnd net-_q10-pad3_ 3k +r20 net-_q10-pad2_ net-_r20-pad2_ 10.5k +c6 net-_c6-pad1_ gnd 15pf +d6 gnd net-_c6-pad1_ 1N4148 +r24 vcc net-_c6-pad1_ 1k +q16 net-_c8-pad1_ net-_q14-pad3_ gnd Q2N2222 +q14 net-_c8-pad1_ net-_q14-pad2_ net-_q14-pad3_ Q2N2222 +r29 net-_q14-pad3_ net-_q14-pad2_ 7.2k +r30 gnd net-_q14-pad3_ 3k +r28 net-_q14-pad2_ net-_r28-pad2_ 10.5k +c8 net-_c8-pad1_ gnd 15pf +d8 gnd net-_c8-pad1_ 1N4148 +r32 vcc net-_c8-pad1_ 1k +* Control Statements + +.ends ULN2804 \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804_Previous_Values.xml b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804_Previous_Values.xml new file mode 100644 index 000000000..4e65e4f62 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/ULN2804_Previous_Values.xml @@ -0,0 +1 @@ +C:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/analysis b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/FOSSEE/eSim/library/SubcircuitLibrary/ULN2804/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74141/3_and-cache.lib b/library/SubcircuitLibrary/74141/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/74141/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74141/3_and.cir b/library/SubcircuitLibrary/74141/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/74141/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/74141/3_and.cir.out b/library/SubcircuitLibrary/74141/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/74141/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74141/3_and.pro b/library/SubcircuitLibrary/74141/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/74141/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/74141/3_and.sch b/library/SubcircuitLibrary/74141/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/74141/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74141/3_and.sub b/library/SubcircuitLibrary/74141/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/74141/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/74141/3_and_Previous_Values.xml b/library/SubcircuitLibrary/74141/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/74141/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/74141/5_and-cache.lib b/library/SubcircuitLibrary/74141/5_and-cache.lib new file mode 100644 index 000000000..fc177c1f9 --- /dev/null +++ b/library/SubcircuitLibrary/74141/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74141/5_and-rescue.lib b/library/SubcircuitLibrary/74141/5_and-rescue.lib new file mode 100644 index 000000000..483b8efb8 --- /dev/null +++ b/library/SubcircuitLibrary/74141/5_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74141/5_and.cir b/library/SubcircuitLibrary/74141/5_and.cir new file mode 100644 index 000000000..6a05b9b5d --- /dev/null +++ b/library/SubcircuitLibrary/74141/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/74141/5_and.cir.out b/library/SubcircuitLibrary/74141/5_and.cir.out new file mode 100644 index 000000000..6a6b126a7 --- /dev/null +++ b/library/SubcircuitLibrary/74141/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74141/5_and.pro b/library/SubcircuitLibrary/74141/5_and.pro new file mode 100644 index 000000000..c16a3f858 --- /dev/null +++ b/library/SubcircuitLibrary/74141/5_and.pro @@ -0,0 +1,49 @@ +update=Wed Mar 18 19:59:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_User +LibName15=eSim_Sources +LibName16=eSim_Subckt diff --git a/library/SubcircuitLibrary/74141/5_and.sch b/library/SubcircuitLibrary/74141/5_and.sch new file mode 100644 index 000000000..aef3c0436 --- /dev/null +++ b/library/SubcircuitLibrary/74141/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:5_and-rescue +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_User +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-5_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74141/5_and.sub b/library/SubcircuitLibrary/74141/5_and.sub new file mode 100644 index 000000000..35b10e173 --- /dev/null +++ b/library/SubcircuitLibrary/74141/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/74141/5_and_Previous_Values.xml b/library/SubcircuitLibrary/74141/5_and_Previous_Values.xml new file mode 100644 index 000000000..ae2c08a7f --- /dev/null +++ b/library/SubcircuitLibrary/74141/5_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/74141/74141-cache.lib b/library/SubcircuitLibrary/74141/74141-cache.lib new file mode 100644 index 000000000..504bcdc37 --- /dev/null +++ b/library/SubcircuitLibrary/74141/74141-cache.lib @@ -0,0 +1,200 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74141/74141.cir b/library/SubcircuitLibrary/74141/74141.cir new file mode 100644 index 000000000..698f7e425 --- /dev/null +++ b/library/SubcircuitLibrary/74141/74141.cir @@ -0,0 +1,51 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74141\74141.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/21/26 15:43:02 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad3_ Net-_Q10-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q1-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q3-Pad3_ Net-_Q10-Pad2_ Net-_Q4-Pad3_ eSim_NPN +Q5 Net-_Q5-Pad1_ Net-_Q1-Pad2_ Net-_Q5-Pad3_ eSim_NPN +Q6 Net-_Q5-Pad3_ Net-_Q10-Pad2_ Net-_Q6-Pad3_ eSim_NPN +Q7 Net-_Q7-Pad1_ Net-_Q1-Pad2_ Net-_Q7-Pad3_ eSim_NPN +Q8 Net-_Q7-Pad3_ Net-_Q10-Pad2_ Net-_Q8-Pad3_ eSim_NPN +Q9 Net-_Q9-Pad1_ Net-_Q1-Pad2_ Net-_Q10-Pad1_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +U10 GND Net-_Q1-Pad1_ zener +U11 GND Net-_Q2-Pad3_ zener +U12 GND Net-_Q3-Pad1_ zener +U13 GND Net-_Q4-Pad3_ zener +U14 GND Net-_Q5-Pad1_ zener +U15 GND Net-_Q6-Pad3_ zener +U16 GND Net-_Q7-Pad1_ zener +U17 GND Net-_Q8-Pad3_ zener +U18 GND Net-_Q9-Pad1_ zener +U19 GND Net-_Q10-Pad3_ zener +X4 Net-_U22-Pad1_ Net-_U23-Pad1_ Net-_U24-Pad1_ Net-_U25-Pad1_ Net-_U4-Pad3_ Net-_U27-Pad1_ 5_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ d_and +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_and +U4 Net-_U1-Pad3_ Net-_U2-Pad3_ Net-_U4-Pad3_ d_nor +U6 Net-_U1-Pad1_ Net-_U4-Pad3_ Net-_U22-Pad1_ d_nand +U3 Net-_U20-Pad3_ Net-_U21-Pad1_ d_inverter +U5 Net-_U21-Pad1_ Net-_U26-Pad1_ d_inverter +X3 Net-_U23-Pad1_ Net-_U4-Pad3_ Net-_U2-Pad2_ Net-_U9-Pad1_ 3_and +X2 Net-_U4-Pad3_ Net-_U1-Pad2_ Net-_U23-Pad1_ Net-_U8-Pad1_ 3_and +X1 Net-_U1-Pad2_ Net-_U4-Pad3_ Net-_U2-Pad2_ Net-_U7-Pad1_ 3_and +U7 Net-_U7-Pad1_ Net-_U23-Pad1_ d_inverter +U8 Net-_U8-Pad1_ Net-_U24-Pad1_ d_inverter +U9 Net-_U9-Pad1_ Net-_U25-Pad1_ d_inverter +U20 Net-_Q1-Pad1_ Net-_Q2-Pad3_ Net-_U20-Pad3_ Net-_U1-Pad1_ ? Net-_U2-Pad2_ Net-_U1-Pad2_ Net-_Q8-Pad3_ Net-_Q7-Pad1_ Net-_Q3-Pad1_ Net-_Q4-Pad3_ GND Net-_Q6-Pad3_ Net-_Q5-Pad1_ Net-_Q9-Pad1_ Net-_Q10-Pad3_ PORT +U22 Net-_U22-Pad1_ Net-_Q1-Pad3_ dac_bridge_1 +U23 Net-_U23-Pad1_ Net-_Q3-Pad3_ dac_bridge_1 +U24 Net-_U24-Pad1_ Net-_Q5-Pad3_ dac_bridge_1 +U25 Net-_U25-Pad1_ Net-_Q7-Pad3_ dac_bridge_1 +U26 Net-_U26-Pad1_ Net-_Q1-Pad2_ dac_bridge_1 +U27 Net-_U27-Pad1_ Net-_Q10-Pad1_ dac_bridge_1 +U21 Net-_U21-Pad1_ Net-_Q10-Pad2_ dac_bridge_1 + +.end diff --git a/library/SubcircuitLibrary/74141/74141.cir.out b/library/SubcircuitLibrary/74141/74141.cir.out new file mode 100644 index 000000000..27d514aad --- /dev/null +++ b/library/SubcircuitLibrary/74141/74141.cir.out @@ -0,0 +1,133 @@ +* c:\fossee\esim\library\subcircuitlibrary\74141\74141.cir + +.include 3_and.sub +.include 5_and.sub +.include NPN.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q1-pad3_ net-_q10-pad2_ net-_q2-pad3_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad2_ net-_q3-pad3_ Q2N2222 +q4 net-_q3-pad3_ net-_q10-pad2_ net-_q4-pad3_ Q2N2222 +q5 net-_q5-pad1_ net-_q1-pad2_ net-_q5-pad3_ Q2N2222 +q6 net-_q5-pad3_ net-_q10-pad2_ net-_q6-pad3_ Q2N2222 +q7 net-_q7-pad1_ net-_q1-pad2_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q10-pad2_ net-_q8-pad3_ Q2N2222 +q9 net-_q9-pad1_ net-_q1-pad2_ net-_q10-pad1_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +* u10 gnd net-_q1-pad1_ zener +* u11 gnd net-_q2-pad3_ zener +* u12 gnd net-_q3-pad1_ zener +* u13 gnd net-_q4-pad3_ zener +* u14 gnd net-_q5-pad1_ zener +* u15 gnd net-_q6-pad3_ zener +* u16 gnd net-_q7-pad1_ zener +* u17 gnd net-_q8-pad3_ zener +* u18 gnd net-_q9-pad1_ zener +* u19 gnd net-_q10-pad3_ zener +x4 net-_u22-pad1_ net-_u23-pad1_ net-_u24-pad1_ net-_u25-pad1_ net-_u4-pad3_ net-_u27-pad1_ 5_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u4 net-_u1-pad3_ net-_u2-pad3_ net-_u4-pad3_ d_nor +* u6 net-_u1-pad1_ net-_u4-pad3_ net-_u22-pad1_ d_nand +* u3 net-_u20-pad3_ net-_u21-pad1_ d_inverter +* u5 net-_u21-pad1_ net-_u26-pad1_ d_inverter +x3 net-_u23-pad1_ net-_u4-pad3_ net-_u2-pad2_ net-_u9-pad1_ 3_and +x2 net-_u4-pad3_ net-_u1-pad2_ net-_u23-pad1_ net-_u8-pad1_ 3_and +x1 net-_u1-pad2_ net-_u4-pad3_ net-_u2-pad2_ net-_u7-pad1_ 3_and +* u7 net-_u7-pad1_ net-_u23-pad1_ d_inverter +* u8 net-_u8-pad1_ net-_u24-pad1_ d_inverter +* u9 net-_u9-pad1_ net-_u25-pad1_ d_inverter +* u20 net-_q1-pad1_ net-_q2-pad3_ net-_u20-pad3_ net-_u1-pad1_ ? net-_u2-pad2_ net-_u1-pad2_ net-_q8-pad3_ net-_q7-pad1_ net-_q3-pad1_ net-_q4-pad3_ gnd net-_q6-pad3_ net-_q5-pad1_ net-_q9-pad1_ net-_q10-pad3_ port +* u22 net-_u22-pad1_ net-_q1-pad3_ dac_bridge_1 +* u23 net-_u23-pad1_ net-_q3-pad3_ dac_bridge_1 +* u24 net-_u24-pad1_ net-_q5-pad3_ dac_bridge_1 +* u25 net-_u25-pad1_ net-_q7-pad3_ dac_bridge_1 +* u26 net-_u26-pad1_ net-_q1-pad2_ dac_bridge_1 +* u27 net-_u27-pad1_ net-_q10-pad1_ dac_bridge_1 +* u21 net-_u21-pad1_ net-_q10-pad2_ dac_bridge_1 +a1 gnd net-_q1-pad1_ u10 +a2 gnd net-_q2-pad3_ u11 +a3 gnd net-_q3-pad1_ u12 +a4 gnd net-_q4-pad3_ u13 +a5 gnd net-_q5-pad1_ u14 +a6 gnd net-_q6-pad3_ u15 +a7 gnd net-_q7-pad1_ u16 +a8 gnd net-_q8-pad3_ u17 +a9 gnd net-_q9-pad1_ u18 +a10 gnd net-_q10-pad3_ u19 +a11 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1 +a12 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a13 [net-_u1-pad3_ net-_u2-pad3_ ] net-_u4-pad3_ u4 +a14 [net-_u1-pad1_ net-_u4-pad3_ ] net-_u22-pad1_ u6 +a15 net-_u20-pad3_ net-_u21-pad1_ u3 +a16 net-_u21-pad1_ net-_u26-pad1_ u5 +a17 net-_u7-pad1_ net-_u23-pad1_ u7 +a18 net-_u8-pad1_ net-_u24-pad1_ u8 +a19 net-_u9-pad1_ net-_u25-pad1_ u9 +a20 [net-_u22-pad1_ ] [net-_q1-pad3_ ] u22 +a21 [net-_u23-pad1_ ] [net-_q3-pad3_ ] u23 +a22 [net-_u24-pad1_ ] [net-_q5-pad3_ ] u24 +a23 [net-_u25-pad1_ ] [net-_q7-pad3_ ] u25 +a24 [net-_u26-pad1_ ] [net-_q1-pad2_ ] u26 +a25 [net-_u27-pad1_ ] [net-_q10-pad1_ ] u27 +a26 [net-_u21-pad1_ ] [net-_q10-pad2_ ] u21 +* Schematic Name: zener, NgSpice Name: zener +.model u10 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u11 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u12 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u13 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u14 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u15 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u16 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u17 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u18 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u19 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u23 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74141/74141.pro b/library/SubcircuitLibrary/74141/74141.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/74141/74141.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74141/74141.sch b/library/SubcircuitLibrary/74141/74141.sch new file mode 100644 index 000000000..95c8465a5 --- /dev/null +++ b/library/SubcircuitLibrary/74141/74141.sch @@ -0,0 +1,1008 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 69996B1C +P 9050 1250 +F 0 "Q1" H 8950 1300 50 0000 R CNN +F 1 "eSim_NPN" H 9000 1400 50 0000 R CNN +F 2 "" H 9250 1350 29 0000 C CNN +F 3 "" H 9050 1250 60 0000 C CNN + 1 9050 1250 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 69996BA7 +P 9050 1650 +F 0 "Q2" H 8950 1700 50 0000 R CNN +F 1 "eSim_NPN" H 9000 1800 50 0000 R CNN +F 2 "" H 9250 1750 29 0000 C CNN +F 3 "" H 9050 1650 60 0000 C CNN + 1 9050 1650 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 69996C7B +P 9050 2200 +F 0 "Q3" H 8950 2250 50 0000 R CNN +F 1 "eSim_NPN" H 9000 2350 50 0000 R CNN +F 2 "" H 9250 2300 29 0000 C CNN +F 3 "" H 9050 2200 60 0000 C CNN + 1 9050 2200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 69996C81 +P 9050 2600 +F 0 "Q4" H 8950 2650 50 0000 R CNN +F 1 "eSim_NPN" H 9000 2750 50 0000 R CNN +F 2 "" H 9250 2700 29 0000 C CNN +F 3 "" H 9050 2600 60 0000 C CNN + 1 9050 2600 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 69996CBD +P 9050 3150 +F 0 "Q5" H 8950 3200 50 0000 R CNN +F 1 "eSim_NPN" H 9000 3300 50 0000 R CNN +F 2 "" H 9250 3250 29 0000 C CNN +F 3 "" H 9050 3150 60 0000 C CNN + 1 9050 3150 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 69996CC3 +P 9050 3550 +F 0 "Q6" H 8950 3600 50 0000 R CNN +F 1 "eSim_NPN" H 9000 3700 50 0000 R CNN +F 2 "" H 9250 3650 29 0000 C CNN +F 3 "" H 9050 3550 60 0000 C CNN + 1 9050 3550 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 69996DD2 +P 9050 4200 +F 0 "Q7" H 8950 4250 50 0000 R CNN +F 1 "eSim_NPN" H 9000 4350 50 0000 R CNN +F 2 "" H 9250 4300 29 0000 C CNN +F 3 "" H 9050 4200 60 0000 C CNN + 1 9050 4200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 69996DD8 +P 9050 4600 +F 0 "Q8" H 8950 4650 50 0000 R CNN +F 1 "eSim_NPN" H 9000 4750 50 0000 R CNN +F 2 "" H 9250 4700 29 0000 C CNN +F 3 "" H 9050 4600 60 0000 C CNN + 1 9050 4600 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 69996E34 +P 9050 5300 +F 0 "Q9" H 8950 5350 50 0000 R CNN +F 1 "eSim_NPN" H 9000 5450 50 0000 R CNN +F 2 "" H 9250 5400 29 0000 C CNN +F 3 "" H 9050 5300 60 0000 C CNN + 1 9050 5300 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 69996E3A +P 9050 5700 +F 0 "Q10" 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0 "U20" H 10650 4600 30 0000 C CNN +F 1 "PORT" H 10600 4500 30 0000 C CNN +F 2 "" H 10600 4500 60 0000 C CNN +F 3 "" H 10600 4500 60 0000 C CNN + 8 10600 4500 + -1 0 0 1 +$EndComp +$Comp +L PORT U20 +U 9 1 6999BE4F +P 10600 4300 +F 0 "U20" H 10650 4400 30 0000 C CNN +F 1 "PORT" H 10600 4300 30 0000 C CNN +F 2 "" H 10600 4300 60 0000 C CNN +F 3 "" H 10600 4300 60 0000 C CNN + 9 10600 4300 + -1 0 0 1 +$EndComp +$Comp +L PORT U20 +U 10 1 6999BEC4 +P 10600 2300 +F 0 "U20" H 10650 2400 30 0000 C CNN +F 1 "PORT" H 10600 2300 30 0000 C CNN +F 2 "" H 10600 2300 60 0000 C CNN +F 3 "" H 10600 2300 60 0000 C CNN + 10 10600 2300 + -1 0 0 1 +$EndComp +$Comp +L PORT U20 +U 11 1 6999BF33 +P 10600 2500 +F 0 "U20" H 10650 2600 30 0000 C CNN +F 1 "PORT" H 10600 2500 30 0000 C CNN +F 2 "" H 10600 2500 60 0000 C CNN +F 3 "" H 10600 2500 60 0000 C CNN + 11 10600 2500 + -1 0 0 1 +$EndComp +$Comp +L PORT U20 +U 12 1 6999BFC2 +P 2000 6900 +F 0 "U20" H 2050 7000 30 0000 C CNN +F 1 "PORT" H 2000 6900 30 0000 C CNN +F 2 "" H 2000 6900 60 0000 C CNN +F 3 "" H 2000 6900 60 0000 C CNN + 12 2000 6900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U20 +U 13 1 6999C04D +P 10600 3450 +F 0 "U20" H 10650 3550 30 0000 C CNN +F 1 "PORT" H 10600 3450 30 0000 C CNN +F 2 "" H 10600 3450 60 0000 C CNN +F 3 "" H 10600 3450 60 0000 C CNN + 13 10600 3450 + -1 0 0 1 +$EndComp +$Comp +L PORT U20 +U 14 1 6999C0D2 +P 10600 3250 +F 0 "U20" H 10650 3350 30 0000 C CNN +F 1 "PORT" H 10600 3250 30 0000 C CNN +F 2 "" H 10600 3250 60 0000 C CNN +F 3 "" H 10600 3250 60 0000 C CNN + 14 10600 3250 + -1 0 0 1 +$EndComp +Wire Wire Line + 3150 1900 3250 1900 +Connection ~ 3250 1900 +Connection ~ 8650 5500 +Text GLabel 2400 6900 2 60 Input ~ 0 +GND +Wire Wire Line + 2250 6900 2400 6900 +Text GLabel 10850 1300 2 60 Input ~ 0 +GND +Text GLabel 10700 1700 2 60 Input ~ 0 +GND +Text GLabel 10750 2300 2 60 Input ~ 0 +GND +Text GLabel 10750 2700 2 60 Input ~ 0 +GND +Text GLabel 10750 3700 2 60 Input ~ 0 +GND +Text GLabel 10750 4250 2 60 Input ~ 0 +GND +Text GLabel 10750 4700 2 60 Input ~ 0 +GND +Text GLabel 10750 5300 2 60 Input ~ 0 +GND +Text GLabel 10750 5750 2 60 Input ~ 0 +GND +Wire Wire Line + 1650 5150 1100 5150 +Wire Wire Line + 950 1050 3550 1050 +$Comp +L PORT U20 +U 15 1 6999F9E9 +P 10600 5400 +F 0 "U20" H 10650 5500 30 0000 C CNN +F 1 "PORT" H 10600 5400 30 0000 C CNN +F 2 "" H 10600 5400 60 0000 C CNN +F 3 "" H 10600 5400 60 0000 C CNN + 15 10600 5400 + -1 0 0 1 +$EndComp +$Comp +L PORT U20 +U 16 1 6999FB0C +P 10600 5600 +F 0 "U20" H 10650 5700 30 0000 C CNN +F 1 "PORT" H 10600 5600 30 0000 C CNN +F 2 "" H 10600 5600 60 0000 C CNN +F 3 "" H 10600 5600 60 0000 C CNN + 16 10600 5600 + -1 0 0 1 +$EndComp +NoConn ~ 1050 7500 +Wire Wire Line + 10200 1200 10850 1200 +Wire Wire Line + 10850 1200 10850 1300 +Text GLabel 10750 3100 2 60 Input ~ 0 +GND +$Comp +L dac_bridge_1 U22 +U 1 1 699A260C +P 7700 1050 +F 0 "U22" H 7700 1050 60 0000 C CNN +F 1 "dac_bridge_1" H 7700 1200 60 0000 C CNN +F 2 "" H 7700 1050 60 0000 C CNN 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CNN + 1 7700 5050 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U27 +U 1 1 699A2A4B +P 7850 6100 +F 0 "U27" H 7850 6100 60 0000 C CNN +F 1 "dac_bridge_1" H 7850 6250 60 0000 C CNN +F 2 "" H 7850 6100 60 0000 C CNN +F 3 "" H 7850 6100 60 0000 C CNN + 1 7850 6100 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U21 +U 1 1 699A2B08 +P 5200 6400 +F 0 "U21" H 5200 6400 60 0000 C CNN +F 1 "dac_bridge_1" H 5200 6550 60 0000 C CNN +F 2 "" H 5200 6400 60 0000 C CNN +F 3 "" H 5200 6400 60 0000 C CNN + 1 5200 6400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 1100 7100 1100 +Wire Wire Line + 7100 1100 7100 1000 +Wire Wire Line + 8250 1000 8250 1100 +Wire Wire Line + 8250 1100 8650 1100 +Wire Wire Line + 5050 2500 7100 2500 +Wire Wire Line + 7100 2500 7100 2350 +Wire Wire Line + 8250 2350 8250 2500 +Wire Wire Line + 8250 2500 8850 2500 +Wire Wire Line + 5050 3350 7100 3350 +Wire Wire Line + 7100 3350 7100 3150 +Wire Wire Line + 8250 3150 8250 3350 +Wire Wire Line + 8250 3350 8650 3350 +Wire Wire Line + 5100 4250 7100 4250 +Wire Wire Line + 7100 4250 7100 4100 +Wire Wire Line + 8250 4100 8250 4250 +Wire Wire Line + 8250 4250 8700 4250 +Wire Wire Line + 3650 5150 7100 5150 +Wire Wire Line + 7100 5150 7100 5000 +Wire Wire Line + 8250 5000 8250 5150 +Wire Wire Line + 8250 5150 8950 5150 +Wire Wire Line + 5750 6350 9050 6350 +Wire Wire Line + 8650 5500 8400 5500 +Wire Wire Line + 8400 5500 8400 6050 +Wire Wire Line + 8200 5500 8200 5850 +Wire Wire Line + 8200 5850 7250 5850 +Wire Wire Line + 7250 5850 7250 6050 +Wire Wire Line + 2600 6350 4600 6350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74141/74141.sub b/library/SubcircuitLibrary/74141/74141.sub new file mode 100644 index 000000000..e5b5394b0 --- /dev/null +++ b/library/SubcircuitLibrary/74141/74141.sub @@ -0,0 +1,127 @@ +* Subcircuit 74141 +.subckt 74141 net-_q1-pad1_ net-_q2-pad3_ net-_u20-pad3_ net-_u1-pad1_ ? net-_u2-pad2_ net-_u1-pad2_ net-_q8-pad3_ net-_q7-pad1_ net-_q3-pad1_ net-_q4-pad3_ gnd net-_q6-pad3_ net-_q5-pad1_ net-_q9-pad1_ net-_q10-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\74141\74141.cir +.include 3_and.sub +.include 5_and.sub +.include NPN.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q1-pad3_ net-_q10-pad2_ net-_q2-pad3_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad2_ net-_q3-pad3_ Q2N2222 +q4 net-_q3-pad3_ net-_q10-pad2_ net-_q4-pad3_ Q2N2222 +q5 net-_q5-pad1_ net-_q1-pad2_ net-_q5-pad3_ Q2N2222 +q6 net-_q5-pad3_ net-_q10-pad2_ net-_q6-pad3_ Q2N2222 +q7 net-_q7-pad1_ net-_q1-pad2_ net-_q7-pad3_ Q2N2222 +q8 net-_q7-pad3_ net-_q10-pad2_ net-_q8-pad3_ Q2N2222 +q9 net-_q9-pad1_ net-_q1-pad2_ net-_q10-pad1_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +* u10 gnd net-_q1-pad1_ zener +* u11 gnd net-_q2-pad3_ zener +* u12 gnd net-_q3-pad1_ zener +* u13 gnd net-_q4-pad3_ zener +* u14 gnd net-_q5-pad1_ zener +* u15 gnd net-_q6-pad3_ zener +* u16 gnd net-_q7-pad1_ zener +* u17 gnd net-_q8-pad3_ zener +* u18 gnd net-_q9-pad1_ zener +* u19 gnd net-_q10-pad3_ zener +x4 net-_u22-pad1_ net-_u23-pad1_ net-_u24-pad1_ net-_u25-pad1_ net-_u4-pad3_ net-_u27-pad1_ 5_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ d_and +* u2 net-_u1-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u4 net-_u1-pad3_ net-_u2-pad3_ net-_u4-pad3_ d_nor +* u6 net-_u1-pad1_ net-_u4-pad3_ net-_u22-pad1_ d_nand +* u3 net-_u20-pad3_ net-_u21-pad1_ d_inverter +* u5 net-_u21-pad1_ net-_u26-pad1_ d_inverter +x3 net-_u23-pad1_ net-_u4-pad3_ net-_u2-pad2_ net-_u9-pad1_ 3_and +x2 net-_u4-pad3_ net-_u1-pad2_ net-_u23-pad1_ net-_u8-pad1_ 3_and +x1 net-_u1-pad2_ net-_u4-pad3_ net-_u2-pad2_ net-_u7-pad1_ 3_and +* u7 net-_u7-pad1_ net-_u23-pad1_ d_inverter +* u8 net-_u8-pad1_ net-_u24-pad1_ d_inverter +* u9 net-_u9-pad1_ net-_u25-pad1_ d_inverter +* u22 net-_u22-pad1_ net-_q1-pad3_ dac_bridge_1 +* u23 net-_u23-pad1_ net-_q3-pad3_ dac_bridge_1 +* u24 net-_u24-pad1_ net-_q5-pad3_ dac_bridge_1 +* u25 net-_u25-pad1_ net-_q7-pad3_ dac_bridge_1 +* u26 net-_u26-pad1_ net-_q1-pad2_ dac_bridge_1 +* u27 net-_u27-pad1_ net-_q10-pad1_ dac_bridge_1 +* u21 net-_u21-pad1_ net-_q10-pad2_ dac_bridge_1 +a1 gnd net-_q1-pad1_ u10 +a2 gnd net-_q2-pad3_ u11 +a3 gnd net-_q3-pad1_ u12 +a4 gnd net-_q4-pad3_ u13 +a5 gnd net-_q5-pad1_ u14 +a6 gnd net-_q6-pad3_ u15 +a7 gnd net-_q7-pad1_ u16 +a8 gnd net-_q8-pad3_ u17 +a9 gnd net-_q9-pad1_ u18 +a10 gnd net-_q10-pad3_ u19 +a11 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u1-pad3_ u1 +a12 [net-_u1-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a13 [net-_u1-pad3_ net-_u2-pad3_ ] net-_u4-pad3_ u4 +a14 [net-_u1-pad1_ net-_u4-pad3_ ] net-_u22-pad1_ u6 +a15 net-_u20-pad3_ net-_u21-pad1_ u3 +a16 net-_u21-pad1_ net-_u26-pad1_ u5 +a17 net-_u7-pad1_ net-_u23-pad1_ u7 +a18 net-_u8-pad1_ net-_u24-pad1_ u8 +a19 net-_u9-pad1_ net-_u25-pad1_ u9 +a20 [net-_u22-pad1_ ] [net-_q1-pad3_ ] u22 +a21 [net-_u23-pad1_ ] [net-_q3-pad3_ ] u23 +a22 [net-_u24-pad1_ ] [net-_q5-pad3_ ] u24 +a23 [net-_u25-pad1_ ] [net-_q7-pad3_ ] u25 +a24 [net-_u26-pad1_ ] [net-_q1-pad2_ ] u26 +a25 [net-_u27-pad1_ ] [net-_q10-pad1_ ] u27 +a26 [net-_u21-pad1_ ] [net-_q10-pad2_ ] u21 +* Schematic Name: zener, NgSpice Name: zener +.model u10 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u11 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u12 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u13 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u14 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u15 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u16 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u17 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u18 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u19 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u1 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u6 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u22 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u23 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u26 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u27 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u21 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends 74141 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74141/74141_Previous_Values.xml b/library/SubcircuitLibrary/74141/74141_Previous_Values.xml new file mode 100644 index 000000000..415c2888c --- /dev/null +++ b/library/SubcircuitLibrary/74141/74141_Previous_Values.xml @@ -0,0 +1 @@ +zenerzenerzenerzenerzenerzenerzenerzenerzenerzenerd_andd_andd_nord_nandd_inverterd_inverterd_inverterd_inverterd_inverterdac_bridgedac_bridgedac_bridgedac_bridgedac_bridgedac_bridgedac_bridgeC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/74141/NPN.lib b/library/SubcircuitLibrary/74141/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/74141/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/74141/analysis b/library/SubcircuitLibrary/74141/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/74141/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HCT165/3_and-cache.lib b/library/SubcircuitLibrary/74HCT165/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/74HCT165/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74HCT165/3_and.cir b/library/SubcircuitLibrary/74HCT165/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/74HCT165/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/74HCT165/3_and.cir.out b/library/SubcircuitLibrary/74HCT165/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/74HCT165/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74HCT165/3_and.pro b/library/SubcircuitLibrary/74HCT165/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/74HCT165/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/74HCT165/3_and.sch b/library/SubcircuitLibrary/74HCT165/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/74HCT165/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74HCT165/3_and.sub b/library/SubcircuitLibrary/74HCT165/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/74HCT165/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HCT165/3_and_Previous_Values.xml b/library/SubcircuitLibrary/74HCT165/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/74HCT165/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HCT165/74HCT165-cache.lib b/library/SubcircuitLibrary/74HCT165/74HCT165-cache.lib new file mode 100644 index 000000000..69fde18c4 --- /dev/null +++ b/library/SubcircuitLibrary/74HCT165/74HCT165-cache.lib @@ -0,0 +1,125 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_buffer +# +DEF d_buffer U 0 40 Y Y 1 F N +F0 "U" 0 -50 60 H V C CNN +F1 "d_buffer" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N +X IN 1 -500 0 200 R 50 50 1 1 I +X OUT 2 650 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_dff +# +DEF d_dff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_dff" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 350 450 -350 -400 0 1 0 N +X Din 1 -550 350 200 R 50 50 1 1 I +X Clk 2 -550 -300 200 R 50 50 1 1 I C +X Set 3 0 650 200 D 50 50 1 1 I +X Reset 4 0 -600 200 U 50 50 1 1 I +X Dout 5 550 350 200 L 50 50 1 1 O +X Ndout 6 550 -300 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74HCT165/74HCT165.cir b/library/SubcircuitLibrary/74HCT165/74HCT165.cir new file mode 100644 index 000000000..b9cbbdc68 --- /dev/null +++ b/library/SubcircuitLibrary/74HCT165/74HCT165.cir @@ -0,0 +1,69 @@ +* C:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\74HCT165\74HCT165.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/22/26 16:11:17 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad4_ Net-_U12-Pad5_ ? d_dff +U9 Net-_U14-Pad2_ Net-_U10-Pad2_ Net-_U10-Pad1_ d_nand +U11 Net-_U10-Pad1_ Net-_U11-Pad2_ d_inverter +U14 Net-_U1-Pad11_ Net-_U14-Pad2_ d_buffer +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nand +U13 Net-_U10-Pad3_ Net-_U12-Pad4_ d_inverter +U18 Net-_U12-Pad5_ Net-_U12-Pad2_ Net-_U17-Pad2_ Net-_U18-Pad4_ Net-_U18-Pad5_ ? d_dff +U15 Net-_U15-Pad1_ Net-_U10-Pad2_ Net-_U15-Pad3_ d_nand +U17 Net-_U15-Pad3_ Net-_U17-Pad2_ d_inverter +U20 Net-_U1-Pad12_ Net-_U15-Pad1_ d_buffer +U16 Net-_U15-Pad3_ Net-_U10-Pad2_ Net-_U16-Pad3_ d_nand +U19 Net-_U16-Pad3_ Net-_U18-Pad4_ d_inverter +U24 Net-_U18-Pad5_ Net-_U12-Pad2_ Net-_U23-Pad2_ Net-_U24-Pad4_ Net-_U24-Pad5_ ? d_dff +U21 Net-_U21-Pad1_ Net-_U10-Pad2_ Net-_U21-Pad3_ d_nand +U23 Net-_U21-Pad3_ Net-_U23-Pad2_ d_inverter +U26 Net-_U1-Pad13_ Net-_U21-Pad1_ d_buffer +U22 Net-_U21-Pad3_ Net-_U10-Pad2_ Net-_U22-Pad3_ d_nand +U25 Net-_U22-Pad3_ Net-_U24-Pad4_ d_inverter +U30 Net-_U24-Pad5_ Net-_U12-Pad2_ Net-_U29-Pad2_ Net-_U30-Pad4_ Net-_U30-Pad5_ ? d_dff +U27 Net-_U27-Pad1_ Net-_U10-Pad2_ Net-_U27-Pad3_ d_nand +U29 Net-_U27-Pad3_ Net-_U29-Pad2_ d_inverter +U32 Net-_U1-Pad14_ Net-_U27-Pad1_ d_buffer +U28 Net-_U27-Pad3_ Net-_U10-Pad2_ Net-_U28-Pad3_ d_nand +U31 Net-_U28-Pad3_ Net-_U30-Pad4_ d_inverter +U36 Net-_U30-Pad5_ Net-_U12-Pad2_ Net-_U35-Pad2_ Net-_U36-Pad4_ Net-_U36-Pad5_ ? d_dff +U33 Net-_U33-Pad1_ Net-_U10-Pad2_ Net-_U33-Pad3_ d_nand +U35 Net-_U33-Pad3_ Net-_U35-Pad2_ d_inverter +U38 Net-_U1-Pad3_ Net-_U33-Pad1_ d_buffer +U34 Net-_U33-Pad3_ Net-_U10-Pad2_ Net-_U34-Pad3_ d_nand +U37 Net-_U34-Pad3_ Net-_U36-Pad4_ d_inverter +U42 Net-_U36-Pad5_ Net-_U12-Pad2_ Net-_U41-Pad2_ Net-_U42-Pad4_ Net-_U42-Pad5_ ? d_dff +U39 Net-_U39-Pad1_ Net-_U10-Pad2_ Net-_U39-Pad3_ d_nand +U41 Net-_U39-Pad3_ Net-_U41-Pad2_ d_inverter +U44 Net-_U1-Pad4_ Net-_U39-Pad1_ d_buffer +U40 Net-_U39-Pad3_ Net-_U10-Pad2_ Net-_U40-Pad3_ d_nand +U43 Net-_U40-Pad3_ Net-_U42-Pad4_ d_inverter +U48 Net-_U42-Pad5_ Net-_U12-Pad2_ Net-_U47-Pad2_ Net-_U48-Pad4_ Net-_U48-Pad5_ ? d_dff +U45 Net-_U45-Pad1_ Net-_U10-Pad2_ Net-_U45-Pad3_ d_nand +U47 Net-_U45-Pad3_ Net-_U47-Pad2_ d_inverter +U50 Net-_U1-Pad5_ Net-_U45-Pad1_ d_buffer +U46 Net-_U45-Pad3_ Net-_U10-Pad2_ Net-_U46-Pad3_ d_nand +U49 Net-_U46-Pad3_ Net-_U48-Pad4_ d_inverter +U54 Net-_U48-Pad5_ Net-_U12-Pad2_ Net-_U53-Pad2_ Net-_U54-Pad4_ Net-_U54-Pad5_ Net-_U54-Pad6_ d_dff +U51 Net-_U51-Pad1_ Net-_U10-Pad2_ Net-_U51-Pad3_ d_nand +U53 Net-_U51-Pad3_ Net-_U53-Pad2_ d_inverter +U56 Net-_U1-Pad6_ Net-_U51-Pad1_ d_buffer +U52 Net-_U51-Pad3_ Net-_U10-Pad2_ Net-_U52-Pad3_ d_nand +U55 Net-_U52-Pad3_ Net-_U54-Pad4_ d_inverter +U57 Net-_U54-Pad5_ Net-_U1-Pad9_ d_buffer +U58 Net-_U54-Pad6_ Net-_U1-Pad7_ d_buffer +U6 Net-_U1-Pad10_ Net-_U6-Pad2_ d_inverter +U7 Net-_U6-Pad2_ Net-_U12-Pad1_ d_inverter +X1 Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U5-Pad2_ Net-_U8-Pad1_ 3_and +U8 Net-_U8-Pad1_ Net-_U12-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad15_ Net-_U4-Pad2_ d_inverter +U2 Net-_U1-Pad1_ Net-_U10-Pad2_ d_inverter +U5 Net-_U10-Pad2_ Net-_U5-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/74HCT165/74HCT165.cir.out b/library/SubcircuitLibrary/74HCT165/74HCT165.cir.out new file mode 100644 index 000000000..b88d71514 --- /dev/null +++ b/library/SubcircuitLibrary/74HCT165/74HCT165.cir.out @@ -0,0 +1,242 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\74hct165\74hct165.cir + +.include 3_and.sub +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad2_ net-_u12-pad4_ net-_u12-pad5_ ? d_dff +* u9 net-_u14-pad2_ net-_u10-pad2_ net-_u10-pad1_ d_nand +* u11 net-_u10-pad1_ net-_u11-pad2_ d_inverter +* u14 net-_u1-pad11_ net-_u14-pad2_ d_buffer +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u13 net-_u10-pad3_ net-_u12-pad4_ d_inverter +* u18 net-_u12-pad5_ net-_u12-pad2_ net-_u17-pad2_ net-_u18-pad4_ net-_u18-pad5_ ? d_dff +* u15 net-_u15-pad1_ net-_u10-pad2_ net-_u15-pad3_ d_nand +* u17 net-_u15-pad3_ net-_u17-pad2_ d_inverter +* u20 net-_u1-pad12_ net-_u15-pad1_ d_buffer +* u16 net-_u15-pad3_ net-_u10-pad2_ net-_u16-pad3_ d_nand +* u19 net-_u16-pad3_ net-_u18-pad4_ d_inverter +* u24 net-_u18-pad5_ net-_u12-pad2_ net-_u23-pad2_ net-_u24-pad4_ net-_u24-pad5_ ? d_dff +* u21 net-_u21-pad1_ net-_u10-pad2_ net-_u21-pad3_ d_nand +* u23 net-_u21-pad3_ net-_u23-pad2_ d_inverter +* u26 net-_u1-pad13_ net-_u21-pad1_ d_buffer +* u22 net-_u21-pad3_ net-_u10-pad2_ net-_u22-pad3_ d_nand +* u25 net-_u22-pad3_ net-_u24-pad4_ d_inverter +* u30 net-_u24-pad5_ net-_u12-pad2_ net-_u29-pad2_ net-_u30-pad4_ net-_u30-pad5_ ? d_dff +* u27 net-_u27-pad1_ net-_u10-pad2_ net-_u27-pad3_ d_nand +* u29 net-_u27-pad3_ net-_u29-pad2_ d_inverter +* u32 net-_u1-pad14_ net-_u27-pad1_ d_buffer +* u28 net-_u27-pad3_ net-_u10-pad2_ net-_u28-pad3_ d_nand +* u31 net-_u28-pad3_ net-_u30-pad4_ d_inverter +* u36 net-_u30-pad5_ net-_u12-pad2_ net-_u35-pad2_ net-_u36-pad4_ net-_u36-pad5_ ? d_dff +* u33 net-_u33-pad1_ net-_u10-pad2_ net-_u33-pad3_ d_nand +* u35 net-_u33-pad3_ net-_u35-pad2_ d_inverter +* u38 net-_u1-pad3_ net-_u33-pad1_ d_buffer +* u34 net-_u33-pad3_ net-_u10-pad2_ net-_u34-pad3_ d_nand +* u37 net-_u34-pad3_ net-_u36-pad4_ d_inverter +* u42 net-_u36-pad5_ net-_u12-pad2_ net-_u41-pad2_ net-_u42-pad4_ net-_u42-pad5_ ? d_dff +* u39 net-_u39-pad1_ net-_u10-pad2_ net-_u39-pad3_ d_nand +* u41 net-_u39-pad3_ net-_u41-pad2_ d_inverter +* u44 net-_u1-pad4_ net-_u39-pad1_ d_buffer +* u40 net-_u39-pad3_ net-_u10-pad2_ net-_u40-pad3_ d_nand +* u43 net-_u40-pad3_ net-_u42-pad4_ d_inverter +* u48 net-_u42-pad5_ net-_u12-pad2_ net-_u47-pad2_ net-_u48-pad4_ net-_u48-pad5_ ? d_dff +* u45 net-_u45-pad1_ net-_u10-pad2_ net-_u45-pad3_ d_nand +* u47 net-_u45-pad3_ net-_u47-pad2_ d_inverter +* u50 net-_u1-pad5_ net-_u45-pad1_ d_buffer +* u46 net-_u45-pad3_ net-_u10-pad2_ net-_u46-pad3_ d_nand +* u49 net-_u46-pad3_ net-_u48-pad4_ d_inverter +* u54 net-_u48-pad5_ net-_u12-pad2_ net-_u53-pad2_ net-_u54-pad4_ net-_u54-pad5_ net-_u54-pad6_ d_dff +* u51 net-_u51-pad1_ net-_u10-pad2_ net-_u51-pad3_ d_nand +* u53 net-_u51-pad3_ net-_u53-pad2_ d_inverter +* u56 net-_u1-pad6_ net-_u51-pad1_ d_buffer +* u52 net-_u51-pad3_ net-_u10-pad2_ net-_u52-pad3_ d_nand +* u55 net-_u52-pad3_ net-_u54-pad4_ d_inverter +* u57 net-_u54-pad5_ net-_u1-pad9_ d_buffer +* u58 net-_u54-pad6_ net-_u1-pad7_ d_buffer +* u6 net-_u1-pad10_ net-_u6-pad2_ d_inverter +* u7 net-_u6-pad2_ net-_u12-pad1_ d_inverter +x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u8-pad1_ 3_and +* u8 net-_u8-pad1_ net-_u12-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad15_ net-_u4-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u10-pad2_ d_inverter +* u5 net-_u10-pad2_ net-_u5-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +a1 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad2_ net-_u12-pad4_ net-_u12-pad5_ ? u12 +a2 [net-_u14-pad2_ net-_u10-pad2_ ] net-_u10-pad1_ u9 +a3 net-_u10-pad1_ net-_u11-pad2_ u11 +a4 net-_u1-pad11_ net-_u14-pad2_ u14 +a5 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a6 net-_u10-pad3_ net-_u12-pad4_ u13 +a7 net-_u12-pad5_ net-_u12-pad2_ net-_u17-pad2_ net-_u18-pad4_ net-_u18-pad5_ ? u18 +a8 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u15-pad3_ u15 +a9 net-_u15-pad3_ net-_u17-pad2_ u17 +a10 net-_u1-pad12_ net-_u15-pad1_ u20 +a11 [net-_u15-pad3_ net-_u10-pad2_ ] net-_u16-pad3_ u16 +a12 net-_u16-pad3_ net-_u18-pad4_ u19 +a13 net-_u18-pad5_ net-_u12-pad2_ net-_u23-pad2_ net-_u24-pad4_ net-_u24-pad5_ ? u24 +a14 [net-_u21-pad1_ net-_u10-pad2_ ] net-_u21-pad3_ u21 +a15 net-_u21-pad3_ net-_u23-pad2_ u23 +a16 net-_u1-pad13_ net-_u21-pad1_ u26 +a17 [net-_u21-pad3_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a18 net-_u22-pad3_ net-_u24-pad4_ u25 +a19 net-_u24-pad5_ net-_u12-pad2_ net-_u29-pad2_ net-_u30-pad4_ net-_u30-pad5_ ? u30 +a20 [net-_u27-pad1_ net-_u10-pad2_ ] net-_u27-pad3_ u27 +a21 net-_u27-pad3_ net-_u29-pad2_ u29 +a22 net-_u1-pad14_ net-_u27-pad1_ u32 +a23 [net-_u27-pad3_ net-_u10-pad2_ ] net-_u28-pad3_ u28 +a24 net-_u28-pad3_ net-_u30-pad4_ u31 +a25 net-_u30-pad5_ net-_u12-pad2_ net-_u35-pad2_ net-_u36-pad4_ net-_u36-pad5_ ? u36 +a26 [net-_u33-pad1_ net-_u10-pad2_ ] net-_u33-pad3_ u33 +a27 net-_u33-pad3_ net-_u35-pad2_ u35 +a28 net-_u1-pad3_ net-_u33-pad1_ u38 +a29 [net-_u33-pad3_ net-_u10-pad2_ ] net-_u34-pad3_ u34 +a30 net-_u34-pad3_ net-_u36-pad4_ u37 +a31 net-_u36-pad5_ net-_u12-pad2_ net-_u41-pad2_ net-_u42-pad4_ net-_u42-pad5_ ? u42 +a32 [net-_u39-pad1_ net-_u10-pad2_ ] net-_u39-pad3_ u39 +a33 net-_u39-pad3_ net-_u41-pad2_ u41 +a34 net-_u1-pad4_ net-_u39-pad1_ u44 +a35 [net-_u39-pad3_ net-_u10-pad2_ ] net-_u40-pad3_ u40 +a36 net-_u40-pad3_ net-_u42-pad4_ u43 +a37 net-_u42-pad5_ net-_u12-pad2_ net-_u47-pad2_ net-_u48-pad4_ net-_u48-pad5_ ? u48 +a38 [net-_u45-pad1_ net-_u10-pad2_ ] net-_u45-pad3_ u45 +a39 net-_u45-pad3_ net-_u47-pad2_ u47 +a40 net-_u1-pad5_ net-_u45-pad1_ u50 +a41 [net-_u45-pad3_ net-_u10-pad2_ ] net-_u46-pad3_ u46 +a42 net-_u46-pad3_ net-_u48-pad4_ u49 +a43 net-_u48-pad5_ net-_u12-pad2_ net-_u53-pad2_ net-_u54-pad4_ net-_u54-pad5_ net-_u54-pad6_ u54 +a44 [net-_u51-pad1_ net-_u10-pad2_ ] net-_u51-pad3_ u51 +a45 net-_u51-pad3_ net-_u53-pad2_ u53 +a46 net-_u1-pad6_ net-_u51-pad1_ u56 +a47 [net-_u51-pad3_ net-_u10-pad2_ ] net-_u52-pad3_ u52 +a48 net-_u52-pad3_ net-_u54-pad4_ u55 +a49 net-_u54-pad5_ net-_u1-pad9_ u57 +a50 net-_u54-pad6_ net-_u1-pad7_ u58 +a51 net-_u1-pad10_ net-_u6-pad2_ u6 +a52 net-_u6-pad2_ net-_u12-pad1_ u7 +a53 net-_u8-pad1_ net-_u12-pad2_ u8 +a54 net-_u1-pad2_ net-_u3-pad2_ u3 +a55 net-_u1-pad15_ net-_u4-pad2_ u4 +a56 net-_u1-pad1_ net-_u10-pad2_ u2 +a57 net-_u10-pad2_ net-_u5-pad2_ u5 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u12 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u14 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u18 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u20 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u24 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u32 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u36 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u38 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u42 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u44 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u48 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u45 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u50 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u54 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u53 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u56 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u52 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u57 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u58 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74HCT165/74HCT165.pro b/library/SubcircuitLibrary/74HCT165/74HCT165.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/74HCT165/74HCT165.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/74HCT165/74HCT165.sch b/library/SubcircuitLibrary/74HCT165/74HCT165.sch new file mode 100644 index 000000000..0115af1ad --- /dev/null +++ b/library/SubcircuitLibrary/74HCT165/74HCT165.sch @@ -0,0 +1,1213 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:74HCT165-cache +EELAYER 25 0 +EELAYER END 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25300 9300 +Wire Wire Line + 25250 13150 25250 13000 +Wire Wire Line + 25250 12250 25250 12400 +Wire Wire Line + 25300 14050 25300 14150 +Wire Wire Line + 25800 11300 26650 11300 +Wire Wire Line + 25300 14150 26050 14150 +Wire Wire Line + 26050 14150 26050 10300 +Wire Wire Line + 26050 10300 25250 10300 +Connection ~ 25250 10300 +Wire Wire Line + 23900 11300 24700 11300 +Wire Wire Line + 24500 14350 24500 11950 +Wire Wire Line + 24500 11950 24700 11950 +Wire Wire Line + 23300 9300 23300 9150 +Connection ~ 23300 9150 +Wire Wire Line + 25200 9300 25200 9150 +Wire Wire Line + 23400 7850 23400 7700 +Wire Wire Line + 25300 7850 25300 7700 +Wire Wire Line + 22800 11950 22350 11950 +Wire Wire Line + 22350 11950 22350 14350 +Connection ~ 22350 14350 +Wire Wire Line + 18300 11950 18000 11950 +Wire Wire Line + 18000 11950 18000 14350 +Connection ~ 18000 14350 +NoConn ~ 10400 11950 +NoConn ~ 12300 11950 +NoConn ~ 14900 11950 +NoConn ~ 16800 11950 +NoConn ~ 19400 11950 +NoConn ~ 21300 11950 +NoConn ~ 23900 11950 +Wire Wire Line + 25800 11950 26700 11950 +$Comp +L d_buffer U57 +U 1 1 699B0124 +P 27150 11300 +F 0 "U57" H 27150 11250 60 0000 C CNN +F 1 "d_buffer" H 27150 11350 60 0000 C CNN +F 2 "" H 27150 11300 60 0000 C CNN +F 3 "" H 27150 11300 60 0000 C CNN + 1 27150 11300 + 1 0 0 -1 +$EndComp +$Comp +L d_buffer U58 +U 1 1 699B033E +P 27200 11950 +F 0 "U58" H 27200 11900 60 0000 C CNN +F 1 "d_buffer" H 27200 12000 60 0000 C CNN +F 2 "" H 27200 11950 60 0000 C CNN +F 3 "" H 27200 11950 60 0000 C CNN + 1 27200 11950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8750 11950 9300 11950 +Wire Wire Line + 8950 11950 8950 14350 +Wire Wire Line + 8550 9150 8550 14500 +$Comp +L d_inverter U6 +U 1 1 699B1535 +P 7100 10550 +F 0 "U6" H 7100 10450 60 0000 C CNN +F 1 "d_inverter" H 7100 10700 60 0000 C CNN +F 2 "" H 7150 10500 60 0000 C CNN +F 3 "" H 7150 10500 60 0000 C CNN + 1 7100 10550 + 1 0 0 1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 699B171A +P 8000 10550 +F 0 "U7" H 8000 10450 60 0000 C CNN +F 1 "d_inverter" H 8000 10700 60 0000 C CNN +F 2 "" H 8050 10500 60 0000 C CNN +F 3 "" H 8050 10500 60 0000 C CNN + 1 8000 10550 + 1 0 0 1 +$EndComp +$Comp +L 3_and X1 +U 1 1 699ADAE2 +P 7100 12050 +F 0 "X1" H 7200 12000 60 0000 C CNN +F 1 "3_and" H 7250 12200 60 0000 C CNN +F 2 "" H 7100 12050 60 0000 C CNN +F 3 "" H 7100 12050 60 0000 C CNN + 1 7100 12050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 699ADEBA +P 8000 12000 +F 0 "U8" H 8000 11900 60 0000 C CNN +F 1 "d_inverter" H 8000 12150 60 0000 C CNN +F 2 "" H 8050 11950 60 0000 C CNN +F 3 "" H 8050 11950 60 0000 C CNN + 1 8000 12000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7600 12000 7700 12000 +$Comp +L d_inverter U3 +U 1 1 699AE6A1 +P 6150 11700 +F 0 "U3" H 6150 11600 60 0000 C CNN +F 1 "d_inverter" H 6150 11850 60 0000 C CNN +F 2 "" H 6200 11650 60 0000 C CNN +F 3 "" H 6200 11650 60 0000 C CNN + 1 6150 11700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 699AE7FC +P 6150 12050 +F 0 "U4" H 6150 11950 60 0000 C CNN +F 1 "d_inverter" H 6150 12200 60 0000 C CNN +F 2 "" H 6200 12000 60 0000 C CNN +F 3 "" H 6200 12000 60 0000 C CNN + 1 6150 12050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 699AE8D0 +P 5450 12550 +F 0 "U2" H 5450 12450 60 0000 C CNN +F 1 "d_inverter" H 5450 12700 60 0000 C CNN +F 2 "" H 5500 12500 60 0000 C CNN +F 3 "" H 5500 12500 60 0000 C CNN + 1 5450 12550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 699AE9AF +P 6300 12550 +F 0 "U5" H 6300 12450 60 0000 C CNN +F 1 "d_inverter" H 6300 12700 60 0000 C CNN +F 2 "" H 6350 12500 60 0000 C CNN +F 3 "" H 6350 12500 60 0000 C CNN + 1 6300 12550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6450 11700 6700 11700 +Wire Wire Line + 6700 11700 6700 11900 +Wire Wire Line + 6700 11900 6750 11900 +Wire Wire Line + 6450 12050 6600 12050 +Wire Wire Line + 6600 12050 6600 12000 +Wire Wire Line + 6600 12000 6750 12000 +Wire Wire Line + 6750 12100 6600 12100 +Wire Wire Line + 6600 12100 6600 12550 +Wire Wire Line + 5750 12550 6000 12550 +Wire Wire Line + 5850 11700 5650 11700 +Wire Wire Line + 5850 12050 5600 12050 +Wire Wire Line + 5150 12550 4950 12550 +Wire Wire Line + 7400 10550 7700 10550 +Wire Wire Line + 8300 10550 8950 10550 +Wire Wire Line + 8950 10550 8950 11300 +Wire Wire Line + 8950 11300 9300 11300 +Wire Wire Line + 8300 12000 8750 12000 +Wire Wire Line + 8750 12000 8750 11950 +Connection ~ 8950 11950 +Wire Wire Line + 5850 12550 5850 13100 +Wire Wire Line + 5850 13100 8550 13100 +Connection ~ 8550 13100 +Connection ~ 5850 12550 +Wire Wire Line + 6800 10550 6500 10550 +Wire Wire Line + 25200 9150 8550 9150 +Wire Wire Line + 8950 14350 24500 14350 +Wire Wire Line + 25200 14050 25200 14450 +Wire Wire Line + 25200 14450 8600 14450 +Wire Wire Line + 8600 14450 8600 14500 +Wire Wire Line + 8600 14500 8550 14500 +Wire Wire Line + 9800 14050 9800 14450 +Connection ~ 9800 14450 +Wire Wire Line + 11700 14050 11700 14450 +Connection ~ 11700 14450 +Wire Wire Line + 14300 14050 14300 14450 +Connection ~ 14300 14450 +Wire Wire Line + 16200 14050 16200 14450 +Connection ~ 16200 14450 +Wire Wire Line + 18800 14050 18800 14450 +Connection ~ 18800 14450 +Wire Wire Line + 20700 14050 20700 14450 +Connection ~ 20700 14450 +Wire Wire Line + 23300 14050 23300 14450 +Connection ~ 23300 14450 +Wire Wire Line + 27800 11300 28050 11300 +Wire Wire Line + 27850 11950 28050 11950 +$Comp +L PORT U1 +U 8 1 699B91C4 +P 1050 1300 +F 0 "U1" H 1100 1400 30 0000 C CNN +F 1 "PORT" H 1050 1300 30 0000 C CNN +F 2 "" H 1050 1300 60 0000 C CNN +F 3 "" H 1050 1300 60 0000 C CNN + 8 1050 1300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 699B94A4 +P 28300 11300 +F 0 "U1" H 28350 11400 30 0000 C CNN +F 1 "PORT" H 28300 11300 30 0000 C CNN +F 2 "" H 28300 11300 60 0000 C CNN +F 3 "" H 28300 11300 60 0000 C CNN + 9 28300 11300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 699B9575 +P 6250 10550 +F 0 "U1" H 6300 10650 30 0000 C CNN +F 1 "PORT" H 6250 10550 30 0000 C CNN +F 2 "" H 6250 10550 60 0000 C CNN +F 3 "" H 6250 10550 60 0000 C CNN + 10 6250 10550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 699B9604 +P 9900 7450 +F 0 "U1" H 9950 7550 30 0000 C CNN +F 1 "PORT" H 9900 7450 30 0000 C CNN +F 2 "" H 9900 7450 60 0000 C CNN +F 3 "" H 9900 7450 60 0000 C CNN + 11 9900 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 699B9695 +P 11800 7450 +F 0 "U1" H 11850 7550 30 0000 C CNN +F 1 "PORT" H 11800 7450 30 0000 C CNN +F 2 "" H 11800 7450 60 0000 C CNN +F 3 "" H 11800 7450 60 0000 C CNN + 12 11800 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 699B973E +P 14400 7450 +F 0 "U1" H 14450 7550 30 0000 C CNN +F 1 "PORT" H 14400 7450 30 0000 C CNN +F 2 "" H 14400 7450 60 0000 C CNN +F 3 "" H 14400 7450 60 0000 C CNN + 13 14400 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 699B97D5 +P 5400 11700 +F 0 "U1" H 5450 11800 30 0000 C CNN +F 1 "PORT" H 5400 11700 30 0000 C CNN +F 2 "" H 5400 11700 60 0000 C CNN +F 3 "" H 5400 11700 60 0000 C CNN + 2 5400 11700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 699B9A78 +P 18900 7450 +F 0 "U1" H 18950 7550 30 0000 C CNN +F 1 "PORT" H 18900 7450 30 0000 C CNN +F 2 "" H 18900 7450 60 0000 C CNN +F 3 "" H 18900 7450 60 0000 C CNN + 3 18900 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 699B9D63 +P 20800 7450 +F 0 "U1" H 20850 7550 30 0000 C CNN +F 1 "PORT" H 20800 7450 30 0000 C CNN +F 2 "" H 20800 7450 60 0000 C CNN +F 3 "" H 20800 7450 60 0000 C CNN + 4 20800 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 699B9DFE +P 23400 7450 +F 0 "U1" H 23450 7550 30 0000 C CNN +F 1 "PORT" H 23400 7450 30 0000 C CNN +F 2 "" H 23400 7450 60 0000 C CNN +F 3 "" H 23400 7450 60 0000 C CNN + 5 23400 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 699B9E9B +P 4700 12550 +F 0 "U1" H 4750 12650 30 0000 C CNN +F 1 "PORT" H 4700 12550 30 0000 C CNN +F 2 "" H 4700 12550 60 0000 C CNN +F 3 "" H 4700 12550 60 0000 C CNN + 1 4700 12550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 699B9F3A +P 25300 7450 +F 0 "U1" H 25350 7550 30 0000 C CNN +F 1 "PORT" H 25300 7450 30 0000 C CNN +F 2 "" H 25300 7450 60 0000 C CNN +F 3 "" H 25300 7450 60 0000 C CNN + 6 25300 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 699BA1C5 +P 28300 11950 +F 0 "U1" H 28350 12050 30 0000 C CNN +F 1 "PORT" H 28300 11950 30 0000 C CNN +F 2 "" H 28300 11950 60 0000 C CNN +F 3 "" H 28300 11950 60 0000 C CNN + 7 28300 11950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 699BA268 +P 16300 7450 +F 0 "U1" H 16350 7550 30 0000 C CNN +F 1 "PORT" H 16300 7450 30 0000 C CNN +F 2 "" H 16300 7450 60 0000 C CNN +F 3 "" H 16300 7450 60 0000 C CNN + 14 16300 7450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 15 1 699BA505 +P 5350 12050 +F 0 "U1" H 5400 12150 30 0000 C CNN +F 1 "PORT" H 5350 12050 30 0000 C CNN +F 2 "" H 5350 12050 60 0000 C CNN +F 3 "" H 5350 12050 60 0000 C CNN + 15 5350 12050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 699BA5AC +P 1050 6200 +F 0 "U1" H 1100 6300 30 0000 C CNN +F 1 "PORT" H 1050 6200 30 0000 C CNN +F 2 "" H 1050 6200 60 0000 C CNN +F 3 "" H 1050 6200 60 0000 C CNN + 16 1050 6200 + 1 0 0 -1 +$EndComp +NoConn ~ 1300 6200 +NoConn ~ 1300 1300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74HCT165/74HCT165.sub b/library/SubcircuitLibrary/74HCT165/74HCT165.sub new file mode 100644 index 000000000..24d0619bf --- /dev/null +++ b/library/SubcircuitLibrary/74HCT165/74HCT165.sub @@ -0,0 +1,236 @@ +* Subcircuit 74HCT165 +.subckt 74HCT165 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\74hct165\74hct165.cir +.include 3_and.sub +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad2_ net-_u12-pad4_ net-_u12-pad5_ ? d_dff +* u9 net-_u14-pad2_ net-_u10-pad2_ net-_u10-pad1_ d_nand +* u11 net-_u10-pad1_ net-_u11-pad2_ d_inverter +* u14 net-_u1-pad11_ net-_u14-pad2_ d_buffer +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u13 net-_u10-pad3_ net-_u12-pad4_ d_inverter +* u18 net-_u12-pad5_ net-_u12-pad2_ net-_u17-pad2_ net-_u18-pad4_ net-_u18-pad5_ ? d_dff +* u15 net-_u15-pad1_ net-_u10-pad2_ net-_u15-pad3_ d_nand +* u17 net-_u15-pad3_ net-_u17-pad2_ d_inverter +* u20 net-_u1-pad12_ net-_u15-pad1_ d_buffer +* u16 net-_u15-pad3_ net-_u10-pad2_ net-_u16-pad3_ d_nand +* u19 net-_u16-pad3_ net-_u18-pad4_ d_inverter +* u24 net-_u18-pad5_ net-_u12-pad2_ net-_u23-pad2_ net-_u24-pad4_ net-_u24-pad5_ ? d_dff +* u21 net-_u21-pad1_ net-_u10-pad2_ net-_u21-pad3_ d_nand +* u23 net-_u21-pad3_ net-_u23-pad2_ d_inverter +* u26 net-_u1-pad13_ net-_u21-pad1_ d_buffer +* u22 net-_u21-pad3_ net-_u10-pad2_ net-_u22-pad3_ d_nand +* u25 net-_u22-pad3_ net-_u24-pad4_ d_inverter +* u30 net-_u24-pad5_ net-_u12-pad2_ net-_u29-pad2_ net-_u30-pad4_ net-_u30-pad5_ ? d_dff +* u27 net-_u27-pad1_ net-_u10-pad2_ net-_u27-pad3_ d_nand +* u29 net-_u27-pad3_ net-_u29-pad2_ d_inverter +* u32 net-_u1-pad14_ net-_u27-pad1_ d_buffer +* u28 net-_u27-pad3_ net-_u10-pad2_ net-_u28-pad3_ d_nand +* u31 net-_u28-pad3_ net-_u30-pad4_ d_inverter +* u36 net-_u30-pad5_ net-_u12-pad2_ net-_u35-pad2_ net-_u36-pad4_ net-_u36-pad5_ ? d_dff +* u33 net-_u33-pad1_ net-_u10-pad2_ net-_u33-pad3_ d_nand +* u35 net-_u33-pad3_ net-_u35-pad2_ d_inverter +* u38 net-_u1-pad3_ net-_u33-pad1_ d_buffer +* u34 net-_u33-pad3_ net-_u10-pad2_ net-_u34-pad3_ d_nand +* u37 net-_u34-pad3_ net-_u36-pad4_ d_inverter +* u42 net-_u36-pad5_ net-_u12-pad2_ net-_u41-pad2_ net-_u42-pad4_ net-_u42-pad5_ ? d_dff +* u39 net-_u39-pad1_ net-_u10-pad2_ net-_u39-pad3_ d_nand +* u41 net-_u39-pad3_ net-_u41-pad2_ d_inverter +* u44 net-_u1-pad4_ net-_u39-pad1_ d_buffer +* u40 net-_u39-pad3_ net-_u10-pad2_ net-_u40-pad3_ d_nand +* u43 net-_u40-pad3_ net-_u42-pad4_ d_inverter +* u48 net-_u42-pad5_ net-_u12-pad2_ net-_u47-pad2_ net-_u48-pad4_ net-_u48-pad5_ ? d_dff +* u45 net-_u45-pad1_ net-_u10-pad2_ net-_u45-pad3_ d_nand +* u47 net-_u45-pad3_ net-_u47-pad2_ d_inverter +* u50 net-_u1-pad5_ net-_u45-pad1_ d_buffer +* u46 net-_u45-pad3_ net-_u10-pad2_ net-_u46-pad3_ d_nand +* u49 net-_u46-pad3_ net-_u48-pad4_ d_inverter +* u54 net-_u48-pad5_ net-_u12-pad2_ net-_u53-pad2_ net-_u54-pad4_ net-_u54-pad5_ net-_u54-pad6_ d_dff +* u51 net-_u51-pad1_ net-_u10-pad2_ net-_u51-pad3_ d_nand +* u53 net-_u51-pad3_ net-_u53-pad2_ d_inverter +* u56 net-_u1-pad6_ net-_u51-pad1_ d_buffer +* u52 net-_u51-pad3_ net-_u10-pad2_ net-_u52-pad3_ d_nand +* u55 net-_u52-pad3_ net-_u54-pad4_ d_inverter +* u57 net-_u54-pad5_ net-_u1-pad9_ d_buffer +* u58 net-_u54-pad6_ net-_u1-pad7_ d_buffer +* u6 net-_u1-pad10_ net-_u6-pad2_ d_inverter +* u7 net-_u6-pad2_ net-_u12-pad1_ d_inverter +x1 net-_u3-pad2_ net-_u4-pad2_ net-_u5-pad2_ net-_u8-pad1_ 3_and +* u8 net-_u8-pad1_ net-_u12-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad15_ net-_u4-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u10-pad2_ d_inverter +* u5 net-_u10-pad2_ net-_u5-pad2_ d_inverter +a1 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad2_ net-_u12-pad4_ net-_u12-pad5_ ? u12 +a2 [net-_u14-pad2_ net-_u10-pad2_ ] net-_u10-pad1_ u9 +a3 net-_u10-pad1_ net-_u11-pad2_ u11 +a4 net-_u1-pad11_ net-_u14-pad2_ u14 +a5 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a6 net-_u10-pad3_ net-_u12-pad4_ u13 +a7 net-_u12-pad5_ net-_u12-pad2_ net-_u17-pad2_ net-_u18-pad4_ net-_u18-pad5_ ? u18 +a8 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u15-pad3_ u15 +a9 net-_u15-pad3_ net-_u17-pad2_ u17 +a10 net-_u1-pad12_ net-_u15-pad1_ u20 +a11 [net-_u15-pad3_ net-_u10-pad2_ ] net-_u16-pad3_ u16 +a12 net-_u16-pad3_ net-_u18-pad4_ u19 +a13 net-_u18-pad5_ net-_u12-pad2_ net-_u23-pad2_ net-_u24-pad4_ net-_u24-pad5_ ? u24 +a14 [net-_u21-pad1_ net-_u10-pad2_ ] net-_u21-pad3_ u21 +a15 net-_u21-pad3_ net-_u23-pad2_ u23 +a16 net-_u1-pad13_ net-_u21-pad1_ u26 +a17 [net-_u21-pad3_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a18 net-_u22-pad3_ net-_u24-pad4_ u25 +a19 net-_u24-pad5_ net-_u12-pad2_ net-_u29-pad2_ net-_u30-pad4_ net-_u30-pad5_ ? u30 +a20 [net-_u27-pad1_ net-_u10-pad2_ ] net-_u27-pad3_ u27 +a21 net-_u27-pad3_ net-_u29-pad2_ u29 +a22 net-_u1-pad14_ net-_u27-pad1_ u32 +a23 [net-_u27-pad3_ net-_u10-pad2_ ] net-_u28-pad3_ u28 +a24 net-_u28-pad3_ net-_u30-pad4_ u31 +a25 net-_u30-pad5_ net-_u12-pad2_ net-_u35-pad2_ net-_u36-pad4_ net-_u36-pad5_ ? u36 +a26 [net-_u33-pad1_ net-_u10-pad2_ ] net-_u33-pad3_ u33 +a27 net-_u33-pad3_ net-_u35-pad2_ u35 +a28 net-_u1-pad3_ net-_u33-pad1_ u38 +a29 [net-_u33-pad3_ net-_u10-pad2_ ] net-_u34-pad3_ u34 +a30 net-_u34-pad3_ net-_u36-pad4_ u37 +a31 net-_u36-pad5_ net-_u12-pad2_ net-_u41-pad2_ net-_u42-pad4_ net-_u42-pad5_ ? u42 +a32 [net-_u39-pad1_ net-_u10-pad2_ ] net-_u39-pad3_ u39 +a33 net-_u39-pad3_ net-_u41-pad2_ u41 +a34 net-_u1-pad4_ net-_u39-pad1_ u44 +a35 [net-_u39-pad3_ net-_u10-pad2_ ] net-_u40-pad3_ u40 +a36 net-_u40-pad3_ net-_u42-pad4_ u43 +a37 net-_u42-pad5_ net-_u12-pad2_ net-_u47-pad2_ net-_u48-pad4_ net-_u48-pad5_ ? u48 +a38 [net-_u45-pad1_ net-_u10-pad2_ ] net-_u45-pad3_ u45 +a39 net-_u45-pad3_ net-_u47-pad2_ u47 +a40 net-_u1-pad5_ net-_u45-pad1_ u50 +a41 [net-_u45-pad3_ net-_u10-pad2_ ] net-_u46-pad3_ u46 +a42 net-_u46-pad3_ net-_u48-pad4_ u49 +a43 net-_u48-pad5_ net-_u12-pad2_ net-_u53-pad2_ net-_u54-pad4_ net-_u54-pad5_ net-_u54-pad6_ u54 +a44 [net-_u51-pad1_ net-_u10-pad2_ ] net-_u51-pad3_ u51 +a45 net-_u51-pad3_ net-_u53-pad2_ u53 +a46 net-_u1-pad6_ net-_u51-pad1_ u56 +a47 [net-_u51-pad3_ net-_u10-pad2_ ] net-_u52-pad3_ u52 +a48 net-_u52-pad3_ net-_u54-pad4_ u55 +a49 net-_u54-pad5_ net-_u1-pad9_ u57 +a50 net-_u54-pad6_ net-_u1-pad7_ u58 +a51 net-_u1-pad10_ net-_u6-pad2_ u6 +a52 net-_u6-pad2_ net-_u12-pad1_ u7 +a53 net-_u8-pad1_ net-_u12-pad2_ u8 +a54 net-_u1-pad2_ net-_u3-pad2_ u3 +a55 net-_u1-pad15_ net-_u4-pad2_ u4 +a56 net-_u1-pad1_ net-_u10-pad2_ u2 +a57 net-_u10-pad2_ net-_u5-pad2_ u5 +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u12 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u14 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u18 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u20 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u24 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u26 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u30 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u32 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u36 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u38 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u42 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u44 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u48 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u45 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u47 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u50 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u49 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_dff, NgSpice Name: d_dff +.model u54 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u53 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u56 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u52 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u55 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u57 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_buffer, NgSpice Name: d_buffer +.model u58 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74HCT165 \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HCT165/74HCT165_Previous_Values.xml b/library/SubcircuitLibrary/74HCT165/74HCT165_Previous_Values.xml new file mode 100644 index 000000000..561b7a311 --- /dev/null +++ b/library/SubcircuitLibrary/74HCT165/74HCT165_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_dffd_nandd_inverterd_bufferd_nandd_inverterd_dffd_nandd_inverterd_bufferd_nandd_inverterd_dffd_nandd_inverterd_bufferd_nandd_inverterd_dffd_nandd_inverterd_bufferd_nandd_inverterd_dffd_nandd_inverterd_bufferd_nandd_inverterd_dffd_nandd_inverterd_bufferd_nandd_inverterd_dffd_nandd_inverterd_bufferd_nandd_inverterd_dffd_nandd_inverterd_bufferd_nandd_inverterd_bufferd_bufferd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/74HCT165/analysis b/library/SubcircuitLibrary/74HCT165/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/74HCT165/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54112/3_and-cache.lib b/library/SubcircuitLibrary/SN54112/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54112/3_and.cir b/library/SubcircuitLibrary/SN54112/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN54112/3_and.cir.out b/library/SubcircuitLibrary/SN54112/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54112/3_and.pro b/library/SubcircuitLibrary/SN54112/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN54112/3_and.sch b/library/SubcircuitLibrary/SN54112/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54112/3_and.sub b/library/SubcircuitLibrary/SN54112/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54112/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54112/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54112/4_OR-cache.lib b/library/SubcircuitLibrary/SN54112/4_OR-cache.lib new file mode 100644 index 000000000..155f5e601 --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54112/4_OR.cir b/library/SubcircuitLibrary/SN54112/4_OR.cir new file mode 100644 index 000000000..b338b7b5f --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN54112/4_OR.cir.out b/library/SubcircuitLibrary/SN54112/4_OR.cir.out new file mode 100644 index 000000000..adb6b01be --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54112/4_OR.pro b/library/SubcircuitLibrary/SN54112/4_OR.pro new file mode 100644 index 000000000..881563ebd --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN54112/4_OR.sch b/library/SubcircuitLibrary/SN54112/4_OR.sch new file mode 100644 index 000000000..118968656 --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54112/4_OR.sub b/library/SubcircuitLibrary/SN54112/4_OR.sub new file mode 100644 index 000000000..d1fd3a241 --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54112/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/SN54112/4_OR_Previous_Values.xml new file mode 100644 index 000000000..0683d9eb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_ord_ortruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54112/SN54112-cache.lib b/library/SubcircuitLibrary/SN54112/SN54112-cache.lib new file mode 100644 index 000000000..cba523827 --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/SN54112-cache.lib @@ -0,0 +1,97 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54112/SN54112.cir b/library/SubcircuitLibrary/SN54112/SN54112.cir new file mode 100644 index 000000000..3b1b065a2 --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/SN54112.cir @@ -0,0 +1,62 @@ +* C:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\SN54112\SN54112.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/17/26 16:05:56 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U23 Net-_U2-Pad2_ Net-_U23-Pad2_ d_inverter +U24 Net-_U24-Pad1_ Net-_U24-Pad2_ d_inverter +U25 Net-_U25-Pad1_ Net-_U25-Pad2_ d_inverter +U2 Net-_U1-Pad1_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad2_ Net-_U24-Pad1_ d_inverter +U4 Net-_U1-Pad3_ Net-_U25-Pad1_ d_inverter +U43 Net-_U11-Pad2_ Net-_U43-Pad2_ d_inverter +U26 Net-_U26-Pad1_ Net-_U26-Pad2_ d_inverter +U27 Net-_U27-Pad1_ Net-_U27-Pad2_ d_inverter +U28 Net-_U28-Pad1_ Net-_U28-Pad2_ d_inverter +U5 Net-_U1-Pad4_ Net-_U26-Pad1_ d_inverter +U6 Net-_U1-Pad5_ Net-_U27-Pad1_ d_inverter +U7 Net-_U1-Pad6_ Net-_U28-Pad1_ d_inverter +U29 Net-_U29-Pad1_ Net-_U29-Pad2_ d_inverter +U30 Net-_U30-Pad1_ Net-_U30-Pad2_ d_inverter +U31 Net-_U10-Pad2_ Net-_U31-Pad2_ d_inverter +U8 Net-_U1-Pad7_ Net-_U29-Pad1_ d_inverter +U9 Net-_U1-Pad8_ Net-_U30-Pad1_ d_inverter +U10 Net-_U1-Pad9_ Net-_U10-Pad2_ d_inverter +U44 Net-_U12-Pad2_ Net-_U44-Pad2_ d_inverter +U45 Net-_U13-Pad2_ Net-_U45-Pad2_ d_inverter +X1 Net-_U24-Pad1_ Net-_U25-Pad1_ Net-_U23-Pad2_ Net-_X1-Pad4_ 3_and +X2 Net-_U2-Pad2_ Net-_U25-Pad1_ Net-_U24-Pad2_ Net-_X13-Pad2_ 3_and +X3 Net-_U24-Pad1_ Net-_U2-Pad2_ Net-_U25-Pad2_ Net-_X13-Pad3_ 3_and +X4 Net-_U25-Pad2_ Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_X13-Pad4_ 3_and +X5 Net-_U27-Pad1_ Net-_U28-Pad1_ Net-_U26-Pad2_ Net-_X14-Pad1_ 3_and +X6 Net-_U26-Pad1_ Net-_U28-Pad1_ Net-_U27-Pad2_ Net-_X14-Pad2_ 3_and +X7 Net-_U27-Pad1_ Net-_U26-Pad1_ Net-_U28-Pad2_ Net-_X14-Pad3_ 3_and +X8 Net-_U28-Pad2_ Net-_U27-Pad2_ Net-_U26-Pad2_ Net-_X14-Pad4_ 3_and +X9 Net-_U30-Pad1_ Net-_U10-Pad2_ Net-_U29-Pad2_ Net-_X15-Pad1_ 3_and +X10 Net-_U29-Pad1_ Net-_U10-Pad2_ Net-_U30-Pad2_ Net-_X10-Pad4_ 3_and +X11 Net-_U30-Pad1_ Net-_U29-Pad1_ Net-_U31-Pad2_ Net-_X11-Pad4_ 3_and +X12 Net-_U31-Pad2_ Net-_U30-Pad2_ Net-_U29-Pad2_ Net-_X12-Pad4_ 3_and +X16 Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U43-Pad2_ Net-_X16-Pad4_ 3_and +X17 Net-_U11-Pad2_ Net-_U13-Pad2_ Net-_U44-Pad2_ Net-_X17-Pad4_ 3_and +X18 Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U45-Pad2_ Net-_X18-Pad4_ 3_and +X19 Net-_U43-Pad2_ Net-_U44-Pad2_ Net-_U45-Pad2_ Net-_X19-Pad4_ 3_and +X20 Net-_U44-Pad2_ Net-_U45-Pad2_ Net-_U11-Pad2_ Net-_X20-Pad4_ 3_and +X21 Net-_U12-Pad2_ Net-_U43-Pad2_ Net-_U45-Pad2_ Net-_X21-Pad4_ 3_and +X22 Net-_U44-Pad2_ Net-_U43-Pad2_ Net-_U13-Pad2_ Net-_X22-Pad4_ 3_and +X23 Net-_U12-Pad2_ Net-_U11-Pad2_ Net-_U13-Pad2_ Net-_X23-Pad4_ 3_and +X13 Net-_X1-Pad4_ Net-_X13-Pad2_ Net-_X13-Pad3_ Net-_X13-Pad4_ Net-_U11-Pad1_ 4_OR +X14 Net-_X14-Pad1_ Net-_X14-Pad2_ Net-_X14-Pad3_ Net-_X14-Pad4_ Net-_U12-Pad1_ 4_OR +X15 Net-_X15-Pad1_ Net-_X10-Pad4_ Net-_X11-Pad4_ Net-_X12-Pad4_ Net-_U13-Pad1_ 4_OR +X25 Net-_X20-Pad4_ Net-_X21-Pad4_ Net-_X22-Pad4_ Net-_X23-Pad4_ Net-_U15-Pad1_ 4_OR +U15 Net-_U15-Pad1_ Net-_U1-Pad11_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +X24 Net-_X16-Pad4_ Net-_X17-Pad4_ Net-_X18-Pad4_ Net-_X19-Pad4_ Net-_U14-Pad1_ 4_OR +U14 Net-_U14-Pad1_ Net-_U1-Pad10_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN54112/SN54112.cir.out b/library/SubcircuitLibrary/SN54112/SN54112.cir.out new file mode 100644 index 000000000..415133133 --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/SN54112.cir.out @@ -0,0 +1,143 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn54112\sn54112.cir + +.include 3_and.sub +.include 4_OR.sub +* u23 net-_u2-pad2_ net-_u23-pad2_ d_inverter +* u24 net-_u24-pad1_ net-_u24-pad2_ d_inverter +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u24-pad1_ d_inverter +* u4 net-_u1-pad3_ net-_u25-pad1_ d_inverter +* u43 net-_u11-pad2_ net-_u43-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u28 net-_u28-pad1_ net-_u28-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u26-pad1_ d_inverter +* u6 net-_u1-pad5_ net-_u27-pad1_ d_inverter +* u7 net-_u1-pad6_ net-_u28-pad1_ d_inverter +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +* u30 net-_u30-pad1_ net-_u30-pad2_ d_inverter +* u31 net-_u10-pad2_ net-_u31-pad2_ d_inverter +* u8 net-_u1-pad7_ net-_u29-pad1_ d_inverter +* u9 net-_u1-pad8_ net-_u30-pad1_ d_inverter +* u10 net-_u1-pad9_ net-_u10-pad2_ d_inverter +* u44 net-_u12-pad2_ net-_u44-pad2_ d_inverter +* u45 net-_u13-pad2_ net-_u45-pad2_ d_inverter +x1 net-_u24-pad1_ net-_u25-pad1_ net-_u23-pad2_ net-_x1-pad4_ 3_and +x2 net-_u2-pad2_ net-_u25-pad1_ net-_u24-pad2_ net-_x13-pad2_ 3_and +x3 net-_u24-pad1_ net-_u2-pad2_ net-_u25-pad2_ net-_x13-pad3_ 3_and +x4 net-_u25-pad2_ net-_u24-pad2_ net-_u23-pad2_ net-_x13-pad4_ 3_and +x5 net-_u27-pad1_ net-_u28-pad1_ net-_u26-pad2_ net-_x14-pad1_ 3_and +x6 net-_u26-pad1_ net-_u28-pad1_ net-_u27-pad2_ net-_x14-pad2_ 3_and +x7 net-_u27-pad1_ net-_u26-pad1_ net-_u28-pad2_ net-_x14-pad3_ 3_and +x8 net-_u28-pad2_ net-_u27-pad2_ net-_u26-pad2_ net-_x14-pad4_ 3_and +x9 net-_u30-pad1_ net-_u10-pad2_ net-_u29-pad2_ net-_x15-pad1_ 3_and +x10 net-_u29-pad1_ net-_u10-pad2_ net-_u30-pad2_ net-_x10-pad4_ 3_and +x11 net-_u30-pad1_ net-_u29-pad1_ net-_u31-pad2_ net-_x11-pad4_ 3_and +x12 net-_u31-pad2_ net-_u30-pad2_ net-_u29-pad2_ net-_x12-pad4_ 3_and +x16 net-_u12-pad2_ net-_u13-pad2_ net-_u43-pad2_ net-_x16-pad4_ 3_and +x17 net-_u11-pad2_ net-_u13-pad2_ net-_u44-pad2_ net-_x17-pad4_ 3_and +x18 net-_u11-pad2_ net-_u12-pad2_ net-_u45-pad2_ net-_x18-pad4_ 3_and +x19 net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_x19-pad4_ 3_and +x20 net-_u44-pad2_ net-_u45-pad2_ net-_u11-pad2_ net-_x20-pad4_ 3_and +x21 net-_u12-pad2_ net-_u43-pad2_ net-_u45-pad2_ net-_x21-pad4_ 3_and +x22 net-_u44-pad2_ net-_u43-pad2_ net-_u13-pad2_ net-_x22-pad4_ 3_and +x23 net-_u12-pad2_ net-_u11-pad2_ net-_u13-pad2_ net-_x23-pad4_ 3_and +x13 net-_x1-pad4_ net-_x13-pad2_ net-_x13-pad3_ net-_x13-pad4_ net-_u11-pad1_ 4_OR +x14 net-_x14-pad1_ net-_x14-pad2_ net-_x14-pad3_ net-_x14-pad4_ net-_u12-pad1_ 4_OR +x15 net-_x15-pad1_ net-_x10-pad4_ net-_x11-pad4_ net-_x12-pad4_ net-_u13-pad1_ 4_OR +x25 net-_x20-pad4_ net-_x21-pad4_ net-_x22-pad4_ net-_x23-pad4_ net-_u15-pad1_ 4_OR +* u15 net-_u15-pad1_ net-_u1-pad11_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +x24 net-_x16-pad4_ net-_x17-pad4_ net-_x18-pad4_ net-_x19-pad4_ net-_u14-pad1_ 4_OR +* u14 net-_u14-pad1_ net-_u1-pad10_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ port +a1 net-_u2-pad2_ net-_u23-pad2_ u23 +a2 net-_u24-pad1_ net-_u24-pad2_ u24 +a3 net-_u25-pad1_ net-_u25-pad2_ u25 +a4 net-_u1-pad1_ net-_u2-pad2_ u2 +a5 net-_u1-pad2_ net-_u24-pad1_ u3 +a6 net-_u1-pad3_ net-_u25-pad1_ u4 +a7 net-_u11-pad2_ net-_u43-pad2_ u43 +a8 net-_u26-pad1_ net-_u26-pad2_ u26 +a9 net-_u27-pad1_ net-_u27-pad2_ u27 +a10 net-_u28-pad1_ net-_u28-pad2_ u28 +a11 net-_u1-pad4_ net-_u26-pad1_ u5 +a12 net-_u1-pad5_ net-_u27-pad1_ u6 +a13 net-_u1-pad6_ net-_u28-pad1_ u7 +a14 net-_u29-pad1_ net-_u29-pad2_ u29 +a15 net-_u30-pad1_ net-_u30-pad2_ u30 +a16 net-_u10-pad2_ net-_u31-pad2_ u31 +a17 net-_u1-pad7_ net-_u29-pad1_ u8 +a18 net-_u1-pad8_ net-_u30-pad1_ u9 +a19 net-_u1-pad9_ net-_u10-pad2_ u10 +a20 net-_u12-pad2_ net-_u44-pad2_ u44 +a21 net-_u13-pad2_ net-_u45-pad2_ u45 +a22 net-_u15-pad1_ net-_u1-pad11_ u15 +a23 net-_u13-pad1_ net-_u13-pad2_ u13 +a24 net-_u12-pad1_ net-_u12-pad2_ u12 +a25 net-_u11-pad1_ net-_u11-pad2_ u11 +a26 net-_u14-pad1_ net-_u1-pad10_ u14 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 10e-09 100e-09 0e-09 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54112/SN54112.pro b/library/SubcircuitLibrary/SN54112/SN54112.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/SN54112.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN54112/SN54112.sch b/library/SubcircuitLibrary/SN54112/SN54112.sch new file mode 100644 index 000000000..140481e89 --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/SN54112.sch @@ -0,0 +1,1229 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN54112-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U23 +U 1 1 6992CFD3 +P 9350 3250 +F 0 "U23" H 9350 3150 60 0000 C CNN +F 1 "d_inverter" H 9350 3400 60 0000 C CNN +F 2 "" H 9400 3200 60 0000 C CNN +F 3 "" H 9400 3200 60 0000 C CNN + 1 9350 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U24 +U 1 1 6992D02E +P 9350 4000 +F 0 "U24" H 9350 3900 60 0000 C CNN +F 1 "d_inverter" H 9350 4150 60 0000 C CNN +F 2 "" H 9400 3950 60 0000 C CNN +F 3 "" H 9400 3950 60 0000 C CNN + 1 9350 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U25 +U 1 1 6992D07C +P 9350 4950 +F 0 "U25" H 9350 4850 60 0000 C CNN +F 1 "d_inverter" H 9350 5100 60 0000 C CNN +F 2 "" H 9400 4900 60 0000 C CNN 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7900 +Wire Wire Line + 13050 7900 13050 8050 +Wire Wire Line + 13650 7600 13650 8050 +Wire Wire Line + 13150 4150 13150 4300 +Wire Wire Line + 13150 4300 13000 4300 +Wire Wire Line + 13000 4300 13000 4550 +Wire Wire Line + 13000 4550 13050 4550 +Wire Wire Line + 13650 4000 13650 4550 +Wire Wire Line + 19300 5100 19300 5250 +Wire Wire Line + 19800 4950 19800 5050 +Wire Wire Line + 19800 5050 19900 5050 +Wire Wire Line + 19900 5050 19900 5250 +Wire Wire Line + 16400 8400 14000 8400 +Connection ~ 14000 8400 +$Comp +L PORT U1 +U 11 1 6993ADA8 +P 20400 9350 +F 0 "U1" H 20450 9450 30 0000 C CNN +F 1 "PORT" H 20400 9350 30 0000 C CNN +F 2 "" H 20400 9350 60 0000 C CNN +F 3 "" H 20400 9350 60 0000 C CNN + 11 20400 9350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 6993AABF +P 20200 4950 +F 0 "U1" H 20250 5050 30 0000 C CNN +F 1 "PORT" H 20200 4950 30 0000 C CNN +F 2 "" H 20200 4950 60 0000 C CNN +F 3 "" H 20200 4950 60 0000 C CNN + 10 20200 4950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 6993AEA9 +P 6800 12500 +F 0 "U1" H 6850 12600 30 0000 C CNN +F 1 "PORT" H 6800 12500 30 0000 C CNN +F 2 "" H 6800 12500 60 0000 C CNN +F 3 "" H 6800 12500 60 0000 C CNN + 9 6800 12500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 6993AD1D +P 6850 11550 +F 0 "U1" H 6900 11650 30 0000 C CNN +F 1 "PORT" H 6850 11550 30 0000 C CNN +F 2 "" H 6850 11550 60 0000 C CNN +F 3 "" H 6850 11550 60 0000 C CNN + 8 6850 11550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 6993A569 +P 6750 10800 +F 0 "U1" H 6800 10900 30 0000 C CNN +F 1 "PORT" H 6750 10800 30 0000 C CNN +F 2 "" H 6750 10800 60 0000 C CNN +F 3 "" H 6750 10800 60 0000 C CNN + 7 6750 10800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6993AC9E +P 6800 8550 +F 0 "U1" H 6850 8650 30 0000 C CNN +F 1 "PORT" H 6800 8550 30 0000 C CNN +F 2 "" H 6800 8550 60 0000 C CNN +F 3 "" H 6800 8550 60 0000 C CNN + 6 6800 8550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6993AB08 +P 6850 7600 +F 0 "U1" H 6900 7700 30 0000 C CNN +F 1 "PORT" H 6850 7600 30 0000 C CNN +F 2 "" H 6850 7600 60 0000 C CNN +F 3 "" H 6850 7600 60 0000 C CNN + 5 6850 7600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6993A973 +P 6750 6850 +F 0 "U1" H 6800 6950 30 0000 C CNN +F 1 "PORT" H 6750 6850 30 0000 C CNN +F 2 "" H 6750 6850 60 0000 C CNN +F 3 "" H 6750 6850 60 0000 C CNN + 4 6750 6850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6993ABCF +P 6800 4950 +F 0 "U1" H 6850 5050 30 0000 C CNN +F 1 "PORT" H 6800 4950 30 0000 C CNN +F 2 "" H 6800 4950 60 0000 C CNN +F 3 "" H 6800 4950 60 0000 C CNN + 3 6800 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6993AA0C +P 6850 4000 +F 0 "U1" H 6900 4100 30 0000 C CNN +F 1 "PORT" H 6850 4000 30 0000 C CNN +F 2 "" H 6850 4000 60 0000 C CNN +F 3 "" H 6850 4000 60 0000 C CNN + 2 6850 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6993ADF6 +P 6750 3250 +F 0 "U1" H 6800 3350 30 0000 C CNN +F 1 "PORT" H 6750 3250 30 0000 C CNN +F 2 "" H 6750 3250 60 0000 C CNN +F 3 "" H 6750 3250 60 0000 C CNN + 1 6750 3250 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54112/SN54112.sub b/library/SubcircuitLibrary/SN54112/SN54112.sub new file mode 100644 index 000000000..41ed1f369 --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/SN54112.sub @@ -0,0 +1,137 @@ +* Subcircuit SN54112 +.subckt SN54112 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn54112\sn54112.cir +.include 3_and.sub +.include 4_OR.sub +* u23 net-_u2-pad2_ net-_u23-pad2_ d_inverter +* u24 net-_u24-pad1_ net-_u24-pad2_ d_inverter +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u24-pad1_ d_inverter +* u4 net-_u1-pad3_ net-_u25-pad1_ d_inverter +* u43 net-_u11-pad2_ net-_u43-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u28 net-_u28-pad1_ net-_u28-pad2_ d_inverter +* u5 net-_u1-pad4_ net-_u26-pad1_ d_inverter +* u6 net-_u1-pad5_ net-_u27-pad1_ d_inverter +* u7 net-_u1-pad6_ net-_u28-pad1_ d_inverter +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +* u30 net-_u30-pad1_ net-_u30-pad2_ d_inverter +* u31 net-_u10-pad2_ net-_u31-pad2_ d_inverter +* u8 net-_u1-pad7_ net-_u29-pad1_ d_inverter +* u9 net-_u1-pad8_ net-_u30-pad1_ d_inverter +* u10 net-_u1-pad9_ net-_u10-pad2_ d_inverter +* u44 net-_u12-pad2_ net-_u44-pad2_ d_inverter +* u45 net-_u13-pad2_ net-_u45-pad2_ d_inverter +x1 net-_u24-pad1_ net-_u25-pad1_ net-_u23-pad2_ net-_x1-pad4_ 3_and +x2 net-_u2-pad2_ net-_u25-pad1_ net-_u24-pad2_ net-_x13-pad2_ 3_and +x3 net-_u24-pad1_ net-_u2-pad2_ net-_u25-pad2_ net-_x13-pad3_ 3_and +x4 net-_u25-pad2_ net-_u24-pad2_ net-_u23-pad2_ net-_x13-pad4_ 3_and +x5 net-_u27-pad1_ net-_u28-pad1_ net-_u26-pad2_ net-_x14-pad1_ 3_and +x6 net-_u26-pad1_ net-_u28-pad1_ net-_u27-pad2_ net-_x14-pad2_ 3_and +x7 net-_u27-pad1_ net-_u26-pad1_ net-_u28-pad2_ net-_x14-pad3_ 3_and +x8 net-_u28-pad2_ net-_u27-pad2_ net-_u26-pad2_ net-_x14-pad4_ 3_and +x9 net-_u30-pad1_ net-_u10-pad2_ net-_u29-pad2_ net-_x15-pad1_ 3_and +x10 net-_u29-pad1_ net-_u10-pad2_ net-_u30-pad2_ net-_x10-pad4_ 3_and +x11 net-_u30-pad1_ net-_u29-pad1_ net-_u31-pad2_ net-_x11-pad4_ 3_and +x12 net-_u31-pad2_ net-_u30-pad2_ net-_u29-pad2_ net-_x12-pad4_ 3_and +x16 net-_u12-pad2_ net-_u13-pad2_ net-_u43-pad2_ net-_x16-pad4_ 3_and +x17 net-_u11-pad2_ net-_u13-pad2_ net-_u44-pad2_ net-_x17-pad4_ 3_and +x18 net-_u11-pad2_ net-_u12-pad2_ net-_u45-pad2_ net-_x18-pad4_ 3_and +x19 net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_x19-pad4_ 3_and +x20 net-_u44-pad2_ net-_u45-pad2_ net-_u11-pad2_ net-_x20-pad4_ 3_and +x21 net-_u12-pad2_ net-_u43-pad2_ net-_u45-pad2_ net-_x21-pad4_ 3_and +x22 net-_u44-pad2_ net-_u43-pad2_ net-_u13-pad2_ net-_x22-pad4_ 3_and +x23 net-_u12-pad2_ net-_u11-pad2_ net-_u13-pad2_ net-_x23-pad4_ 3_and +x13 net-_x1-pad4_ net-_x13-pad2_ net-_x13-pad3_ net-_x13-pad4_ net-_u11-pad1_ 4_OR +x14 net-_x14-pad1_ net-_x14-pad2_ net-_x14-pad3_ net-_x14-pad4_ net-_u12-pad1_ 4_OR +x15 net-_x15-pad1_ net-_x10-pad4_ net-_x11-pad4_ net-_x12-pad4_ net-_u13-pad1_ 4_OR +x25 net-_x20-pad4_ net-_x21-pad4_ net-_x22-pad4_ net-_x23-pad4_ net-_u15-pad1_ 4_OR +* u15 net-_u15-pad1_ net-_u1-pad11_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +x24 net-_x16-pad4_ net-_x17-pad4_ net-_x18-pad4_ net-_x19-pad4_ net-_u14-pad1_ 4_OR +* u14 net-_u14-pad1_ net-_u1-pad10_ d_inverter +a1 net-_u2-pad2_ net-_u23-pad2_ u23 +a2 net-_u24-pad1_ net-_u24-pad2_ u24 +a3 net-_u25-pad1_ net-_u25-pad2_ u25 +a4 net-_u1-pad1_ net-_u2-pad2_ u2 +a5 net-_u1-pad2_ net-_u24-pad1_ u3 +a6 net-_u1-pad3_ net-_u25-pad1_ u4 +a7 net-_u11-pad2_ net-_u43-pad2_ u43 +a8 net-_u26-pad1_ net-_u26-pad2_ u26 +a9 net-_u27-pad1_ net-_u27-pad2_ u27 +a10 net-_u28-pad1_ net-_u28-pad2_ u28 +a11 net-_u1-pad4_ net-_u26-pad1_ u5 +a12 net-_u1-pad5_ net-_u27-pad1_ u6 +a13 net-_u1-pad6_ net-_u28-pad1_ u7 +a14 net-_u29-pad1_ net-_u29-pad2_ u29 +a15 net-_u30-pad1_ net-_u30-pad2_ u30 +a16 net-_u10-pad2_ net-_u31-pad2_ u31 +a17 net-_u1-pad7_ net-_u29-pad1_ u8 +a18 net-_u1-pad8_ net-_u30-pad1_ u9 +a19 net-_u1-pad9_ net-_u10-pad2_ u10 +a20 net-_u12-pad2_ net-_u44-pad2_ u44 +a21 net-_u13-pad2_ net-_u45-pad2_ u45 +a22 net-_u15-pad1_ net-_u1-pad11_ u15 +a23 net-_u13-pad1_ net-_u13-pad2_ u13 +a24 net-_u12-pad1_ net-_u12-pad2_ u12 +a25 net-_u11-pad1_ net-_u11-pad2_ u11 +a26 net-_u14-pad1_ net-_u1-pad10_ u14 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN54112 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54112/SN54112_Previous_Values.xml b/library/SubcircuitLibrary/SN54112/SN54112_Previous_Values.xml new file mode 100644 index 000000000..b07c85088 --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/SN54112_Previous_Values.xml @@ -0,0 +1 @@ +dc5dc0dc5dc0dc5dc0dc5dc0dc5and3_gateand3_gateand3_gateand3_gated_inverterd_inverterd_inverterd_inverterd_inverterd_inverternor_fourand3_gateand3_gateand3_gateand3_gatenor_fourd_inverterand3_gateand3_gateand3_gateand3_gated_inverterd_inverterd_inverterd_inverterd_inverterd_inverternor_fourand3_gateand3_gateand3_gateand3_gated_inverterd_inverterd_inverterd_inverterd_inverterd_inverternor_fourand3_gateand3_gateand3_gateand3_gatenor_fourd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverteradc_bridgeadc_bridgedac_bridgeC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_ORtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes010100nsnsns \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54112/analysis b/library/SubcircuitLibrary/SN54112/analysis new file mode 100644 index 000000000..6e2c10bbf --- /dev/null +++ b/library/SubcircuitLibrary/SN54112/analysis @@ -0,0 +1 @@ +.tran 10e-09 100e-09 0e-09 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54190/3_and-cache.lib b/library/SubcircuitLibrary/SN54190/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54190/3_and.cir b/library/SubcircuitLibrary/SN54190/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN54190/3_and.cir.out b/library/SubcircuitLibrary/SN54190/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54190/3_and.pro b/library/SubcircuitLibrary/SN54190/3_and.pro new file mode 100644 index 000000000..00597a5ad --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN54190/3_and.sch b/library/SubcircuitLibrary/SN54190/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54190/3_and.sub b/library/SubcircuitLibrary/SN54190/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54190/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54190/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54190/4_and-cache.lib b/library/SubcircuitLibrary/SN54190/4_and-cache.lib new file mode 100644 index 000000000..60f1a83d4 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54190/4_and-rescue.lib b/library/SubcircuitLibrary/SN54190/4_and-rescue.lib new file mode 100644 index 000000000..e38330518 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54190/4_and.cir b/library/SubcircuitLibrary/SN54190/4_and.cir new file mode 100644 index 000000000..fdf2e1074 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN54190/4_and.cir.out b/library/SubcircuitLibrary/SN54190/4_and.cir.out new file mode 100644 index 000000000..f40e5bc62 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54190/4_and.pro b/library/SubcircuitLibrary/SN54190/4_and.pro new file mode 100644 index 000000000..b13a0a825 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/SN54190/4_and.sch b/library/SubcircuitLibrary/SN54190/4_and.sch new file mode 100644 index 000000000..f5e8febdc --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54190/4_and.sub b/library/SubcircuitLibrary/SN54190/4_and.sub new file mode 100644 index 000000000..8663f37e6 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54190/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54190/4_and_Previous_Values.xml new file mode 100644 index 000000000..f2ba0130e --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/4_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54190/SN54190-cache.lib b/library/SubcircuitLibrary/SN54190/SN54190-cache.lib new file mode 100644 index 000000000..4c5d1a3fb --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/SN54190-cache.lib @@ -0,0 +1,169 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_jkff +# +DEF d_jkff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_jkff" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X J 1 -800 400 200 R 50 50 1 1 I +X K 2 -800 -450 200 R 50 50 1 1 I +X Clk 3 -800 0 200 R 50 50 1 1 I C +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54190/SN54190.cir b/library/SubcircuitLibrary/SN54190/SN54190.cir new file mode 100644 index 000000000..ec473efd1 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/SN54190.cir @@ -0,0 +1,63 @@ +* C:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\SN54190\SN54190.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/17/26 20:44:06 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U4-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad7_ Net-_U17-Pad1_ 3_and +X2 Net-_U3-Pad1_ Net-_U32-Pad7_ Net-_U35-Pad7_ Net-_X2-Pad4_ 3_and +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U1-Pad12_ d_or +X3 Net-_X2-Pad4_ Net-_U38-Pad7_ Net-_U15-Pad2_ Net-_U17-Pad2_ 3_and +U10 Net-_U1-Pad15_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nand +U32 Net-_U22-Pad2_ Net-_U22-Pad2_ Net-_U26-Pad2_ Net-_U31-Pad2_ Net-_U32-Pad5_ Net-_U1-Pad3_ Net-_U32-Pad7_ d_jkff +U33 Net-_U16-Pad3_ Net-_U32-Pad5_ d_inverter +U31 Net-_U10-Pad3_ Net-_U31-Pad2_ d_inverter +U9 Net-_U1-Pad4_ Net-_U22-Pad2_ d_inverter +U16 Net-_U10-Pad3_ Net-_U10-Pad2_ Net-_U16-Pad3_ d_nand +U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_nand +U43 Net-_U30-Pad3_ Net-_U1-Pad12_ Net-_U1-Pad13_ d_nand +U30 Net-_U22-Pad3_ Net-_U22-Pad3_ Net-_U30-Pad3_ d_nand +U26 Net-_U22-Pad1_ Net-_U26-Pad2_ d_inverter +U5 Net-_U1-Pad14_ Net-_U22-Pad1_ d_inverter +U6 Net-_U1-Pad5_ Net-_U4-Pad2_ d_inverter +U7 Net-_U4-Pad2_ Net-_U3-Pad1_ d_inverter +U3 Net-_U3-Pad1_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_nor +U4 Net-_U1-Pad4_ Net-_U4-Pad2_ Net-_U4-Pad3_ d_nor +U38 Net-_U19-Pad3_ Net-_U19-Pad3_ Net-_U28-Pad2_ Net-_U37-Pad2_ Net-_U38-Pad5_ Net-_U1-Pad6_ Net-_U38-Pad7_ d_jkff +U39 Net-_U24-Pad3_ Net-_U38-Pad5_ d_inverter +U37 Net-_U13-Pad3_ Net-_U37-Pad2_ d_inverter +U28 Net-_U22-Pad1_ Net-_U28-Pad2_ d_inverter +U24 Net-_U13-Pad3_ Net-_U10-Pad2_ Net-_U24-Pad3_ d_nand +U19 Net-_U19-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_or +U35 Net-_U18-Pad3_ Net-_U18-Pad3_ Net-_U27-Pad2_ Net-_U34-Pad2_ Net-_U35-Pad5_ Net-_U1-Pad2_ Net-_U35-Pad7_ d_jkff +U36 Net-_U23-Pad3_ Net-_U35-Pad5_ d_inverter +U34 Net-_U12-Pad3_ Net-_U34-Pad2_ d_inverter +U27 Net-_U22-Pad1_ Net-_U27-Pad2_ d_inverter +U23 Net-_U12-Pad3_ Net-_U10-Pad2_ Net-_U23-Pad3_ d_nand +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_or +U41 Net-_U20-Pad3_ Net-_U20-Pad3_ Net-_U29-Pad2_ Net-_U40-Pad2_ Net-_U41-Pad5_ Net-_U1-Pad7_ Net-_U15-Pad2_ d_jkff +U42 Net-_U25-Pad3_ Net-_U41-Pad5_ d_inverter +U40 Net-_U14-Pad3_ Net-_U40-Pad2_ d_inverter +U29 Net-_U22-Pad1_ Net-_U29-Pad2_ d_inverter +U25 Net-_U14-Pad3_ Net-_U10-Pad2_ Net-_U25-Pad3_ d_nand +U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U20-Pad1_ d_or +U12 Net-_U1-Pad1_ Net-_U10-Pad2_ Net-_U12-Pad3_ d_nand +X4 Net-_U4-Pad3_ Net-_U32-Pad7_ Net-_U15-Pad3_ Net-_U18-Pad1_ 3_and +X5 Net-_U1-Pad3_ Net-_U15-Pad2_ Net-_U3-Pad3_ Net-_U18-Pad2_ 3_and +U8 Net-_U35-Pad7_ Net-_U38-Pad7_ Net-_U11-Pad1_ d_nand +U15 Net-_U11-Pad3_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nand +U11 Net-_U11-Pad1_ Net-_U11-Pad1_ Net-_U11-Pad3_ d_nand +U13 Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U13-Pad3_ d_nand +X7 Net-_U15-Pad3_ Net-_U4-Pad3_ Net-_U32-Pad7_ Net-_U35-Pad7_ Net-_U19-Pad1_ 4_and +U14 Net-_U1-Pad9_ Net-_U10-Pad2_ Net-_U14-Pad3_ d_nand +X9 Net-_U4-Pad3_ Net-_U32-Pad7_ Net-_U35-Pad7_ Net-_U38-Pad7_ Net-_U21-Pad1_ 4_and +X6 Net-_U1-Pad3_ Net-_U1-Pad7_ Net-_U3-Pad3_ Net-_U21-Pad2_ 3_and +X10 Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad6_ Net-_U3-Pad3_ Net-_U20-Pad2_ 4_and +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_or +U2 Net-_U1-Pad11_ Net-_U10-Pad2_ d_inverter +X8 Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U3-Pad3_ Net-_U19-Pad2_ 3_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN54190/SN54190.cir.out b/library/SubcircuitLibrary/SN54190/SN54190.cir.out new file mode 100644 index 000000000..b67f7dcb0 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/SN54190.cir.out @@ -0,0 +1,192 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn54190\sn54190.cir + +.include 3_and.sub +.include 4_and.sub +x1 net-_u4-pad2_ net-_u1-pad3_ net-_u1-pad7_ net-_u17-pad1_ 3_and +x2 net-_u3-pad1_ net-_u32-pad7_ net-_u35-pad7_ net-_x2-pad4_ 3_and +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u1-pad12_ d_or +x3 net-_x2-pad4_ net-_u38-pad7_ net-_u15-pad2_ net-_u17-pad2_ 3_and +* u10 net-_u1-pad15_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u32 net-_u22-pad2_ net-_u22-pad2_ net-_u26-pad2_ net-_u31-pad2_ net-_u32-pad5_ net-_u1-pad3_ net-_u32-pad7_ d_jkff +* u33 net-_u16-pad3_ net-_u32-pad5_ d_inverter +* u31 net-_u10-pad3_ net-_u31-pad2_ d_inverter +* u9 net-_u1-pad4_ net-_u22-pad2_ d_inverter +* u16 net-_u10-pad3_ net-_u10-pad2_ net-_u16-pad3_ d_nand +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_nand +* u43 net-_u30-pad3_ net-_u1-pad12_ net-_u1-pad13_ d_nand +* u30 net-_u22-pad3_ net-_u22-pad3_ net-_u30-pad3_ d_nand +* u26 net-_u22-pad1_ net-_u26-pad2_ d_inverter +* u5 net-_u1-pad14_ net-_u22-pad1_ d_inverter +* u6 net-_u1-pad5_ net-_u4-pad2_ d_inverter +* u7 net-_u4-pad2_ net-_u3-pad1_ d_inverter +* u3 net-_u3-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_nor +* u4 net-_u1-pad4_ net-_u4-pad2_ net-_u4-pad3_ d_nor +* u38 net-_u19-pad3_ net-_u19-pad3_ net-_u28-pad2_ net-_u37-pad2_ net-_u38-pad5_ net-_u1-pad6_ net-_u38-pad7_ d_jkff +* u39 net-_u24-pad3_ net-_u38-pad5_ d_inverter +* u37 net-_u13-pad3_ net-_u37-pad2_ d_inverter +* u28 net-_u22-pad1_ net-_u28-pad2_ d_inverter +* u24 net-_u13-pad3_ net-_u10-pad2_ net-_u24-pad3_ d_nand +* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_or +* u35 net-_u18-pad3_ net-_u18-pad3_ net-_u27-pad2_ net-_u34-pad2_ net-_u35-pad5_ net-_u1-pad2_ net-_u35-pad7_ d_jkff +* u36 net-_u23-pad3_ net-_u35-pad5_ d_inverter +* u34 net-_u12-pad3_ net-_u34-pad2_ d_inverter +* u27 net-_u22-pad1_ net-_u27-pad2_ d_inverter +* u23 net-_u12-pad3_ net-_u10-pad2_ net-_u23-pad3_ d_nand +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_or +* u41 net-_u20-pad3_ net-_u20-pad3_ net-_u29-pad2_ net-_u40-pad2_ net-_u41-pad5_ net-_u1-pad7_ net-_u15-pad2_ d_jkff +* u42 net-_u25-pad3_ net-_u41-pad5_ d_inverter +* u40 net-_u14-pad3_ net-_u40-pad2_ d_inverter +* u29 net-_u22-pad1_ net-_u29-pad2_ d_inverter +* u25 net-_u14-pad3_ net-_u10-pad2_ net-_u25-pad3_ d_nand +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u20-pad1_ d_or +* u12 net-_u1-pad1_ net-_u10-pad2_ net-_u12-pad3_ d_nand +x4 net-_u4-pad3_ net-_u32-pad7_ net-_u15-pad3_ net-_u18-pad1_ 3_and +x5 net-_u1-pad3_ net-_u15-pad2_ net-_u3-pad3_ net-_u18-pad2_ 3_and +* u8 net-_u35-pad7_ net-_u38-pad7_ net-_u11-pad1_ d_nand +* u15 net-_u11-pad3_ net-_u15-pad2_ net-_u15-pad3_ d_nand +* u11 net-_u11-pad1_ net-_u11-pad1_ net-_u11-pad3_ d_nand +* u13 net-_u1-pad10_ net-_u10-pad2_ net-_u13-pad3_ d_nand +x7 net-_u15-pad3_ net-_u4-pad3_ net-_u32-pad7_ net-_u35-pad7_ net-_u19-pad1_ 4_and +* u14 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ d_nand +x9 net-_u4-pad3_ net-_u32-pad7_ net-_u35-pad7_ net-_u38-pad7_ net-_u21-pad1_ 4_and +x6 net-_u1-pad3_ net-_u1-pad7_ net-_u3-pad3_ net-_u21-pad2_ 3_and +x10 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u3-pad3_ net-_u20-pad2_ 4_and +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u20-pad3_ d_or +* u2 net-_u1-pad11_ net-_u10-pad2_ d_inverter +x8 net-_u1-pad3_ net-_u1-pad2_ net-_u3-pad3_ net-_u19-pad2_ 3_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +a1 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u1-pad12_ u17 +a2 [net-_u1-pad15_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a3 net-_u22-pad2_ net-_u22-pad2_ net-_u26-pad2_ net-_u31-pad2_ net-_u32-pad5_ net-_u1-pad3_ net-_u32-pad7_ u32 +a4 net-_u16-pad3_ net-_u32-pad5_ u33 +a5 net-_u10-pad3_ net-_u31-pad2_ u31 +a6 net-_u1-pad4_ net-_u22-pad2_ u9 +a7 [net-_u10-pad3_ net-_u10-pad2_ ] net-_u16-pad3_ u16 +a8 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a9 [net-_u30-pad3_ net-_u1-pad12_ ] net-_u1-pad13_ u43 +a10 [net-_u22-pad3_ net-_u22-pad3_ ] net-_u30-pad3_ u30 +a11 net-_u22-pad1_ net-_u26-pad2_ u26 +a12 net-_u1-pad14_ net-_u22-pad1_ u5 +a13 net-_u1-pad5_ net-_u4-pad2_ u6 +a14 net-_u4-pad2_ net-_u3-pad1_ u7 +a15 [net-_u3-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a16 [net-_u1-pad4_ net-_u4-pad2_ ] net-_u4-pad3_ u4 +a17 net-_u19-pad3_ net-_u19-pad3_ net-_u28-pad2_ net-_u37-pad2_ net-_u38-pad5_ net-_u1-pad6_ net-_u38-pad7_ u38 +a18 net-_u24-pad3_ net-_u38-pad5_ u39 +a19 net-_u13-pad3_ net-_u37-pad2_ u37 +a20 net-_u22-pad1_ net-_u28-pad2_ u28 +a21 [net-_u13-pad3_ net-_u10-pad2_ ] net-_u24-pad3_ u24 +a22 [net-_u19-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a23 net-_u18-pad3_ net-_u18-pad3_ net-_u27-pad2_ net-_u34-pad2_ net-_u35-pad5_ net-_u1-pad2_ net-_u35-pad7_ u35 +a24 net-_u23-pad3_ net-_u35-pad5_ u36 +a25 net-_u12-pad3_ net-_u34-pad2_ u34 +a26 net-_u22-pad1_ net-_u27-pad2_ u27 +a27 [net-_u12-pad3_ net-_u10-pad2_ ] net-_u23-pad3_ u23 +a28 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a29 net-_u20-pad3_ net-_u20-pad3_ net-_u29-pad2_ net-_u40-pad2_ net-_u41-pad5_ net-_u1-pad7_ net-_u15-pad2_ u41 +a30 net-_u25-pad3_ net-_u41-pad5_ u42 +a31 net-_u14-pad3_ net-_u40-pad2_ u40 +a32 net-_u22-pad1_ net-_u29-pad2_ u29 +a33 [net-_u14-pad3_ net-_u10-pad2_ ] net-_u25-pad3_ u25 +a34 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u20-pad1_ u21 +a35 [net-_u1-pad1_ net-_u10-pad2_ ] net-_u12-pad3_ u12 +a36 [net-_u35-pad7_ net-_u38-pad7_ ] net-_u11-pad1_ u8 +a37 [net-_u11-pad3_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a38 [net-_u11-pad1_ net-_u11-pad1_ ] net-_u11-pad3_ u11 +a39 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u13-pad3_ u13 +a40 [net-_u1-pad9_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a41 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a42 net-_u1-pad11_ net-_u10-pad2_ u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u32 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u38 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u35 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u41 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54190/SN54190.pro b/library/SubcircuitLibrary/SN54190/SN54190.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/SN54190.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN54190/SN54190.sch b/library/SubcircuitLibrary/SN54190/SN54190.sch new file mode 100644 index 000000000..518f28071 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/SN54190.sch @@ -0,0 +1,1415 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A1 33110 23386 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X1 +U 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+Connection ~ 13700 17450 +Wire Wire Line + 14050 14150 13700 14150 +Connection ~ 13700 14150 +Wire Wire Line + 13950 9900 13250 9900 +Connection ~ 13250 9900 +Wire Wire Line + 13500 4700 11500 4700 +Wire Wire Line + 11500 4700 11500 19550 +Wire Wire Line + 11500 19550 20600 19550 +Wire Wire Line + 20600 19550 20600 16950 +Wire Wire Line + 14000 17550 11500 17550 +Connection ~ 11500 17550 +Wire Wire Line + 14050 16750 13400 16750 +Wire Wire Line + 13400 16750 13400 10750 +Wire Wire Line + 13400 10750 12600 10750 +Wire Wire Line + 12600 10750 12600 10000 +Wire Wire Line + 12600 10000 13150 10000 +Wire Wire Line + 13150 10000 13150 5150 +Wire Wire Line + 13150 5150 13500 5150 +Wire Wire Line + 20150 6450 20550 6450 +Wire Wire Line + 20550 6450 20550 7950 +Wire Wire Line + 20550 7950 13150 7950 +Connection ~ 13150 7950 +Wire Wire Line + 13950 9450 13150 9450 +Connection ~ 13150 9450 +Wire Wire Line + 14000 13400 13400 13400 +Connection ~ 13400 13400 +Wire Wire Line + 13250 16850 14050 16850 +Wire Wire Line + 13250 11250 12300 11250 +Wire Wire Line + 12300 11250 12300 9950 +Wire Wire Line + 12300 9950 13000 9950 +Wire Wire Line + 13000 9950 13000 5250 +Wire Wire Line + 13000 5250 13500 5250 +Wire Wire Line + 12700 10450 12300 10450 +Connection ~ 12300 10450 +Wire Wire Line + 12300 11200 20350 11200 +Connection ~ 12300 11200 +Wire Wire Line + 20350 11200 20350 10150 +Wire Wire Line + 20350 10150 20250 10150 +Wire Wire Line + 13250 11250 13250 16850 +Wire Wire Line + 14000 13500 13250 13500 +Connection ~ 13250 13500 +Wire Wire Line + 13500 5600 12750 5600 +Wire Wire Line + 12750 5600 12750 9800 +Wire Wire Line + 12750 9800 12150 9800 +Wire Wire Line + 12150 9800 12150 11350 +Wire Wire Line + 12150 11350 13100 11350 +Wire Wire Line + 13100 11350 13100 16950 +Wire Wire Line + 13100 16950 14050 16950 +Wire Wire Line + 12700 10550 12150 10550 +Connection ~ 12150 10550 +Wire Wire Line + 13100 15500 20450 15500 +Wire Wire Line + 20450 15500 20450 13900 +Wire Wire Line + 20450 13900 20250 13900 +Connection ~ 13100 15500 +Wire Wire Line + 20350 16950 20900 16950 +Wire Wire Line + 13500 5700 12300 5700 +Wire Wire Line + 12300 5700 12300 9600 +Wire Wire Line + 12300 9600 11900 9600 +Wire Wire Line + 11900 9600 11900 11550 +Wire Wire Line + 11900 11550 12800 11550 +Wire Wire Line + 12800 11550 12800 19750 +Wire Wire Line + 12800 19750 20300 19750 +Wire Wire Line + 20300 19750 20300 17900 +Wire Wire Line + 20300 17900 20400 17900 +Wire Wire Line + 20400 17900 20400 17800 +Wire Wire Line + 20400 17800 20350 17800 +Wire Wire Line + 13950 10000 13300 10000 +Wire Wire Line + 13300 10000 13300 10050 +Wire Wire Line + 13300 10050 11900 10050 +Connection ~ 11900 10050 +Wire Wire Line + 14650 10600 14650 10700 +Wire Wire Line + 14650 10700 11900 10700 +Connection ~ 11900 10700 +Wire Wire Line + 20250 13050 20950 13050 +Wire Wire Line + 20750 13050 20750 15750 +Wire Wire Line + 20750 15750 13500 15750 +Wire Wire Line + 13500 15750 13500 18550 +Wire Wire Line + 13500 18550 14050 18550 +Wire Wire Line + 20250 9300 21500 9300 +Wire Wire Line + 21250 9300 21250 11600 +Wire Wire Line + 21250 11600 12450 11600 +Wire Wire Line + 12450 11600 12450 18450 +Wire Wire Line + 12450 18450 14050 18450 +Wire Wire Line + 14050 14250 12450 14250 +Connection ~ 12450 14250 +Wire Wire Line + 15650 10650 15550 10650 +Wire Wire Line + 15550 10650 15550 13000 +Wire Wire Line + 15550 13000 13900 13000 +Wire Wire Line + 13900 13000 13900 13200 +Wire Wire Line + 13900 13200 14000 13200 +Connection ~ 15650 10550 +Wire Wire Line + 13250 8150 20800 8150 +Wire Wire Line + 20800 8150 20800 5550 +Wire Wire Line + 20150 5550 21000 5550 +Wire Wire Line + 20150 5550 20150 5600 +Connection ~ 13250 8150 +Wire Wire Line + 16850 5350 17850 5350 +Wire Wire Line + 17850 5350 17850 17600 +Wire Wire Line + 17850 17600 18250 17600 +Wire Wire Line + 17850 13700 18150 13700 +Connection ~ 17850 13700 +Wire Wire Line + 18150 9950 17850 9950 +Connection ~ 17850 9950 +Wire Wire Line + 18050 6250 17850 6250 +Connection ~ 17850 6250 +Connection ~ 20800 5550 +Connection ~ 21250 9300 +Connection ~ 20750 13050 +Connection ~ 20600 16950 +$Comp +L PORT U1 +U 1 1 699825C2 +P 8100 8850 +F 0 "U1" H 8150 8950 30 0000 C CNN +F 1 "PORT" H 8100 8850 30 0000 C CNN +F 2 "" H 8100 8850 60 0000 C CNN +F 3 "" H 8100 8850 60 0000 C CNN + 1 8100 8850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 699826EE +P 21750 9300 +F 0 "U1" H 21800 9400 30 0000 C CNN +F 1 "PORT" H 21750 9300 30 0000 C CNN +F 2 "" H 21750 9300 60 0000 C CNN +F 3 "" H 21750 9300 60 0000 C CNN + 2 21750 9300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 6998279D +P 8450 5850 +F 0 "U1" H 8500 5950 30 0000 C CNN +F 1 "PORT" H 8450 5850 30 0000 C CNN +F 2 "" H 8450 5850 60 0000 C CNN +F 3 "" H 8450 5850 60 0000 C CNN + 4 8450 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 69982820 +P 9550 4300 +F 0 "U1" H 9600 4400 30 0000 C CNN +F 1 "PORT" H 9550 4300 30 0000 C CNN +F 2 "" H 9550 4300 60 0000 C CNN +F 3 "" H 9550 4300 60 0000 C CNN + 5 9550 4300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 69982AE1 +P 21200 13050 +F 0 "U1" H 21250 13150 30 0000 C CNN +F 1 "PORT" H 21200 13050 30 0000 C CNN +F 2 "" H 21200 13050 60 0000 C CNN +F 3 "" H 21200 13050 60 0000 C CNN + 6 21200 13050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 69982B68 +P 21250 5550 +F 0 "U1" H 21300 5650 30 0000 C CNN +F 1 "PORT" H 21250 5550 30 0000 C CNN +F 2 "" H 21250 5550 60 0000 C CNN +F 3 "" H 21250 5550 60 0000 C CNN + 3 21250 5550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 69982BF1 +P 21150 16950 +F 0 "U1" H 21200 17050 30 0000 C CNN +F 1 "PORT" H 21150 16950 30 0000 C CNN +F 2 "" H 21150 16950 60 0000 C CNN +F 3 "" H 21150 16950 60 0000 C CNN + 7 21150 16950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 69982C7C +P 2100 5200 +F 0 "U1" H 2150 5300 30 0000 C CNN +F 1 "PORT" H 2100 5200 30 0000 C CNN +F 2 "" H 2100 5200 60 0000 C CNN +F 3 "" H 2100 5200 60 0000 C CNN + 8 2100 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 69982EAD +P 7050 16050 +F 0 "U1" H 7100 16150 30 0000 C CNN +F 1 "PORT" H 7050 16050 30 0000 C CNN +F 2 "" H 7050 16050 60 0000 C CNN +F 3 "" H 7050 16050 60 0000 C CNN + 9 7050 16050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 69982F3C +P 9550 3650 +F 0 "U1" H 9600 3750 30 0000 C CNN +F 1 "PORT" H 9550 3650 30 0000 C CNN +F 2 "" H 9550 3650 60 0000 C CNN +F 3 "" H 9550 3650 60 0000 C CNN + 14 9550 3650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 69983181 +P 7700 12650 +F 0 "U1" H 7750 12750 30 0000 C CNN +F 1 "PORT" H 7700 12650 30 0000 C CNN +F 2 "" H 7700 12650 60 0000 C CNN +F 3 "" H 7700 12650 60 0000 C CNN + 10 7700 12650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 69983214 +P 7400 19450 +F 0 "U1" H 7450 19550 30 0000 C CNN +F 1 "PORT" H 7400 19450 30 0000 C CNN +F 2 "" H 7400 19450 60 0000 C CNN +F 3 "" H 7400 19450 60 0000 C CNN + 11 7400 19450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 699832A9 +P 21050 4350 +F 0 "U1" H 21100 4450 30 0000 C CNN +F 1 "PORT" H 21050 4350 30 0000 C CNN +F 2 "" H 21050 4350 60 0000 C CNN +F 3 "" H 21050 4350 60 0000 C CNN + 12 21050 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 699833C2 +P 8000 6500 +F 0 "U1" H 8050 6600 30 0000 C CNN +F 1 "PORT" H 8000 6500 30 0000 C CNN +F 2 "" H 8000 6500 60 0000 C CNN +F 3 "" H 8000 6500 60 0000 C CNN + 15 8000 6500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 699834F1 +P 21300 4200 +F 0 "U1" H 21350 4300 30 0000 C CNN +F 1 "PORT" H 21300 4200 30 0000 C CNN +F 2 "" H 21300 4200 60 0000 C CNN +F 3 "" H 21300 4200 60 0000 C CNN + 13 21300 4200 + -1 0 0 1 +$EndComp +Wire Wire Line + 7650 19450 7900 19450 +Wire Wire Line + 9800 3650 9900 3650 +Wire Wire Line + 9800 4300 9900 4300 +NoConn ~ 2350 5200 +$Comp +L PORT U1 +U 16 1 69994509 +P 4150 4300 +F 0 "U1" H 4200 4400 30 0000 C CNN +F 1 "PORT" H 4150 4300 30 0000 C CNN +F 2 "" H 4150 4300 60 0000 C CNN +F 3 "" H 4150 4300 60 0000 C CNN + 16 4150 4300 + 1 0 0 -1 +$EndComp +NoConn ~ 4400 4300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54190/SN54190.sub b/library/SubcircuitLibrary/SN54190/SN54190.sub new file mode 100644 index 000000000..8b262d40e --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/SN54190.sub @@ -0,0 +1,186 @@ +* Subcircuit SN54190 +.subckt SN54190 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn54190\sn54190.cir +.include 3_and.sub +.include 4_and.sub +x1 net-_u4-pad2_ net-_u1-pad3_ net-_u1-pad7_ net-_u17-pad1_ 3_and +x2 net-_u3-pad1_ net-_u32-pad7_ net-_u35-pad7_ net-_x2-pad4_ 3_and +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u1-pad12_ d_or +x3 net-_x2-pad4_ net-_u38-pad7_ net-_u15-pad2_ net-_u17-pad2_ 3_and +* u10 net-_u1-pad15_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u32 net-_u22-pad2_ net-_u22-pad2_ net-_u26-pad2_ net-_u31-pad2_ net-_u32-pad5_ net-_u1-pad3_ net-_u32-pad7_ d_jkff +* u33 net-_u16-pad3_ net-_u32-pad5_ d_inverter +* u31 net-_u10-pad3_ net-_u31-pad2_ d_inverter +* u9 net-_u1-pad4_ net-_u22-pad2_ d_inverter +* u16 net-_u10-pad3_ net-_u10-pad2_ net-_u16-pad3_ d_nand +* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_nand +* u43 net-_u30-pad3_ net-_u1-pad12_ net-_u1-pad13_ d_nand +* u30 net-_u22-pad3_ net-_u22-pad3_ net-_u30-pad3_ d_nand +* u26 net-_u22-pad1_ net-_u26-pad2_ d_inverter +* u5 net-_u1-pad14_ net-_u22-pad1_ d_inverter +* u6 net-_u1-pad5_ net-_u4-pad2_ d_inverter +* u7 net-_u4-pad2_ net-_u3-pad1_ d_inverter +* u3 net-_u3-pad1_ net-_u1-pad4_ net-_u3-pad3_ d_nor +* u4 net-_u1-pad4_ net-_u4-pad2_ net-_u4-pad3_ d_nor +* u38 net-_u19-pad3_ net-_u19-pad3_ net-_u28-pad2_ net-_u37-pad2_ net-_u38-pad5_ net-_u1-pad6_ net-_u38-pad7_ d_jkff +* u39 net-_u24-pad3_ net-_u38-pad5_ d_inverter +* u37 net-_u13-pad3_ net-_u37-pad2_ d_inverter +* u28 net-_u22-pad1_ net-_u28-pad2_ d_inverter +* u24 net-_u13-pad3_ net-_u10-pad2_ net-_u24-pad3_ d_nand +* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_or +* u35 net-_u18-pad3_ net-_u18-pad3_ net-_u27-pad2_ net-_u34-pad2_ net-_u35-pad5_ net-_u1-pad2_ net-_u35-pad7_ d_jkff +* u36 net-_u23-pad3_ net-_u35-pad5_ d_inverter +* u34 net-_u12-pad3_ net-_u34-pad2_ d_inverter +* u27 net-_u22-pad1_ net-_u27-pad2_ d_inverter +* u23 net-_u12-pad3_ net-_u10-pad2_ net-_u23-pad3_ d_nand +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_or +* u41 net-_u20-pad3_ net-_u20-pad3_ net-_u29-pad2_ net-_u40-pad2_ net-_u41-pad5_ net-_u1-pad7_ net-_u15-pad2_ d_jkff +* u42 net-_u25-pad3_ net-_u41-pad5_ d_inverter +* u40 net-_u14-pad3_ net-_u40-pad2_ d_inverter +* u29 net-_u22-pad1_ net-_u29-pad2_ d_inverter +* u25 net-_u14-pad3_ net-_u10-pad2_ net-_u25-pad3_ d_nand +* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u20-pad1_ d_or +* u12 net-_u1-pad1_ net-_u10-pad2_ net-_u12-pad3_ d_nand +x4 net-_u4-pad3_ net-_u32-pad7_ net-_u15-pad3_ net-_u18-pad1_ 3_and +x5 net-_u1-pad3_ net-_u15-pad2_ net-_u3-pad3_ net-_u18-pad2_ 3_and +* u8 net-_u35-pad7_ net-_u38-pad7_ net-_u11-pad1_ d_nand +* u15 net-_u11-pad3_ net-_u15-pad2_ net-_u15-pad3_ d_nand +* u11 net-_u11-pad1_ net-_u11-pad1_ net-_u11-pad3_ d_nand +* u13 net-_u1-pad10_ net-_u10-pad2_ net-_u13-pad3_ d_nand +x7 net-_u15-pad3_ net-_u4-pad3_ net-_u32-pad7_ net-_u35-pad7_ net-_u19-pad1_ 4_and +* u14 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ d_nand +x9 net-_u4-pad3_ net-_u32-pad7_ net-_u35-pad7_ net-_u38-pad7_ net-_u21-pad1_ 4_and +x6 net-_u1-pad3_ net-_u1-pad7_ net-_u3-pad3_ net-_u21-pad2_ 3_and +x10 net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u3-pad3_ net-_u20-pad2_ 4_and +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u20-pad3_ d_or +* u2 net-_u1-pad11_ net-_u10-pad2_ d_inverter +x8 net-_u1-pad3_ net-_u1-pad2_ net-_u3-pad3_ net-_u19-pad2_ 3_and +a1 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u1-pad12_ u17 +a2 [net-_u1-pad15_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a3 net-_u22-pad2_ net-_u22-pad2_ net-_u26-pad2_ net-_u31-pad2_ net-_u32-pad5_ net-_u1-pad3_ net-_u32-pad7_ u32 +a4 net-_u16-pad3_ net-_u32-pad5_ u33 +a5 net-_u10-pad3_ net-_u31-pad2_ u31 +a6 net-_u1-pad4_ net-_u22-pad2_ u9 +a7 [net-_u10-pad3_ net-_u10-pad2_ ] net-_u16-pad3_ u16 +a8 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22 +a9 [net-_u30-pad3_ net-_u1-pad12_ ] net-_u1-pad13_ u43 +a10 [net-_u22-pad3_ net-_u22-pad3_ ] net-_u30-pad3_ u30 +a11 net-_u22-pad1_ net-_u26-pad2_ u26 +a12 net-_u1-pad14_ net-_u22-pad1_ u5 +a13 net-_u1-pad5_ net-_u4-pad2_ u6 +a14 net-_u4-pad2_ net-_u3-pad1_ u7 +a15 [net-_u3-pad1_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a16 [net-_u1-pad4_ net-_u4-pad2_ ] net-_u4-pad3_ u4 +a17 net-_u19-pad3_ net-_u19-pad3_ net-_u28-pad2_ net-_u37-pad2_ net-_u38-pad5_ net-_u1-pad6_ net-_u38-pad7_ u38 +a18 net-_u24-pad3_ net-_u38-pad5_ u39 +a19 net-_u13-pad3_ net-_u37-pad2_ u37 +a20 net-_u22-pad1_ net-_u28-pad2_ u28 +a21 [net-_u13-pad3_ net-_u10-pad2_ ] net-_u24-pad3_ u24 +a22 [net-_u19-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19 +a23 net-_u18-pad3_ net-_u18-pad3_ net-_u27-pad2_ net-_u34-pad2_ net-_u35-pad5_ net-_u1-pad2_ net-_u35-pad7_ u35 +a24 net-_u23-pad3_ net-_u35-pad5_ u36 +a25 net-_u12-pad3_ net-_u34-pad2_ u34 +a26 net-_u22-pad1_ net-_u27-pad2_ u27 +a27 [net-_u12-pad3_ net-_u10-pad2_ ] net-_u23-pad3_ u23 +a28 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a29 net-_u20-pad3_ net-_u20-pad3_ net-_u29-pad2_ net-_u40-pad2_ net-_u41-pad5_ net-_u1-pad7_ net-_u15-pad2_ u41 +a30 net-_u25-pad3_ net-_u41-pad5_ u42 +a31 net-_u14-pad3_ net-_u40-pad2_ u40 +a32 net-_u22-pad1_ net-_u29-pad2_ u29 +a33 [net-_u14-pad3_ net-_u10-pad2_ ] net-_u25-pad3_ u25 +a34 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u20-pad1_ u21 +a35 [net-_u1-pad1_ net-_u10-pad2_ ] net-_u12-pad3_ u12 +a36 [net-_u35-pad7_ net-_u38-pad7_ ] net-_u11-pad1_ u8 +a37 [net-_u11-pad3_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a38 [net-_u11-pad1_ net-_u11-pad1_ ] net-_u11-pad3_ u11 +a39 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u13-pad3_ u13 +a40 [net-_u1-pad9_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a41 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a42 net-_u1-pad11_ net-_u10-pad2_ u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u32 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u3 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u4 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u38 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u35 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u41 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u42 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u21 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN54190 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54190/SN54190_Previous_Values.xml b/library/SubcircuitLibrary/SN54190/SN54190_Previous_Values.xml new file mode 100644 index 000000000..ac42ee323 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/SN54190_Previous_Values.xml @@ -0,0 +1 @@ +d_ord_nandd_jkffd_inverterd_inverterd_inverterd_nandd_nandd_nandd_nandd_inverterd_inverterd_inverterd_inverterd_nord_nord_jkffd_inverterd_inverterd_inverterd_nandd_ord_jkffd_inverterd_inverterd_inverterd_nandd_ord_jkffd_inverterd_inverterd_inverterd_nandd_ord_nandd_nandd_nandd_nandd_nandd_nandd_ord_inverterC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\4_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54190/analysis b/library/SubcircuitLibrary/SN54190/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN54190/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55189/NPN.lib b/library/SubcircuitLibrary/SN55189/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/SN55189/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN55189/SN55189-cache.lib b/library/SubcircuitLibrary/SN55189/SN55189-cache.lib new file mode 100644 index 000000000..d900cc5d9 --- /dev/null +++ b/library/SubcircuitLibrary/SN55189/SN55189-cache.lib @@ -0,0 +1,128 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS capacitor_polarised +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN55189/SN55189.cir b/library/SubcircuitLibrary/SN55189/SN55189.cir new file mode 100644 index 000000000..47b81d862 --- /dev/null +++ b/library/SubcircuitLibrary/SN55189/SN55189.cir @@ -0,0 +1,87 @@ +* C:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\SN55189\SN55189.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/20/26 18:15:45 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_D4-Pad2_ Net-_D2-Pad2_ GND eSim_NPN +D4 Net-_D2-Pad2_ Net-_D4-Pad2_ eSim_Diode +Q4 Net-_D6-Pad2_ Net-_D4-Pad2_ GND eSim_NPN +D6 Net-_D4-Pad2_ Net-_D6-Pad2_ eSim_Diode +Q6 Net-_C2-Pad1_ Net-_D6-Pad2_ GND eSim_NPN +D8 Net-_D6-Pad2_ Net-_C2-Pad1_ eSim_Diode +R2 Net-_R2-Pad1_ Net-_D2-Pad2_ 4k +D2 GND Net-_D2-Pad2_ eSim_Diode +R5 Net-_D2-Pad2_ GND 10k +R6 Net-_D2-Pad2_ Net-_D6-Pad2_ 8.4k +R8 VCC Net-_D4-Pad2_ 9k +R10 VCC Net-_D6-Pad2_ 5k +R12 VCC Net-_C2-Pad1_ 1.66k +C2 Net-_C2-Pad1_ GND 15pF +D10 Net-_D10-Pad1_ Net-_C2-Pad1_ eSim_Diode +D12 Net-_D10-Pad1_ Net-_D12-Pad2_ eSim_Diode +D14 Net-_D12-Pad2_ Net-_D14-Pad2_ eSim_Diode +D17 Net-_D14-Pad2_ GND eSim_Diode +R14 VCC Net-_D10-Pad1_ 3.9k +Q1 Net-_D3-Pad2_ Net-_D1-Pad2_ GND eSim_NPN +D3 Net-_D1-Pad2_ Net-_D3-Pad2_ eSim_Diode +Q3 Net-_D5-Pad2_ Net-_D3-Pad2_ GND eSim_NPN +D5 Net-_D3-Pad2_ Net-_D5-Pad2_ eSim_Diode +Q5 Net-_C1-Pad1_ Net-_D5-Pad2_ GND eSim_NPN +D7 Net-_D5-Pad2_ Net-_C1-Pad1_ eSim_Diode +R1 Net-_R1-Pad1_ Net-_D1-Pad2_ 4k +D1 GND Net-_D1-Pad2_ eSim_Diode +R3 Net-_D1-Pad2_ GND 10k +R4 Net-_D1-Pad2_ Net-_D5-Pad2_ 8.4k +R7 VCC Net-_D3-Pad2_ 9k +R9 VCC Net-_D5-Pad2_ 5k +R11 VCC Net-_C1-Pad1_ 1.66k +C1 Net-_C1-Pad1_ GND 15pF +D9 Net-_D11-Pad1_ Net-_C1-Pad1_ eSim_Diode +D11 Net-_D11-Pad1_ Net-_D11-Pad2_ eSim_Diode +D13 Net-_D11-Pad2_ Net-_D13-Pad2_ eSim_Diode +D15 Net-_D13-Pad2_ GND eSim_Diode +R13 VCC Net-_D11-Pad1_ 3.9k +Q8 Net-_D20-Pad2_ Net-_D18-Pad2_ GND eSim_NPN +D20 Net-_D18-Pad2_ Net-_D20-Pad2_ eSim_Diode +Q10 Net-_D22-Pad2_ Net-_D20-Pad2_ GND eSim_NPN +D22 Net-_D20-Pad2_ Net-_D22-Pad2_ eSim_Diode +Q12 Net-_C4-Pad1_ Net-_D22-Pad2_ GND eSim_NPN +D24 Net-_D22-Pad2_ Net-_C4-Pad1_ eSim_Diode +R16 Net-_R16-Pad1_ Net-_D18-Pad2_ 4k +D18 GND Net-_D18-Pad2_ eSim_Diode +R19 Net-_D18-Pad2_ GND 10k +R20 Net-_D18-Pad2_ Net-_D22-Pad2_ 8.4k +R22 VCC Net-_D20-Pad2_ 9k +R24 VCC Net-_D22-Pad2_ 5k +R26 VCC Net-_C4-Pad1_ 1.66k +C4 Net-_C4-Pad1_ GND 15pF +D26 Net-_D26-Pad1_ Net-_C4-Pad1_ eSim_Diode +D28 Net-_D26-Pad1_ Net-_D28-Pad2_ eSim_Diode +D30 Net-_D28-Pad2_ Net-_D30-Pad2_ eSim_Diode +D32 Net-_D30-Pad2_ GND eSim_Diode +R28 VCC Net-_D26-Pad1_ 3.9k +Q7 Net-_D19-Pad2_ Net-_D16-Pad2_ GND eSim_NPN +D19 Net-_D16-Pad2_ Net-_D19-Pad2_ eSim_Diode +Q9 Net-_D21-Pad2_ Net-_D19-Pad2_ GND eSim_NPN +D21 Net-_D19-Pad2_ Net-_D21-Pad2_ eSim_Diode +Q11 Net-_C3-Pad1_ Net-_D21-Pad2_ GND eSim_NPN +D23 Net-_D21-Pad2_ Net-_C3-Pad1_ eSim_Diode +R15 Net-_R15-Pad1_ Net-_D16-Pad2_ 4k +D16 GND Net-_D16-Pad2_ eSim_Diode +R17 Net-_D16-Pad2_ GND 10k +R18 Net-_D16-Pad2_ Net-_D21-Pad2_ 8.4k +R21 VCC Net-_D19-Pad2_ 9k +R23 VCC Net-_D21-Pad2_ 5k +R25 VCC Net-_C3-Pad1_ 1.66k +C3 Net-_C3-Pad1_ GND 15pF +D25 Net-_D25-Pad1_ Net-_C3-Pad1_ eSim_Diode +D27 Net-_D25-Pad1_ Net-_D27-Pad2_ eSim_Diode +D29 Net-_D27-Pad2_ Net-_D29-Pad2_ eSim_Diode +D31 Net-_D29-Pad2_ GND eSim_Diode +R27 VCC Net-_D25-Pad1_ 3.9k +U1 Net-_R2-Pad1_ ? Net-_C2-Pad1_ Net-_R1-Pad1_ ? Net-_C1-Pad1_ GND Net-_C4-Pad1_ ? Net-_R16-Pad1_ Net-_C3-Pad1_ ? Net-_R15-Pad1_ VCC PORT + +.end diff --git a/library/SubcircuitLibrary/SN55189/SN55189.cir.out b/library/SubcircuitLibrary/SN55189/SN55189.cir.out new file mode 100644 index 000000000..762e48679 --- /dev/null +++ b/library/SubcircuitLibrary/SN55189/SN55189.cir.out @@ -0,0 +1,90 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn55189\sn55189.cir + +.include NPN.lib +.include schottky.lib +q2 net-_d4-pad2_ net-_d2-pad2_ gnd Q2N2222 +d4 net-_d2-pad2_ net-_d4-pad2_ 1N5819 +q4 net-_d6-pad2_ net-_d4-pad2_ gnd Q2N2222 +d6 net-_d4-pad2_ net-_d6-pad2_ 1N5819 +q6 net-_c2-pad1_ net-_d6-pad2_ gnd Q2N2222 +d8 net-_d6-pad2_ net-_c2-pad1_ 1N5819 +r2 net-_r2-pad1_ net-_d2-pad2_ 4k +d2 gnd net-_d2-pad2_ 1N5819 +r5 net-_d2-pad2_ gnd 10k +r6 net-_d2-pad2_ net-_d6-pad2_ 8.4k +r8 vcc net-_d4-pad2_ 9k +r10 vcc net-_d6-pad2_ 5k +r12 vcc net-_c2-pad1_ 1.66k +c2 net-_c2-pad1_ gnd 15pf +d10 net-_d10-pad1_ net-_c2-pad1_ 1N5819 +d12 net-_d10-pad1_ net-_d12-pad2_ 1N5819 +d14 net-_d12-pad2_ net-_d14-pad2_ 1N5819 +d17 net-_d14-pad2_ gnd 1N5819 +r14 vcc net-_d10-pad1_ 3.9k +q1 net-_d3-pad2_ net-_d1-pad2_ gnd Q2N2222 +d3 net-_d1-pad2_ net-_d3-pad2_ 1N5819 +q3 net-_d5-pad2_ net-_d3-pad2_ gnd Q2N2222 +d5 net-_d3-pad2_ net-_d5-pad2_ 1N5819 +q5 net-_c1-pad1_ net-_d5-pad2_ gnd Q2N2222 +d7 net-_d5-pad2_ net-_c1-pad1_ 1N5819 +r1 net-_r1-pad1_ net-_d1-pad2_ 4k +d1 gnd net-_d1-pad2_ 1N5819 +r3 net-_d1-pad2_ gnd 10k +r4 net-_d1-pad2_ net-_d5-pad2_ 8.4k +r7 vcc net-_d3-pad2_ 9k +r9 vcc net-_d5-pad2_ 5k +r11 vcc net-_c1-pad1_ 1.66k +c1 net-_c1-pad1_ gnd 15pf +d9 net-_d11-pad1_ net-_c1-pad1_ 1N5819 +d11 net-_d11-pad1_ net-_d11-pad2_ 1N5819 +d13 net-_d11-pad2_ net-_d13-pad2_ 1N5819 +d15 net-_d13-pad2_ gnd 1N5819 +r13 vcc net-_d11-pad1_ 3.9k +q8 net-_d20-pad2_ net-_d18-pad2_ gnd Q2N2222 +d20 net-_d18-pad2_ net-_d20-pad2_ 1N5819 +q10 net-_d22-pad2_ net-_d20-pad2_ gnd Q2N2222 +d22 net-_d20-pad2_ net-_d22-pad2_ 1N5819 +q12 net-_c4-pad1_ net-_d22-pad2_ gnd Q2N2222 +d24 net-_d22-pad2_ net-_c4-pad1_ 1N5819 +r16 net-_r16-pad1_ net-_d18-pad2_ 4k +d18 gnd net-_d18-pad2_ 1N5819 +r19 net-_d18-pad2_ gnd 10k +r20 net-_d18-pad2_ net-_d22-pad2_ 8.4k +r22 vcc net-_d20-pad2_ 9k +r24 vcc net-_d22-pad2_ 5k +r26 vcc net-_c4-pad1_ 1.66k +c4 net-_c4-pad1_ gnd 15pf +d26 net-_d26-pad1_ net-_c4-pad1_ 1N5819 +d28 net-_d26-pad1_ net-_d28-pad2_ 1N5819 +d30 net-_d28-pad2_ net-_d30-pad2_ 1N5819 +d32 net-_d30-pad2_ gnd 1N5819 +r28 vcc net-_d26-pad1_ 3.9k +q7 net-_d19-pad2_ net-_d16-pad2_ gnd Q2N2222 +d19 net-_d16-pad2_ net-_d19-pad2_ 1N5819 +q9 net-_d21-pad2_ net-_d19-pad2_ gnd Q2N2222 +d21 net-_d19-pad2_ net-_d21-pad2_ 1N5819 +q11 net-_c3-pad1_ net-_d21-pad2_ gnd Q2N2222 +d23 net-_d21-pad2_ net-_c3-pad1_ 1N5819 +r15 net-_r15-pad1_ net-_d16-pad2_ 4k +d16 gnd net-_d16-pad2_ 1N5819 +r17 net-_d16-pad2_ gnd 10k +r18 net-_d16-pad2_ net-_d21-pad2_ 8.4k +r21 vcc net-_d19-pad2_ 9k +r23 vcc net-_d21-pad2_ 5k +r25 vcc net-_c3-pad1_ 1.66k +c3 net-_c3-pad1_ gnd 15pf +d25 net-_d25-pad1_ net-_c3-pad1_ 1N5819 +d27 net-_d25-pad1_ net-_d27-pad2_ 1N5819 +d29 net-_d27-pad2_ net-_d29-pad2_ 1N5819 +d31 net-_d29-pad2_ gnd 1N5819 +r27 vcc net-_d25-pad1_ 3.9k +* u1 net-_r2-pad1_ ? net-_c2-pad1_ net-_r1-pad1_ ? net-_c1-pad1_ gnd net-_c4-pad1_ ? net-_r16-pad1_ net-_c3-pad1_ ? net-_r15-pad1_ vcc port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN55189/SN55189.pro b/library/SubcircuitLibrary/SN55189/SN55189.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN55189/SN55189.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN55189/SN55189.sch b/library/SubcircuitLibrary/SN55189/SN55189.sch new file mode 100644 index 000000000..c1c096665 --- /dev/null +++ b/library/SubcircuitLibrary/SN55189/SN55189.sch @@ -0,0 +1,1598 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q2 +U 1 1 6998530F +P 6900 5200 +F 0 "Q2" H 6800 5250 50 0000 R CNN +F 1 "eSim_NPN" H 6850 5350 50 0000 R CNN +F 2 "" H 7100 5300 29 0000 C CNN +F 3 "" H 6900 5200 60 0000 C CNN + 1 6900 5200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 6998536D +P 6350 5050 +F 0 "D4" H 6350 5150 50 0000 C CNN +F 1 "eSim_Diode" H 6350 4950 50 0000 C CNN +F 2 "" H 6350 5050 60 0000 C CNN +F 3 "" H 6350 5050 60 0000 C CNN + 1 6350 5050 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6350 4900 6350 4850 +Wire Wire Line + 6350 4850 7000 4850 +Wire Wire Line + 7000 3450 7000 5000 +Wire Wire Line + 6350 5200 6350 5250 +Wire Wire Line + 5300 5250 6700 5250 +Wire Wire Line + 6700 5250 6700 5200 +Connection ~ 6350 5250 +Connection ~ 7000 4850 +$Comp +L eSim_NPN Q4 +U 1 1 69985459 +P 8200 4400 +F 0 "Q4" H 8100 4450 50 0000 R CNN +F 1 "eSim_NPN" H 8150 4550 50 0000 R CNN +F 2 "" H 8400 4500 29 0000 C CNN +F 3 "" H 8200 4400 60 0000 C CNN + 1 8200 4400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 6998545F +P 7650 4250 +F 0 "D6" H 7650 4350 50 0000 C CNN +F 1 "eSim_Diode" H 7650 4150 50 0000 C CNN +F 2 "" H 7650 4250 60 0000 C CNN +F 3 "" H 7650 4250 60 0000 C CNN + 1 7650 4250 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7650 4100 7650 4050 +Wire Wire Line + 7650 4050 8300 4050 +Wire Wire Line + 8300 3650 8300 4200 +Wire Wire Line + 7650 4400 7650 4450 +Wire Wire Line + 7000 4450 8000 4450 +Wire Wire Line + 8000 4450 8000 4400 +Connection ~ 7650 4450 +Connection ~ 8300 4050 +$Comp +L eSim_NPN Q6 +U 1 1 699854A7 +P 9550 3650 +F 0 "Q6" H 9450 3700 50 0000 R CNN +F 1 "eSim_NPN" H 9500 3800 50 0000 R CNN +F 2 "" H 9750 3750 29 0000 C CNN +F 3 "" H 9550 3650 60 0000 C CNN + 1 9550 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D8 +U 1 1 699854AD +P 9000 3500 +F 0 "D8" H 9000 3600 50 0000 C CNN +F 1 "eSim_Diode" H 9000 3400 50 0000 C CNN +F 2 "" H 9000 3500 60 0000 C CNN +F 3 "" H 9000 3500 60 0000 C CNN + 1 9000 3500 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 9000 3350 9000 3300 +Wire Wire Line + 9000 3300 9650 3300 +Wire Wire Line + 9650 3150 9650 3450 +Wire Wire Line + 9000 3650 9000 3700 +Wire Wire Line + 8750 3700 9350 3700 +Wire Wire Line + 9350 3700 9350 3650 +Connection ~ 9000 3700 +Connection ~ 9650 3300 +$Comp +L resistor R2 +U 1 1 699854F9 +P 5100 5300 +F 0 "R2" H 5150 5430 50 0000 C CNN +F 1 "4k" H 5150 5250 50 0000 C CNN +F 2 "" H 5150 5280 30 0000 C CNN +F 3 "" V 5150 5350 30 0000 C CNN + 1 5100 5300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 699855A7 +P 5450 5600 +F 0 "D2" H 5450 5700 50 0000 C CNN +F 1 "eSim_Diode" H 5450 5500 50 0000 C CNN +F 2 "" H 5450 5600 60 0000 C CNN +F 3 "" H 5450 5600 60 0000 C CNN + 1 5450 5600 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 699855E1 +P 5800 5550 +F 0 "R5" H 5850 5680 50 0000 C CNN +F 1 "10k" H 5850 5500 50 0000 C CNN +F 2 "" H 5850 5530 30 0000 C CNN +F 3 "" V 5850 5600 30 0000 C CNN + 1 5800 5550 + 0 1 1 0 +$EndComp +Wire Wire Line + 5450 5450 5450 5250 +Connection ~ 5450 5250 +Wire Wire Line + 5850 5450 5850 5250 +Connection ~ 5850 5250 +$Comp +L resistor R6 +U 1 1 699856A5 +P 6100 3700 +F 0 "R6" H 6150 3830 50 0000 C CNN +F 1 "8.4k" H 6150 3650 50 0000 C CNN +F 2 "" H 6150 3680 30 0000 C CNN +F 3 "" V 6150 3750 30 0000 C CNN + 1 6100 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8750 3650 8750 3700 +Connection ~ 8300 3650 +Wire Wire Line + 6300 3650 8750 3650 +Wire Wire Line + 6000 3650 5700 3650 +Wire Wire Line + 5700 3650 5700 5250 +Connection ~ 5700 5250 +$Comp +L resistor R8 +U 1 1 69985AA2 +P 6950 3250 +F 0 "R8" H 7000 3380 50 0000 C CNN +F 1 "9k" H 7000 3200 50 0000 C CNN +F 2 "" H 7000 3230 30 0000 C CNN +F 3 "" V 7000 3300 30 0000 C CNN + 1 6950 3250 + 0 1 1 0 +$EndComp +Connection ~ 7000 4450 +$Comp +L resistor R10 +U 1 1 69985C6D +P 7550 3250 +F 0 "R10" H 7600 3380 50 0000 C CNN +F 1 "5k" H 7600 3200 50 0000 C CNN +F 2 "" H 7600 3230 30 0000 C CNN +F 3 "" V 7600 3300 30 0000 C CNN + 1 7550 3250 + 0 1 1 0 +$EndComp +Wire Wire Line + 7600 3450 7600 3650 +Connection ~ 7600 3650 +$Comp +L resistor R12 +U 1 1 69985CF0 +P 9600 2950 +F 0 "R12" H 9650 3080 50 0000 C CNN +F 1 "1.66k" H 9650 2900 50 0000 C CNN +F 2 "" H 9650 2930 30 0000 C CNN +F 3 "" V 9650 3000 30 0000 C CNN + 1 9600 2950 + 0 1 1 0 +$EndComp +Wire Wire Line + 7000 3150 7000 2700 +Wire Wire Line + 7000 2700 10300 2700 +Wire Wire Line + 9650 2850 9650 2700 +Connection ~ 9650 2700 +Wire Wire Line + 7600 3150 7600 2700 +Connection ~ 7600 2700 +Wire Wire Line + 9650 3400 10250 3400 +Connection ~ 9650 3400 +Wire Wire Line + 5450 5750 5450 5900 +Wire Wire Line + 5450 5900 9600 5900 +Wire Wire Line + 9600 5900 9600 3850 +Wire Wire Line + 9600 3850 9650 3850 +Wire Wire Line + 8300 4600 8300 5900 +Connection ~ 8300 5900 +Wire Wire Line + 7000 5400 7000 5900 +Connection ~ 7000 5900 +Wire Wire Line + 5850 5750 5850 5900 +Connection ~ 5850 5900 +Wire Wire Line + 5000 5250 4700 5250 +$Comp +L capacitor_polarised C2 +U 1 1 699866AB +P 10050 3700 +F 0 "C2" H 10075 3800 50 0000 L CNN +F 1 "15pF" H 10075 3600 50 0000 L CNN +F 2 "" H 10050 3700 50 0001 C CNN +F 3 "" H 10050 3700 50 0001 C CNN + 1 10050 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10050 3550 10050 3400 +Connection ~ 10050 3400 +$Comp +L eSim_Diode D10 +U 1 1 699867A2 +P 10400 3400 +F 0 "D10" H 10400 3500 50 0000 C CNN +F 1 "eSim_Diode" H 10400 3300 50 0000 C CNN +F 2 "" H 10400 3400 60 0000 C CNN +F 3 "" H 10400 3400 60 0000 C CNN + 1 10400 3400 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D12 +U 1 1 69986840 +P 11000 3400 +F 0 "D12" H 11000 3500 50 0000 C CNN +F 1 "eSim_Diode" H 11000 3300 50 0000 C CNN +F 2 "" H 11000 3400 60 0000 C CNN +F 3 "" H 11000 3400 60 0000 C CNN + 1 11000 3400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D14 +U 1 1 6998688C +P 11450 3400 +F 0 "D14" H 11450 3500 50 0000 C CNN +F 1 "eSim_Diode" H 11450 3300 50 0000 C CNN +F 2 "" H 11450 3400 60 0000 C CNN +F 3 "" H 11450 3400 60 0000 C CNN + 1 11450 3400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D17 +U 1 1 699868D7 +P 11900 3400 +F 0 "D17" H 11900 3500 50 0000 C CNN +F 1 "eSim_Diode" H 11900 3300 50 0000 C CNN +F 2 "" H 11900 3400 60 0000 C CNN +F 3 "" H 11900 3400 60 0000 C CNN + 1 11900 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11150 3400 11300 3400 +Wire Wire Line + 11600 3400 11750 3400 +Wire Wire Line + 12050 3400 12300 3400 +Wire Wire Line + 12300 3400 12300 3800 +Wire Wire Line + 10550 3400 10850 3400 +Wire Wire Line + 10050 2700 10050 2950 +Wire Wire Line + 10050 2950 10700 2950 +Connection ~ 10050 2700 +$Comp +L resistor R14 +U 1 1 69986C1D +P 10650 3100 +F 0 "R14" H 10700 3230 50 0000 C CNN +F 1 "3.9k" H 10700 3050 50 0000 C CNN +F 2 "" H 10700 3080 30 0000 C CNN +F 3 "" V 10700 3150 30 0000 C CNN + 1 10650 3100 + 0 1 1 0 +$EndComp +Wire Wire Line + 10700 2950 10700 3000 +Wire Wire Line + 10700 3300 10700 3400 +Connection ~ 10700 3400 +Wire Wire Line + 7650 6000 7650 5900 +Connection ~ 7650 5900 +Wire Wire Line + 10050 3850 10050 3950 +Wire Wire Line + 9850 3400 9850 4150 +Wire Wire Line + 9850 4150 10300 4150 +Connection ~ 9850 3400 +$Comp +L eSim_NPN Q1 +U 1 1 69987A24 +P 6450 9900 +F 0 "Q1" H 6350 9950 50 0000 R CNN +F 1 "eSim_NPN" H 6400 10050 50 0000 R CNN +F 2 "" H 6650 10000 29 0000 C CNN +F 3 "" H 6450 9900 60 0000 C CNN + 1 6450 9900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 69987A2A +P 5900 9750 +F 0 "D3" H 5900 9850 50 0000 C CNN +F 1 "eSim_Diode" H 5900 9650 50 0000 C CNN +F 2 "" H 5900 9750 60 0000 C CNN +F 3 "" H 5900 9750 60 0000 C CNN + 1 5900 9750 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5900 9600 5900 9550 +Wire Wire Line + 5900 9550 6550 9550 +Wire Wire Line + 6550 8150 6550 9700 +Wire Wire Line + 5900 9900 5900 9950 +Wire Wire Line + 4850 9950 6250 9950 +Wire Wire Line + 6250 9950 6250 9900 +Connection ~ 5900 9950 +Connection ~ 6550 9550 +$Comp +L eSim_NPN Q3 +U 1 1 69987A38 +P 7750 9100 +F 0 "Q3" H 7650 9150 50 0000 R CNN +F 1 "eSim_NPN" H 7700 9250 50 0000 R CNN +F 2 "" H 7950 9200 29 0000 C CNN +F 3 "" H 7750 9100 60 0000 C CNN + 1 7750 9100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 69987A3E +P 7200 8950 +F 0 "D5" H 7200 9050 50 0000 C CNN +F 1 "eSim_Diode" H 7200 8850 50 0000 C CNN +F 2 "" H 7200 8950 60 0000 C CNN +F 3 "" H 7200 8950 60 0000 C CNN + 1 7200 8950 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7200 8800 7200 8750 +Wire Wire Line + 7200 8750 7850 8750 +Wire Wire Line + 7850 8350 7850 8900 +Wire Wire Line + 7200 9100 7200 9150 +Wire Wire Line + 6550 9150 7550 9150 +Wire Wire Line + 7550 9150 7550 9100 +Connection ~ 7200 9150 +Connection ~ 7850 8750 +$Comp +L eSim_NPN Q5 +U 1 1 69987A4C +P 9100 8350 +F 0 "Q5" H 9000 8400 50 0000 R CNN +F 1 "eSim_NPN" H 9050 8500 50 0000 R CNN +F 2 "" H 9300 8450 29 0000 C CNN +F 3 "" H 9100 8350 60 0000 C CNN + 1 9100 8350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 69987A52 +P 8550 8200 +F 0 "D7" H 8550 8300 50 0000 C CNN +F 1 "eSim_Diode" H 8550 8100 50 0000 C CNN +F 2 "" H 8550 8200 60 0000 C CNN +F 3 "" H 8550 8200 60 0000 C CNN + 1 8550 8200 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8550 8050 8550 8000 +Wire Wire Line + 8550 8000 9200 8000 +Wire Wire Line + 9200 7850 9200 8150 +Wire Wire Line + 8550 8350 8550 8400 +Wire Wire Line + 8300 8400 8900 8400 +Wire Wire Line + 8900 8400 8900 8350 +Connection ~ 8550 8400 +Connection ~ 9200 8000 +$Comp +L resistor R1 +U 1 1 69987A60 +P 4650 10000 +F 0 "R1" H 4700 10130 50 0000 C CNN +F 1 "4k" H 4700 9950 50 0000 C CNN +F 2 "" H 4700 9980 30 0000 C CNN +F 3 "" V 4700 10050 30 0000 C CNN + 1 4650 10000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 69987A66 +P 5000 10300 +F 0 "D1" H 5000 10400 50 0000 C CNN +F 1 "eSim_Diode" H 5000 10200 50 0000 C CNN +F 2 "" H 5000 10300 60 0000 C CNN +F 3 "" H 5000 10300 60 0000 C CNN + 1 5000 10300 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 69987A6C +P 5350 10250 +F 0 "R3" H 5400 10380 50 0000 C CNN +F 1 "10k" H 5400 10200 50 0000 C CNN +F 2 "" H 5400 10230 30 0000 C CNN +F 3 "" V 5400 10300 30 0000 C CNN + 1 5350 10250 + 0 1 1 0 +$EndComp +Wire Wire Line + 5000 10150 5000 9950 +Connection ~ 5000 9950 +Wire Wire Line + 5400 10150 5400 9950 +Connection ~ 5400 9950 +$Comp +L resistor R4 +U 1 1 69987A76 +P 5650 8400 +F 0 "R4" H 5700 8530 50 0000 C CNN +F 1 "8.4k" H 5700 8350 50 0000 C CNN +F 2 "" H 5700 8380 30 0000 C CNN +F 3 "" V 5700 8450 30 0000 C CNN + 1 5650 8400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8300 8350 8300 8400 +Connection ~ 7850 8350 +Wire Wire Line + 5850 8350 8300 8350 +Wire Wire Line + 5550 8350 5250 8350 +Wire Wire Line + 5250 8350 5250 9950 +Connection ~ 5250 9950 +$Comp +L resistor R7 +U 1 1 69987A82 +P 6500 7950 +F 0 "R7" H 6550 8080 50 0000 C CNN +F 1 "9k" H 6550 7900 50 0000 C CNN +F 2 "" H 6550 7930 30 0000 C CNN +F 3 "" V 6550 8000 30 0000 C CNN + 1 6500 7950 + 0 1 1 0 +$EndComp +Connection ~ 6550 9150 +$Comp +L resistor R9 +U 1 1 69987A89 +P 7100 7950 +F 0 "R9" H 7150 8080 50 0000 C CNN +F 1 "5k" H 7150 7900 50 0000 C CNN +F 2 "" H 7150 7930 30 0000 C CNN +F 3 "" V 7150 8000 30 0000 C CNN + 1 7100 7950 + 0 1 1 0 +$EndComp +Wire Wire Line + 7150 8150 7150 8350 +Connection ~ 7150 8350 +$Comp +L resistor R11 +U 1 1 69987A91 +P 9150 7650 +F 0 "R11" H 9200 7780 50 0000 C CNN +F 1 "1.66k" H 9200 7600 50 0000 C CNN +F 2 "" H 9200 7630 30 0000 C CNN +F 3 "" V 9200 7700 30 0000 C CNN + 1 9150 7650 + 0 1 1 0 +$EndComp +Wire Wire Line + 6550 7850 6550 7400 +Wire Wire Line + 6550 7400 9850 7400 +Wire Wire Line + 9200 7550 9200 7400 +Connection ~ 9200 7400 +Wire Wire Line + 7150 7850 7150 7400 +Connection ~ 7150 7400 +Wire Wire Line + 9200 8100 9800 8100 +Connection ~ 9200 8100 +Wire Wire Line + 5000 10450 5000 10600 +Wire Wire Line + 5000 10600 9150 10600 +Wire Wire Line + 9150 10600 9150 8550 +Wire Wire Line + 9150 8550 9200 8550 +Wire Wire Line + 7850 9300 7850 10600 +Connection ~ 7850 10600 +Wire Wire Line + 6550 10100 6550 10600 +Connection ~ 6550 10600 +Wire Wire Line + 5400 10450 5400 10600 +Connection ~ 5400 10600 +Wire Wire Line + 4550 9950 4250 9950 +$Comp +L capacitor_polarised C1 +U 1 1 69987AAA +P 9600 8400 +F 0 "C1" H 9625 8500 50 0000 L CNN +F 1 "15pF" H 9625 8300 50 0000 L CNN +F 2 "" H 9600 8400 50 0001 C CNN +F 3 "" H 9600 8400 50 0001 C CNN + 1 9600 8400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9600 8250 9600 8100 +Connection ~ 9600 8100 +$Comp +L eSim_Diode D9 +U 1 1 69987AB2 +P 9950 8100 +F 0 "D9" H 9950 8200 50 0000 C CNN +F 1 "eSim_Diode" H 9950 8000 50 0000 C CNN +F 2 "" H 9950 8100 60 0000 C CNN +F 3 "" H 9950 8100 60 0000 C CNN + 1 9950 8100 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D11 +U 1 1 69987AB8 +P 10550 8100 +F 0 "D11" H 10550 8200 50 0000 C CNN +F 1 "eSim_Diode" H 10550 8000 50 0000 C CNN +F 2 "" H 10550 8100 60 0000 C CNN +F 3 "" H 10550 8100 60 0000 C CNN + 1 10550 8100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D13 +U 1 1 69987ABE +P 11000 8100 +F 0 "D13" H 11000 8200 50 0000 C CNN +F 1 "eSim_Diode" H 11000 8000 50 0000 C CNN +F 2 "" H 11000 8100 60 0000 C CNN +F 3 "" H 11000 8100 60 0000 C CNN + 1 11000 8100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D15 +U 1 1 69987AC4 +P 11450 8100 +F 0 "D15" H 11450 8200 50 0000 C CNN +F 1 "eSim_Diode" H 11450 8000 50 0000 C CNN +F 2 "" H 11450 8100 60 0000 C CNN +F 3 "" H 11450 8100 60 0000 C CNN + 1 11450 8100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10700 8100 10850 8100 +Wire Wire Line + 11150 8100 11300 8100 +Wire Wire Line + 11600 8100 11850 8100 +Wire Wire Line + 11850 8100 11850 8500 +Wire Wire Line + 10100 8100 10400 8100 +Wire Wire Line + 9600 7400 9600 7650 +Wire Wire Line + 9600 7650 10250 7650 +Connection ~ 9600 7400 +$Comp +L resistor R13 +U 1 1 69987AD2 +P 10200 7800 +F 0 "R13" H 10250 7930 50 0000 C CNN +F 1 "3.9k" H 10250 7750 50 0000 C CNN +F 2 "" H 10250 7780 30 0000 C CNN +F 3 "" V 10250 7850 30 0000 C CNN + 1 10200 7800 + 0 1 1 0 +$EndComp +Wire Wire Line + 10250 7650 10250 7700 +Wire Wire Line + 10250 8000 10250 8100 +Connection ~ 10250 8100 +Wire Wire Line + 7200 10700 7200 10600 +Connection ~ 7200 10600 +Wire Wire Line + 9600 8550 9600 8650 +Wire Wire Line + 9400 8100 9400 8850 +Wire Wire Line + 9400 8850 9850 8850 +Connection ~ 9400 8100 +$Comp +L eSim_NPN Q8 +U 1 1 6998830B +P 13700 6600 +F 0 "Q8" H 13600 6650 50 0000 R CNN +F 1 "eSim_NPN" H 13650 6750 50 0000 R CNN +F 2 "" H 13900 6700 29 0000 C CNN +F 3 "" H 13700 6600 60 0000 C CNN + 1 13700 6600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D20 +U 1 1 69988311 +P 13150 6450 +F 0 "D20" H 13150 6550 50 0000 C CNN +F 1 "eSim_Diode" H 13150 6350 50 0000 C CNN +F 2 "" H 13150 6450 60 0000 C CNN +F 3 "" H 13150 6450 60 0000 C CNN + 1 13150 6450 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 13150 6300 13150 6250 +Wire Wire Line + 13150 6250 13800 6250 +Wire Wire Line + 13800 4850 13800 6400 +Wire Wire Line + 13150 6600 13150 6650 +Wire Wire Line + 12100 6650 13500 6650 +Wire Wire Line + 13500 6650 13500 6600 +Connection ~ 13150 6650 +Connection ~ 13800 6250 +$Comp +L eSim_NPN Q10 +U 1 1 6998831F +P 15000 5800 +F 0 "Q10" H 14900 5850 50 0000 R CNN +F 1 "eSim_NPN" H 14950 5950 50 0000 R CNN +F 2 "" H 15200 5900 29 0000 C CNN +F 3 "" H 15000 5800 60 0000 C CNN + 1 15000 5800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D22 +U 1 1 69988325 +P 14450 5650 +F 0 "D22" H 14450 5750 50 0000 C CNN +F 1 "eSim_Diode" H 14450 5550 50 0000 C CNN +F 2 "" H 14450 5650 60 0000 C CNN +F 3 "" H 14450 5650 60 0000 C CNN + 1 14450 5650 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 14450 5500 14450 5450 +Wire Wire Line + 14450 5450 15100 5450 +Wire Wire Line + 15100 5050 15100 5600 +Wire Wire Line + 14450 5800 14450 5850 +Wire Wire Line + 13800 5850 14800 5850 +Wire Wire Line + 14800 5850 14800 5800 +Connection ~ 14450 5850 +Connection ~ 15100 5450 +$Comp +L eSim_NPN Q12 +U 1 1 69988333 +P 16350 5050 +F 0 "Q12" H 16250 5100 50 0000 R CNN +F 1 "eSim_NPN" H 16300 5200 50 0000 R CNN +F 2 "" H 16550 5150 29 0000 C CNN +F 3 "" H 16350 5050 60 0000 C CNN + 1 16350 5050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D24 +U 1 1 69988339 +P 15800 4900 +F 0 "D24" H 15800 5000 50 0000 C CNN +F 1 "eSim_Diode" H 15800 4800 50 0000 C CNN +F 2 "" H 15800 4900 60 0000 C CNN +F 3 "" H 15800 4900 60 0000 C CNN + 1 15800 4900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 15800 4750 15800 4700 +Wire Wire Line + 15800 4700 16450 4700 +Wire Wire Line + 16450 4550 16450 4850 +Wire Wire Line + 15800 5050 15800 5100 +Wire Wire Line + 15550 5100 16150 5100 +Wire Wire Line + 16150 5100 16150 5050 +Connection ~ 15800 5100 +Connection ~ 16450 4700 +$Comp +L resistor R16 +U 1 1 69988347 +P 11900 6700 +F 0 "R16" H 11950 6830 50 0000 C CNN +F 1 "4k" H 11950 6650 50 0000 C CNN +F 2 "" H 11950 6680 30 0000 C CNN +F 3 "" V 11950 6750 30 0000 C CNN + 1 11900 6700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D18 +U 1 1 6998834D +P 12250 7000 +F 0 "D18" H 12250 7100 50 0000 C CNN +F 1 "eSim_Diode" H 12250 6900 50 0000 C CNN +F 2 "" H 12250 7000 60 0000 C CNN +F 3 "" H 12250 7000 60 0000 C CNN + 1 12250 7000 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R19 +U 1 1 69988353 +P 12600 6950 +F 0 "R19" H 12650 7080 50 0000 C CNN +F 1 "10k" H 12650 6900 50 0000 C CNN +F 2 "" H 12650 6930 30 0000 C CNN +F 3 "" V 12650 7000 30 0000 C CNN + 1 12600 6950 + 0 1 1 0 +$EndComp +Wire Wire Line + 12250 6850 12250 6650 +Connection ~ 12250 6650 +Wire Wire Line + 12650 6850 12650 6650 +Connection ~ 12650 6650 +$Comp +L resistor R20 +U 1 1 6998835D +P 12900 5100 +F 0 "R20" H 12950 5230 50 0000 C CNN +F 1 "8.4k" H 12950 5050 50 0000 C CNN +F 2 "" H 12950 5080 30 0000 C CNN +F 3 "" V 12950 5150 30 0000 C CNN + 1 12900 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15550 5050 15550 5100 +Connection ~ 15100 5050 +Wire Wire Line + 13100 5050 15550 5050 +Wire Wire Line + 12800 5050 12500 5050 +Wire Wire Line + 12500 5050 12500 6650 +Connection ~ 12500 6650 +$Comp +L resistor R22 +U 1 1 69988369 +P 13750 4650 +F 0 "R22" H 13800 4780 50 0000 C CNN +F 1 "9k" H 13800 4600 50 0000 C CNN +F 2 "" H 13800 4630 30 0000 C CNN +F 3 "" V 13800 4700 30 0000 C CNN + 1 13750 4650 + 0 1 1 0 +$EndComp +Connection ~ 13800 5850 +$Comp +L resistor R24 +U 1 1 69988370 +P 14350 4650 +F 0 "R24" H 14400 4780 50 0000 C CNN +F 1 "5k" H 14400 4600 50 0000 C CNN +F 2 "" H 14400 4630 30 0000 C CNN +F 3 "" V 14400 4700 30 0000 C CNN + 1 14350 4650 + 0 1 1 0 +$EndComp +Wire Wire Line + 14400 4850 14400 5050 +Connection ~ 14400 5050 +$Comp +L resistor R26 +U 1 1 69988378 +P 16400 4350 +F 0 "R26" H 16450 4480 50 0000 C CNN +F 1 "1.66k" H 16450 4300 50 0000 C CNN +F 2 "" H 16450 4330 30 0000 C CNN +F 3 "" V 16450 4400 30 0000 C CNN + 1 16400 4350 + 0 1 1 0 +$EndComp +Wire Wire Line + 13800 4550 13800 4100 +Wire Wire Line + 13800 4100 17100 4100 +Wire Wire Line + 16450 4250 16450 4100 +Connection ~ 16450 4100 +Wire Wire Line + 14400 4550 14400 4100 +Connection ~ 14400 4100 +Wire Wire Line + 16450 4800 17050 4800 +Connection ~ 16450 4800 +Wire Wire Line + 12250 7150 12250 7300 +Wire Wire Line + 12250 7300 16400 7300 +Wire Wire Line + 16400 7300 16400 5250 +Wire Wire Line + 16400 5250 16450 5250 +Wire Wire Line + 15100 6000 15100 7300 +Connection ~ 15100 7300 +Wire Wire Line + 13800 6800 13800 7300 +Connection ~ 13800 7300 +Wire Wire Line + 12650 7150 12650 7300 +Connection ~ 12650 7300 +Wire Wire Line + 11800 6650 11500 6650 +$Comp +L capacitor_polarised C4 +U 1 1 69988391 +P 16850 5100 +F 0 "C4" H 16875 5200 50 0000 L CNN +F 1 "15pF" H 16875 5000 50 0000 L CNN +F 2 "" H 16850 5100 50 0001 C CNN +F 3 "" H 16850 5100 50 0001 C CNN + 1 16850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16850 4950 16850 4800 +Connection ~ 16850 4800 +$Comp +L eSim_Diode D26 +U 1 1 69988399 +P 17200 4800 +F 0 "D26" H 17200 4900 50 0000 C CNN +F 1 "eSim_Diode" H 17200 4700 50 0000 C CNN +F 2 "" H 17200 4800 60 0000 C CNN +F 3 "" H 17200 4800 60 0000 C CNN + 1 17200 4800 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D28 +U 1 1 6998839F +P 17800 4800 +F 0 "D28" H 17800 4900 50 0000 C CNN +F 1 "eSim_Diode" H 17800 4700 50 0000 C CNN +F 2 "" H 17800 4800 60 0000 C CNN +F 3 "" H 17800 4800 60 0000 C CNN + 1 17800 4800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D30 +U 1 1 699883A5 +P 18250 4800 +F 0 "D30" H 18250 4900 50 0000 C CNN +F 1 "eSim_Diode" H 18250 4700 50 0000 C CNN +F 2 "" H 18250 4800 60 0000 C CNN +F 3 "" H 18250 4800 60 0000 C CNN + 1 18250 4800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D32 +U 1 1 699883AB +P 18700 4800 +F 0 "D32" H 18700 4900 50 0000 C CNN +F 1 "eSim_Diode" H 18700 4700 50 0000 C CNN +F 2 "" H 18700 4800 60 0000 C CNN +F 3 "" H 18700 4800 60 0000 C CNN + 1 18700 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 17950 4800 18100 4800 +Wire Wire Line + 18400 4800 18550 4800 +Wire Wire Line + 18850 4800 19100 4800 +Wire Wire Line + 19100 4800 19100 5200 +Wire Wire Line + 17350 4800 17650 4800 +Wire Wire Line + 16850 4100 16850 4350 +Wire Wire Line + 16850 4350 17500 4350 +Connection ~ 16850 4100 +$Comp +L resistor R28 +U 1 1 699883B9 +P 17450 4500 +F 0 "R28" H 17500 4630 50 0000 C CNN +F 1 "3.9k" H 17500 4450 50 0000 C CNN +F 2 "" H 17500 4480 30 0000 C CNN +F 3 "" V 17500 4550 30 0000 C CNN + 1 17450 4500 + 0 1 1 0 +$EndComp +Wire Wire Line + 17500 4350 17500 4400 +Wire Wire Line + 17500 4700 17500 4800 +Connection ~ 17500 4800 +Wire Wire Line + 14450 7400 14450 7300 +Connection ~ 14450 7300 +Wire Wire Line + 16850 5250 16850 5350 +Wire Wire Line + 16650 4800 16650 5550 +Wire Wire Line + 16650 5550 17100 5550 +Connection ~ 16650 4800 +$Comp +L eSim_NPN Q7 +U 1 1 699883C8 +P 13250 11300 +F 0 "Q7" H 13150 11350 50 0000 R CNN +F 1 "eSim_NPN" H 13200 11450 50 0000 R CNN +F 2 "" H 13450 11400 29 0000 C CNN +F 3 "" H 13250 11300 60 0000 C CNN + 1 13250 11300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D19 +U 1 1 699883CE +P 12700 11150 +F 0 "D19" H 12700 11250 50 0000 C CNN +F 1 "eSim_Diode" H 12700 11050 50 0000 C CNN +F 2 "" H 12700 11150 60 0000 C CNN +F 3 "" H 12700 11150 60 0000 C CNN + 1 12700 11150 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 12700 11000 12700 10950 +Wire Wire Line + 12700 10950 13350 10950 +Wire Wire Line + 13350 9550 13350 11100 +Wire Wire Line + 12700 11300 12700 11350 +Wire Wire Line + 11650 11350 13050 11350 +Wire Wire Line + 13050 11350 13050 11300 +Connection ~ 12700 11350 +Connection ~ 13350 10950 +$Comp +L eSim_NPN Q9 +U 1 1 699883DC +P 14550 10500 +F 0 "Q9" H 14450 10550 50 0000 R CNN +F 1 "eSim_NPN" H 14500 10650 50 0000 R CNN +F 2 "" H 14750 10600 29 0000 C CNN +F 3 "" H 14550 10500 60 0000 C CNN + 1 14550 10500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D21 +U 1 1 699883E2 +P 14000 10350 +F 0 "D21" H 14000 10450 50 0000 C CNN +F 1 "eSim_Diode" H 14000 10250 50 0000 C CNN +F 2 "" H 14000 10350 60 0000 C CNN +F 3 "" H 14000 10350 60 0000 C CNN + 1 14000 10350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 14000 10200 14000 10150 +Wire Wire Line + 14000 10150 14650 10150 +Wire Wire Line + 14650 9750 14650 10300 +Wire Wire Line + 14000 10500 14000 10550 +Wire Wire Line + 13350 10550 14350 10550 +Wire Wire Line + 14350 10550 14350 10500 +Connection ~ 14000 10550 +Connection ~ 14650 10150 +$Comp +L eSim_NPN Q11 +U 1 1 699883F0 +P 15900 9750 +F 0 "Q11" H 15800 9800 50 0000 R CNN +F 1 "eSim_NPN" H 15850 9900 50 0000 R CNN +F 2 "" H 16100 9850 29 0000 C CNN +F 3 "" H 15900 9750 60 0000 C CNN + 1 15900 9750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D23 +U 1 1 699883F6 +P 15350 9600 +F 0 "D23" H 15350 9700 50 0000 C CNN +F 1 "eSim_Diode" H 15350 9500 50 0000 C CNN +F 2 "" H 15350 9600 60 0000 C CNN +F 3 "" H 15350 9600 60 0000 C CNN + 1 15350 9600 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 15350 9450 15350 9400 +Wire Wire Line + 15350 9400 16000 9400 +Wire Wire Line + 16000 9250 16000 9550 +Wire Wire Line + 15350 9750 15350 9800 +Wire Wire Line + 15100 9800 15700 9800 +Wire Wire Line + 15700 9800 15700 9750 +Connection ~ 15350 9800 +Connection ~ 16000 9400 +$Comp +L resistor R15 +U 1 1 69988404 +P 11450 11400 +F 0 "R15" H 11500 11530 50 0000 C CNN +F 1 "4k" H 11500 11350 50 0000 C CNN +F 2 "" H 11500 11380 30 0000 C CNN +F 3 "" V 11500 11450 30 0000 C CNN + 1 11450 11400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D16 +U 1 1 6998840A +P 11800 11700 +F 0 "D16" H 11800 11800 50 0000 C CNN +F 1 "eSim_Diode" H 11800 11600 50 0000 C CNN +F 2 "" H 11800 11700 60 0000 C CNN +F 3 "" H 11800 11700 60 0000 C CNN + 1 11800 11700 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R17 +U 1 1 69988410 +P 12150 11650 +F 0 "R17" H 12200 11780 50 0000 C CNN +F 1 "10k" H 12200 11600 50 0000 C CNN +F 2 "" H 12200 11630 30 0000 C CNN +F 3 "" V 12200 11700 30 0000 C CNN + 1 12150 11650 + 0 1 1 0 +$EndComp +Wire Wire Line + 11800 11550 11800 11350 +Connection ~ 11800 11350 +Wire Wire Line + 12200 11550 12200 11350 +Connection ~ 12200 11350 +$Comp +L resistor R18 +U 1 1 6998841A +P 12450 9800 +F 0 "R18" H 12500 9930 50 0000 C CNN +F 1 "8.4k" H 12500 9750 50 0000 C CNN +F 2 "" H 12500 9780 30 0000 C CNN +F 3 "" V 12500 9850 30 0000 C CNN + 1 12450 9800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 15100 9750 15100 9800 +Connection ~ 14650 9750 +Wire Wire Line + 12650 9750 15100 9750 +Wire Wire Line + 12350 9750 12050 9750 +Wire Wire Line + 12050 9750 12050 11350 +Connection ~ 12050 11350 +$Comp +L resistor R21 +U 1 1 69988426 +P 13300 9350 +F 0 "R21" H 13350 9480 50 0000 C CNN +F 1 "9k" H 13350 9300 50 0000 C CNN +F 2 "" H 13350 9330 30 0000 C CNN +F 3 "" V 13350 9400 30 0000 C CNN + 1 13300 9350 + 0 1 1 0 +$EndComp +Connection ~ 13350 10550 +$Comp +L resistor R23 +U 1 1 6998842D +P 13900 9350 +F 0 "R23" H 13950 9480 50 0000 C CNN +F 1 "5k" H 13950 9300 50 0000 C CNN +F 2 "" H 13950 9330 30 0000 C CNN +F 3 "" V 13950 9400 30 0000 C CNN + 1 13900 9350 + 0 1 1 0 +$EndComp +Wire Wire Line + 13950 9550 13950 9750 +Connection ~ 13950 9750 +$Comp +L resistor R25 +U 1 1 69988435 +P 15950 9050 +F 0 "R25" H 16000 9180 50 0000 C CNN +F 1 "1.66k" H 16000 9000 50 0000 C CNN +F 2 "" H 16000 9030 30 0000 C CNN +F 3 "" V 16000 9100 30 0000 C CNN + 1 15950 9050 + 0 1 1 0 +$EndComp +Wire Wire Line + 13350 9250 13350 8800 +Wire Wire Line + 13350 8800 16650 8800 +Wire Wire Line + 16000 8950 16000 8800 +Connection ~ 16000 8800 +Wire Wire Line + 13950 9250 13950 8800 +Connection ~ 13950 8800 +Wire Wire Line + 16000 9500 16600 9500 +Connection ~ 16000 9500 +Wire Wire Line + 11800 11850 11800 12000 +Wire Wire Line + 11800 12000 15950 12000 +Wire Wire Line + 15950 12000 15950 9950 +Wire Wire Line + 15950 9950 16000 9950 +Wire Wire Line + 14650 10700 14650 12000 +Connection ~ 14650 12000 +Wire Wire Line + 13350 11500 13350 12000 +Connection ~ 13350 12000 +Wire Wire Line + 12200 11850 12200 12000 +Connection ~ 12200 12000 +Wire Wire Line + 11350 11350 11050 11350 +$Comp +L capacitor_polarised C3 +U 1 1 6998844E +P 16400 9800 +F 0 "C3" H 16425 9900 50 0000 L CNN +F 1 "15pF" H 16425 9700 50 0000 L CNN +F 2 "" H 16400 9800 50 0001 C CNN +F 3 "" H 16400 9800 50 0001 C CNN + 1 16400 9800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16400 9650 16400 9500 +Connection ~ 16400 9500 +$Comp +L eSim_Diode D25 +U 1 1 69988456 +P 16750 9500 +F 0 "D25" H 16750 9600 50 0000 C CNN +F 1 "eSim_Diode" H 16750 9400 50 0000 C CNN +F 2 "" H 16750 9500 60 0000 C CNN +F 3 "" H 16750 9500 60 0000 C CNN + 1 16750 9500 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D27 +U 1 1 6998845C +P 17350 9500 +F 0 "D27" H 17350 9600 50 0000 C CNN +F 1 "eSim_Diode" H 17350 9400 50 0000 C CNN +F 2 "" H 17350 9500 60 0000 C CNN +F 3 "" H 17350 9500 60 0000 C CNN + 1 17350 9500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D29 +U 1 1 69988462 +P 17800 9500 +F 0 "D29" H 17800 9600 50 0000 C CNN +F 1 "eSim_Diode" H 17800 9400 50 0000 C CNN +F 2 "" H 17800 9500 60 0000 C CNN +F 3 "" H 17800 9500 60 0000 C CNN + 1 17800 9500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D31 +U 1 1 69988468 +P 18250 9500 +F 0 "D31" H 18250 9600 50 0000 C CNN +F 1 "eSim_Diode" H 18250 9400 50 0000 C CNN +F 2 "" H 18250 9500 60 0000 C CNN +F 3 "" H 18250 9500 60 0000 C CNN + 1 18250 9500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 17500 9500 17650 9500 +Wire Wire Line + 17950 9500 18100 9500 +Wire Wire Line + 18400 9500 18650 9500 +Wire Wire Line + 18650 9500 18650 9900 +Wire Wire Line + 16900 9500 17200 9500 +Wire Wire Line + 16400 8800 16400 9050 +Wire Wire Line + 16400 9050 17050 9050 +Connection ~ 16400 8800 +$Comp +L resistor R27 +U 1 1 69988476 +P 17000 9200 +F 0 "R27" H 17050 9330 50 0000 C CNN +F 1 "3.9k" H 17050 9150 50 0000 C CNN +F 2 "" H 17050 9180 30 0000 C CNN +F 3 "" V 17050 9250 30 0000 C CNN + 1 17000 9200 + 0 1 1 0 +$EndComp +Wire Wire Line + 17050 9050 17050 9100 +Wire Wire Line + 17050 9400 17050 9500 +Connection ~ 17050 9500 +Wire Wire Line + 14000 12100 14000 12000 +Connection ~ 14000 12000 +Wire Wire Line + 16400 9950 16400 10050 +Wire Wire Line + 16200 9500 16200 10250 +Wire Wire Line + 16200 10250 16650 10250 +Connection ~ 16200 9500 +$Comp +L PORT U1 +U 10 1 69988C3F +P 11250 6650 +F 0 "U1" H 11300 6750 30 0000 C CNN +F 1 "PORT" H 11250 6650 30 0000 C CNN +F 2 "" H 11250 6650 60 0000 C CNN +F 3 "" H 11250 6650 60 0000 C CNN + 10 11250 6650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 69988D18 +P 16900 10250 +F 0 "U1" H 16950 10350 30 0000 C CNN +F 1 "PORT" H 16900 10250 30 0000 C CNN +F 2 "" H 16900 10250 60 0000 C CNN +F 3 "" H 16900 10250 60 0000 C CNN + 11 16900 10250 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 69988DCD +P 3200 3300 +F 0 "U1" H 3250 3400 30 0000 C CNN +F 1 "PORT" H 3200 3300 30 0000 C CNN +F 2 "" H 3200 3300 60 0000 C CNN +F 3 "" H 3200 3300 60 0000 C CNN + 12 3200 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 69988E80 +P 3150 3750 +F 0 "U1" H 3200 3850 30 0000 C CNN +F 1 "PORT" H 3150 3750 30 0000 C CNN +F 2 "" H 3150 3750 60 0000 C CNN +F 3 "" H 3150 3750 60 0000 C CNN + 7 3150 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 69988F3D +P 17350 5550 +F 0 "U1" H 17400 5650 30 0000 C CNN +F 1 "PORT" H 17350 5550 30 0000 C CNN +F 2 "" H 17350 5550 60 0000 C CNN +F 3 "" H 17350 5550 60 0000 C CNN + 8 17350 5550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 699891E8 +P 10800 11350 +F 0 "U1" H 10850 11450 30 0000 C CNN +F 1 "PORT" H 10800 11350 30 0000 C CNN +F 2 "" H 10800 11350 60 0000 C CNN +F 3 "" H 10800 11350 60 0000 C CNN + 13 10800 11350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 699892AB +P 3150 5000 +F 0 "U1" H 3200 5100 30 0000 C CNN +F 1 "PORT" H 3150 5000 30 0000 C CNN +F 2 "" H 3150 5000 60 0000 C CNN +F 3 "" H 3150 5000 60 0000 C CNN + 9 3150 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 69989374 +P 3200 5350 +F 0 "U1" H 3250 5450 30 0000 C CNN +F 1 "PORT" H 3200 5350 30 0000 C CNN +F 2 "" H 3200 5350 60 0000 C CNN +F 3 "" H 3200 5350 60 0000 C CNN + 14 3200 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 69989443 +P 3050 5700 +F 0 "U1" H 3100 5800 30 0000 C CNN +F 1 "PORT" H 3050 5700 30 0000 C CNN +F 2 "" H 3050 5700 60 0000 C CNN +F 3 "" H 3050 5700 60 0000 C CNN + 2 3050 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 69989504 +P 10550 4150 +F 0 "U1" H 10600 4250 30 0000 C CNN +F 1 "PORT" H 10550 4150 30 0000 C CNN +F 2 "" H 10550 4150 60 0000 C CNN +F 3 "" H 10550 4150 60 0000 C CNN + 3 10550 4150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 699895C5 +P 4450 5250 +F 0 "U1" H 4500 5350 30 0000 C CNN +F 1 "PORT" H 4450 5250 30 0000 C CNN +F 2 "" H 4450 5250 60 0000 C CNN +F 3 "" H 4450 5250 60 0000 C CNN + 1 4450 5250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 69989841 +P 4000 9950 +F 0 "U1" H 4050 10050 30 0000 C CNN +F 1 "PORT" H 4000 9950 30 0000 C CNN +F 2 "" H 4000 9950 60 0000 C CNN +F 3 "" H 4000 9950 60 0000 C CNN + 4 4000 9950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 69989910 +P 3050 7100 +F 0 "U1" H 3100 7200 30 0000 C CNN +F 1 "PORT" H 3050 7100 30 0000 C CNN +F 2 "" H 3050 7100 60 0000 C CNN +F 3 "" H 3050 7100 60 0000 C CNN + 5 3050 7100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 699899DD +P 10100 8850 +F 0 "U1" H 10150 8950 30 0000 C CNN +F 1 "PORT" H 10100 8850 30 0000 C CNN +F 2 "" H 10100 8850 60 0000 C CNN +F 3 "" H 10100 8850 60 0000 C CNN + 6 10100 8850 + -1 0 0 1 +$EndComp +Text GLabel 3550 5350 2 60 Input ~ 0 +VCC +Text GLabel 3700 3750 2 60 Input ~ 0 +GND +Wire Wire Line + 3400 3750 3700 3750 +Wire Wire Line + 3450 5350 3550 5350 +Text GLabel 10300 2700 2 60 Input ~ 0 +VCC +Text GLabel 17100 4100 2 60 Input ~ 0 +VCC +Text GLabel 9850 7400 2 60 Input ~ 0 +VCC +Text GLabel 16650 8800 2 60 Input ~ 0 +VCC +Text GLabel 7650 6000 3 60 Input ~ 0 +GND +Text GLabel 14450 7400 3 60 Input ~ 0 +GND +Text GLabel 14000 12100 3 60 Input ~ 0 +GND +Text GLabel 7200 10700 3 60 Input ~ 0 +GND +Text GLabel 9600 8650 2 60 Input ~ 0 +GND +Text GLabel 11850 8500 2 60 Input ~ 0 +GND +Text GLabel 10050 3950 2 60 Input ~ 0 +GND +Text GLabel 12300 3800 2 60 Input ~ 0 +GND +Text GLabel 16850 5350 2 60 Input ~ 0 +GND +Text GLabel 19100 5200 2 60 Input ~ 0 +GND +Text GLabel 16400 10050 2 60 Input ~ 0 +GND +Text GLabel 18650 9900 2 60 Input ~ 0 +GND +NoConn ~ 3300 7100 +NoConn ~ 3300 5700 +NoConn ~ 3400 5000 +NoConn ~ 3450 3300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN55189/SN55189.sub b/library/SubcircuitLibrary/SN55189/SN55189.sub new file mode 100644 index 000000000..b077d8b26 --- /dev/null +++ b/library/SubcircuitLibrary/SN55189/SN55189.sub @@ -0,0 +1,84 @@ +* Subcircuit SN55189 +.subckt SN55189 net-_r2-pad1_ ? net-_c2-pad1_ net-_r1-pad1_ ? net-_c1-pad1_ gnd net-_c4-pad1_ ? net-_r16-pad1_ net-_c3-pad1_ ? net-_r15-pad1_ vcc +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn55189\sn55189.cir +.include NPN.lib +.include schottky.lib +q2 net-_d4-pad2_ net-_d2-pad2_ gnd Q2N2222 +d4 net-_d2-pad2_ net-_d4-pad2_ 1N5819 +q4 net-_d6-pad2_ net-_d4-pad2_ gnd Q2N2222 +d6 net-_d4-pad2_ net-_d6-pad2_ 1N5819 +q6 net-_c2-pad1_ net-_d6-pad2_ gnd Q2N2222 +d8 net-_d6-pad2_ net-_c2-pad1_ 1N5819 +r2 net-_r2-pad1_ net-_d2-pad2_ 4k +d2 gnd net-_d2-pad2_ 1N5819 +r5 net-_d2-pad2_ gnd 10k +r6 net-_d2-pad2_ net-_d6-pad2_ 8.4k +r8 vcc net-_d4-pad2_ 9k +r10 vcc net-_d6-pad2_ 5k +r12 vcc net-_c2-pad1_ 1.66k +c2 net-_c2-pad1_ gnd 15pf +d10 net-_d10-pad1_ net-_c2-pad1_ 1N5819 +d12 net-_d10-pad1_ net-_d12-pad2_ 1N5819 +d14 net-_d12-pad2_ net-_d14-pad2_ 1N5819 +d17 net-_d14-pad2_ gnd 1N5819 +r14 vcc net-_d10-pad1_ 3.9k +q1 net-_d3-pad2_ net-_d1-pad2_ gnd Q2N2222 +d3 net-_d1-pad2_ net-_d3-pad2_ 1N5819 +q3 net-_d5-pad2_ net-_d3-pad2_ gnd Q2N2222 +d5 net-_d3-pad2_ net-_d5-pad2_ 1N5819 +q5 net-_c1-pad1_ net-_d5-pad2_ gnd Q2N2222 +d7 net-_d5-pad2_ net-_c1-pad1_ 1N5819 +r1 net-_r1-pad1_ net-_d1-pad2_ 4k +d1 gnd net-_d1-pad2_ 1N5819 +r3 net-_d1-pad2_ gnd 10k +r4 net-_d1-pad2_ net-_d5-pad2_ 8.4k +r7 vcc net-_d3-pad2_ 9k +r9 vcc net-_d5-pad2_ 5k +r11 vcc net-_c1-pad1_ 1.66k +c1 net-_c1-pad1_ gnd 15pf +d9 net-_d11-pad1_ net-_c1-pad1_ 1N5819 +d11 net-_d11-pad1_ net-_d11-pad2_ 1N5819 +d13 net-_d11-pad2_ net-_d13-pad2_ 1N5819 +d15 net-_d13-pad2_ gnd 1N5819 +r13 vcc net-_d11-pad1_ 3.9k +q8 net-_d20-pad2_ net-_d18-pad2_ gnd Q2N2222 +d20 net-_d18-pad2_ net-_d20-pad2_ 1N5819 +q10 net-_d22-pad2_ net-_d20-pad2_ gnd Q2N2222 +d22 net-_d20-pad2_ net-_d22-pad2_ 1N5819 +q12 net-_c4-pad1_ net-_d22-pad2_ gnd Q2N2222 +d24 net-_d22-pad2_ net-_c4-pad1_ 1N5819 +r16 net-_r16-pad1_ net-_d18-pad2_ 4k +d18 gnd net-_d18-pad2_ 1N5819 +r19 net-_d18-pad2_ gnd 10k +r20 net-_d18-pad2_ net-_d22-pad2_ 8.4k +r22 vcc net-_d20-pad2_ 9k +r24 vcc net-_d22-pad2_ 5k +r26 vcc net-_c4-pad1_ 1.66k +c4 net-_c4-pad1_ gnd 15pf +d26 net-_d26-pad1_ net-_c4-pad1_ 1N5819 +d28 net-_d26-pad1_ net-_d28-pad2_ 1N5819 +d30 net-_d28-pad2_ net-_d30-pad2_ 1N5819 +d32 net-_d30-pad2_ gnd 1N5819 +r28 vcc net-_d26-pad1_ 3.9k +q7 net-_d19-pad2_ net-_d16-pad2_ gnd Q2N2222 +d19 net-_d16-pad2_ net-_d19-pad2_ 1N5819 +q9 net-_d21-pad2_ net-_d19-pad2_ gnd Q2N2222 +d21 net-_d19-pad2_ net-_d21-pad2_ 1N5819 +q11 net-_c3-pad1_ net-_d21-pad2_ gnd Q2N2222 +d23 net-_d21-pad2_ net-_c3-pad1_ 1N5819 +r15 net-_r15-pad1_ net-_d16-pad2_ 4k +d16 gnd net-_d16-pad2_ 1N5819 +r17 net-_d16-pad2_ gnd 10k +r18 net-_d16-pad2_ net-_d21-pad2_ 8.4k +r21 vcc net-_d19-pad2_ 9k +r23 vcc net-_d21-pad2_ 5k +r25 vcc net-_c3-pad1_ 1.66k +c3 net-_c3-pad1_ gnd 15pf +d25 net-_d25-pad1_ net-_c3-pad1_ 1N5819 +d27 net-_d25-pad1_ net-_d27-pad2_ 1N5819 +d29 net-_d27-pad2_ net-_d29-pad2_ 1N5819 +d31 net-_d29-pad2_ gnd 1N5819 +r27 vcc net-_d25-pad1_ 3.9k +* Control Statements + +.ends SN55189 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55189/SN55189_Previous_Values.xml b/library/SubcircuitLibrary/SN55189/SN55189_Previous_Values.xml new file mode 100644 index 000000000..af199556e --- /dev/null +++ b/library/SubcircuitLibrary/SN55189/SN55189_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperessecsecsecC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\schottky.lib \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55189/analysis b/library/SubcircuitLibrary/SN55189/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN55189/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55189/schottky.lib b/library/SubcircuitLibrary/SN55189/schottky.lib new file mode 100644 index 000000000..9579f7352 --- /dev/null +++ b/library/SubcircuitLibrary/SN55189/schottky.lib @@ -0,0 +1 @@ +.model 1N5819 D(IS=390n RS=0.115 BV=40.0 IBV=1.00m CJO=203p M=0.333 N=1.70 TT=4.32u) diff --git a/library/SubcircuitLibrary/SN74S251/3_and-cache.lib b/library/SubcircuitLibrary/SN74S251/3_and-cache.lib new file mode 100644 index 000000000..af0586415 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74S251/3_and.cir b/library/SubcircuitLibrary/SN74S251/3_and.cir new file mode 100644 index 000000000..ba296cf01 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74S251/3_and.cir.out b/library/SubcircuitLibrary/SN74S251/3_and.cir.out new file mode 100644 index 000000000..d7cf79a07 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74S251/3_and.pro b/library/SubcircuitLibrary/SN74S251/3_and.pro new file mode 100644 index 000000000..da3e199e2 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 20:00:16 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/SN74S251/3_and.sch b/library/SubcircuitLibrary/SN74S251/3_and.sch new file mode 100644 index 000000000..d6ac89f95 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74S251/3_and.sub b/library/SubcircuitLibrary/SN74S251/3_and.sub new file mode 100644 index 000000000..3d9120bb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S251/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74S251/3_and_Previous_Values.xml new file mode 100644 index 000000000..abc5faaae --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/3_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S251/5_and-cache.lib b/library/SubcircuitLibrary/SN74S251/5_and-cache.lib new file mode 100644 index 000000000..fc177c1f9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74S251/5_and-rescue.lib b/library/SubcircuitLibrary/SN74S251/5_and-rescue.lib new file mode 100644 index 000000000..483b8efb8 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/5_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74S251/5_and.cir b/library/SubcircuitLibrary/SN74S251/5_and.cir new file mode 100644 index 000000000..6a05b9b5d --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74S251/5_and.cir.out b/library/SubcircuitLibrary/SN74S251/5_and.cir.out new file mode 100644 index 000000000..6a6b126a7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74S251/5_and.pro b/library/SubcircuitLibrary/SN74S251/5_and.pro new file mode 100644 index 000000000..c16a3f858 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/5_and.pro @@ -0,0 +1,49 @@ +update=Wed Mar 18 19:59:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_User +LibName15=eSim_Sources +LibName16=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74S251/5_and.sch b/library/SubcircuitLibrary/SN74S251/5_and.sch new file mode 100644 index 000000000..aef3c0436 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:5_and-rescue +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_User +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-5_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74S251/5_and.sub b/library/SubcircuitLibrary/SN74S251/5_and.sub new file mode 100644 index 000000000..35b10e173 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S251/5_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74S251/5_and_Previous_Values.xml new file mode 100644 index 000000000..ae2c08a7f --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/5_and_Previous_Values.xml @@ -0,0 +1 @@ +d_andd_andC:\Users\malli\eSim\src\SubcircuitLibrary\3_andtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S251/SN74S251-cache.lib b/library/SubcircuitLibrary/SN74S251/SN74S251-cache.lib new file mode 100644 index 000000000..ca315d6e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/SN74S251-cache.lib @@ -0,0 +1,115 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# nor8_enable +# +DEF nor8_enable U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "nor8_enable" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 900 0 1 0 N +X a7 1 2150 1900 200 R 50 50 1 1 I +X a6 2 2150 1800 200 R 50 50 1 1 I +X a5 3 2150 1700 200 R 50 50 1 1 I +X a4 4 2150 1600 200 R 50 50 1 1 I +X a3 5 2150 1500 200 R 50 50 1 1 I +X a2 6 2150 1400 200 R 50 50 1 1 I +X a1 7 2150 1300 200 R 50 50 1 1 I +X a0 8 2150 1200 200 R 50 50 1 1 I +X en0 9 2150 1100 200 R 50 50 1 1 I +X y0 10 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# one_input_tristate_buffer +# +DEF one_input_tristate_buffer U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "one_input_tristate_buffer" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2350 2100 3350 1600 0 1 0 N +X A0 1 2150 1900 200 R 50 50 1 1 I +X EN0 2 2150 1800 200 R 50 50 1 1 I +X Y0 3 3550 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74S251/SN74S251.cir b/library/SubcircuitLibrary/SN74S251/SN74S251.cir new file mode 100644 index 000000000..9a6e3f3a2 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/SN74S251.cir @@ -0,0 +1,29 @@ +* C:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\SN74S251\SN74S251.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/21/26 22:51:22 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad4_ Net-_U3-Pad2_ Net-_U5-Pad2_ Net-_U4-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad8_ 5_and +X2 Net-_U1-Pad3_ Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U4-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad7_ 5_and +X3 Net-_U1-Pad2_ Net-_U3-Pad2_ Net-_U7-Pad2_ Net-_U4-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad6_ 5_and +X4 Net-_U1-Pad1_ Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U4-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad5_ 5_and +X5 Net-_U1-Pad15_ Net-_U3-Pad2_ Net-_U5-Pad2_ Net-_U8-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad4_ 5_and +X6 Net-_U1-Pad14_ Net-_U6-Pad2_ Net-_U5-Pad2_ Net-_U8-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad3_ 5_and +X7 Net-_U1-Pad13_ Net-_U3-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad2_ 5_and +X8 Net-_U1-Pad12_ Net-_U6-Pad2_ Net-_U7-Pad2_ Net-_U8-Pad2_ Net-_U10-Pad2_ Net-_U9-Pad1_ 5_and +U2 Net-_U1-Pad7_ Net-_U10-Pad2_ d_inverter +U8 Net-_U4-Pad2_ Net-_U8-Pad2_ d_inverter +U4 Net-_U1-Pad9_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad10_ Net-_U5-Pad2_ d_inverter +U7 Net-_U5-Pad2_ Net-_U7-Pad2_ d_inverter +U6 Net-_U3-Pad2_ Net-_U6-Pad2_ d_inverter +U3 Net-_U1-Pad11_ Net-_U3-Pad2_ d_inverter +U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U9-Pad3_ Net-_U9-Pad4_ Net-_U9-Pad5_ Net-_U9-Pad6_ Net-_U9-Pad7_ Net-_U9-Pad8_ Net-_U10-Pad2_ Net-_U1-Pad6_ nor8_enable +U10 Net-_U1-Pad6_ Net-_U10-Pad2_ Net-_U10-Pad3_ one_input_tristate_buffer +U11 Net-_U10-Pad3_ Net-_U1-Pad5_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN74S251/SN74S251.cir.out b/library/SubcircuitLibrary/SN74S251/SN74S251.cir.out new file mode 100644 index 000000000..96cafe374 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/SN74S251.cir.out @@ -0,0 +1,61 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74s251\sn74s251.cir + +.include 5_and.sub +x1 net-_u1-pad4_ net-_u3-pad2_ net-_u5-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad8_ 5_and +x2 net-_u1-pad3_ net-_u6-pad2_ net-_u5-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad7_ 5_and +x3 net-_u1-pad2_ net-_u3-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad6_ 5_and +x4 net-_u1-pad1_ net-_u6-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad5_ 5_and +x5 net-_u1-pad15_ net-_u3-pad2_ net-_u5-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad4_ 5_and +x6 net-_u1-pad14_ net-_u6-pad2_ net-_u5-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad3_ 5_and +x7 net-_u1-pad13_ net-_u3-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad2_ 5_and +x8 net-_u1-pad12_ net-_u6-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad1_ 5_and +* u2 net-_u1-pad7_ net-_u10-pad2_ d_inverter +* u8 net-_u4-pad2_ net-_u8-pad2_ d_inverter +* u4 net-_u1-pad9_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad10_ net-_u5-pad2_ d_inverter +* u7 net-_u5-pad2_ net-_u7-pad2_ d_inverter +* u6 net-_u3-pad2_ net-_u6-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u9-pad3_ net-_u9-pad4_ net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ net-_u10-pad2_ net-_u1-pad6_ nor8_enable +* u10 net-_u1-pad6_ net-_u10-pad2_ net-_u10-pad3_ one_input_tristate_buffer +* u11 net-_u10-pad3_ net-_u1-pad5_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +a1 net-_u1-pad7_ net-_u10-pad2_ u2 +a2 net-_u4-pad2_ net-_u8-pad2_ u8 +a3 net-_u1-pad9_ net-_u4-pad2_ u4 +a4 net-_u1-pad10_ net-_u5-pad2_ u5 +a5 net-_u5-pad2_ net-_u7-pad2_ u7 +a6 net-_u3-pad2_ net-_u6-pad2_ u6 +a7 net-_u1-pad11_ net-_u3-pad2_ u3 +a8 [net-_u9-pad1_ net-_u9-pad2_ net-_u9-pad3_ net-_u9-pad4_ net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ ] [net-_u10-pad2_ ] [net-_u1-pad6_ ] u9 +a9 [net-_u1-pad6_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] u10 +a10 net-_u10-pad3_ net-_u1-pad5_ u11 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: nor8_enable, NgSpice Name: nor8_enable +.model u9 nor8_enable(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u10 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74S251/SN74S251.pro b/library/SubcircuitLibrary/SN74S251/SN74S251.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/SN74S251.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74S251/SN74S251.sch b/library/SubcircuitLibrary/SN74S251/SN74S251.sch new file mode 100644 index 000000000..6a9c3e3c0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/SN74S251.sch @@ -0,0 +1,656 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74S251-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 6999DFBD +P 11550 4000 +F 0 "X1" H 11600 3900 60 0000 C CNN +F 1 "5_and" H 11650 4150 60 0000 C CNN +F 2 "" H 11550 4000 60 0000 C CNN +F 3 "" H 11550 4000 60 0000 C CNN + 1 11550 4000 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X2 +U 1 1 6999E02D +P 11550 5000 +F 0 "X2" H 11600 4900 60 0000 C CNN +F 1 "5_and" H 11650 5150 60 0000 C CNN +F 2 "" H 11550 5000 60 0000 C CNN +F 3 "" H 11550 5000 60 0000 C CNN + 1 11550 5000 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X3 +U 1 1 6999E0B7 +P 11550 5900 +F 0 "X3" H 11600 5800 60 0000 C CNN +F 1 "5_and" H 11650 6050 60 0000 C CNN +F 2 "" H 11550 5900 60 0000 C CNN +F 3 "" H 11550 5900 60 0000 C CNN + 1 11550 5900 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X4 +U 1 1 6999E0BD +P 11550 6900 +F 0 "X4" H 11600 6800 60 0000 C CNN +F 1 "5_and" H 11650 7050 60 0000 C CNN +F 2 "" H 11550 6900 60 0000 C CNN +F 3 "" H 11550 6900 60 0000 C CNN + 1 11550 6900 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X5 +U 1 1 6999E217 +P 11600 7950 +F 0 "X5" H 11650 7850 60 0000 C CNN +F 1 "5_and" H 11700 8100 60 0000 C CNN +F 2 "" H 11600 7950 60 0000 C CNN +F 3 "" H 11600 7950 60 0000 C CNN + 1 11600 7950 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X6 +U 1 1 6999E21D +P 11600 8950 +F 0 "X6" H 11650 8850 60 0000 C CNN +F 1 "5_and" H 11700 9100 60 0000 C CNN +F 2 "" H 11600 8950 60 0000 C CNN +F 3 "" H 11600 8950 60 0000 C CNN + 1 11600 8950 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X7 +U 1 1 6999E223 +P 11600 9850 +F 0 "X7" H 11650 9750 60 0000 C CNN +F 1 "5_and" H 11700 10000 60 0000 C CNN +F 2 "" H 11600 9850 60 0000 C CNN +F 3 "" H 11600 9850 60 0000 C CNN + 1 11600 9850 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X8 +U 1 1 6999E229 +P 11600 10850 +F 0 "X8" H 11650 10750 60 0000 C CNN +F 1 "5_and" H 11700 11000 60 0000 C CNN +F 2 "" H 11600 10850 60 0000 C CNN +F 3 "" H 11600 10850 60 0000 C CNN + 1 11600 10850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 6999E92E +P 7300 2850 +F 0 "U2" H 7300 2750 60 0000 C CNN +F 1 "d_inverter" H 7300 3000 60 0000 C CNN +F 2 "" H 7350 2800 60 0000 C CNN +F 3 "" H 7350 2800 60 0000 C CNN + 1 7300 2850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 6999F3F0 +P 8600 12650 +F 0 "U8" H 8600 12550 60 0000 C CNN +F 1 "d_inverter" H 8600 12800 60 0000 C CNN +F 2 "" H 8650 12600 60 0000 C CNN +F 3 "" H 8650 12600 60 0000 C CNN + 1 8600 12650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 6999F463 +P 7650 12650 +F 0 "U4" H 7650 12550 60 0000 C CNN +F 1 "d_inverter" H 7650 12800 60 0000 C CNN +F 2 "" H 7700 12600 60 0000 C CNN +F 3 "" H 7700 12600 60 0000 C CNN + 1 7650 12650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6999F9D7 +P 7700 12100 +F 0 "U5" H 7700 12000 60 0000 C CNN +F 1 "d_inverter" H 7700 12250 60 0000 C CNN +F 2 "" H 7750 12050 60 0000 C CNN +F 3 "" H 7750 12050 60 0000 C CNN + 1 7700 12100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 6999FA1D +P 8550 12100 +F 0 "U7" H 8550 12000 60 0000 C CNN +F 1 "d_inverter" H 8550 12250 60 0000 C CNN +F 2 "" H 8600 12050 60 0000 C CNN +F 3 "" H 8600 12050 60 0000 C CNN + 1 8550 12100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 699A059C +P 8400 11450 +F 0 "U6" H 8400 11350 60 0000 C CNN +F 1 "d_inverter" H 8400 11600 60 0000 C CNN +F 2 "" H 8450 11400 60 0000 C CNN +F 3 "" H 8450 11400 60 0000 C CNN + 1 8400 11450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 699A05E8 +P 7500 11450 +F 0 "U3" H 7500 11350 60 0000 C CNN +F 1 "d_inverter" H 7500 11600 60 0000 C CNN +F 2 "" H 7550 11400 60 0000 C CNN +F 3 "" H 7550 11400 60 0000 C CNN + 1 7500 11450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11100 3800 6050 3800 +Wire Wire Line + 11100 4800 6100 4800 +Wire Wire Line + 11100 5700 6150 5700 +Wire Wire Line + 11100 6700 6150 6700 +Wire Wire Line + 11150 7750 6000 7750 +Wire Wire Line + 11150 8750 6000 8750 +Wire Wire Line + 11150 9650 5950 9650 +Wire Wire Line + 11150 10650 5700 10650 +Wire Wire Line + 7600 2850 16700 2850 +Wire Wire Line + 10650 2850 10650 11050 +Wire Wire Line + 10650 11050 11150 11050 +Connection ~ 10650 2850 +Wire Wire Line + 11150 10050 10650 10050 +Connection ~ 10650 10050 +Wire Wire Line + 11150 9150 10650 9150 +Connection ~ 10650 9150 +Wire Wire Line + 11150 8150 10650 8150 +Connection ~ 10650 8150 +Wire Wire Line + 11100 7100 10650 7100 +Connection ~ 10650 7100 +Wire Wire Line + 11100 6100 10650 6100 +Connection ~ 10650 6100 +Wire Wire Line + 11100 5200 10650 5200 +Connection ~ 10650 5200 +Wire Wire Line + 11100 4200 10650 4200 +Connection ~ 10650 4200 +Wire Wire Line + 11150 8050 10450 8050 +Wire Wire Line + 10450 8050 10450 12650 +Wire Wire Line + 10450 12650 8900 12650 +Wire Wire Line + 11150 9050 10450 9050 +Connection ~ 10450 9050 +Wire Wire Line + 11150 9950 10450 9950 +Connection ~ 10450 9950 +Wire Wire Line + 11150 10950 10450 10950 +Connection ~ 10450 10950 +Wire Wire Line + 10100 4100 11100 4100 +Wire Wire Line + 10100 12400 10100 4100 +Wire Wire Line + 8150 12400 10100 12400 +Wire Wire Line + 7950 12650 8300 12650 +Wire Wire Line + 8150 12400 8150 12650 +Connection ~ 8150 12650 +Wire Wire Line + 7350 12650 6550 12650 +Wire Wire Line + 11100 5100 10100 5100 +Connection ~ 10100 5100 +Wire Wire Line + 11100 6000 10100 6000 +Connection ~ 10100 6000 +Wire Wire Line + 11100 7000 10100 7000 +Connection ~ 10100 7000 +Wire Wire Line + 11100 5900 9800 5900 +Wire Wire Line + 9800 5900 9800 12100 +Wire Wire Line + 9800 12100 8850 12100 +Wire Wire Line + 8000 12100 8250 12100 +Wire Wire Line + 11100 6900 9800 6900 +Connection ~ 9800 6900 +Wire Wire Line + 11150 10850 9800 10850 +Connection ~ 9800 10850 +Wire Wire Line + 11150 9850 9800 9850 +Connection ~ 9800 9850 +Wire Wire Line + 11100 4000 9400 4000 +Wire Wire Line + 9400 4000 9400 11700 +Wire Wire Line + 9400 11700 8150 11700 +Wire Wire Line + 8150 11700 8150 12100 +Connection ~ 8150 12100 +Wire Wire Line + 11100 5000 9400 5000 +Connection ~ 9400 5000 +Wire Wire Line + 11150 8950 9400 8950 +Connection ~ 9400 8950 +Wire Wire Line + 11150 7950 9400 7950 +Connection ~ 9400 7950 +Wire Wire Line + 11100 4900 9100 4900 +Wire Wire Line + 9100 4900 9100 11450 +Wire Wire Line + 9100 11450 8700 11450 +Wire Wire Line + 7800 11450 8100 11450 +Wire Wire Line + 11150 10750 9100 10750 +Connection ~ 9100 10750 +Wire Wire Line + 11150 8850 9100 8850 +Connection ~ 9100 8850 +Wire Wire Line + 11100 6800 9100 6800 +Connection ~ 9100 6800 +Wire Wire Line + 11100 3900 8650 3900 +Wire Wire Line + 8650 3900 8650 11050 +Wire Wire Line + 8650 11050 7950 11050 +Wire Wire Line + 7950 11050 7950 11450 +Connection ~ 7950 11450 +Wire Wire Line + 7400 12100 6900 12100 +Wire Wire Line + 7200 11450 6700 11450 +Wire Wire Line + 11100 5800 8650 5800 +Connection ~ 8650 5800 +Wire Wire Line + 11150 7850 8650 7850 +Connection ~ 8650 7850 +Wire Wire Line + 11150 9750 8650 9750 +Connection ~ 8650 9750 +$Comp +L nor8_enable U9 +U 1 1 6999E6D2 +P 12950 5700 +F 0 "U9" H 15800 7500 60 0000 C CNN +F 1 "nor8_enable" H 15800 7700 60 0000 C CNN +F 2 "" H 15800 7650 60 0000 C CNN +F 3 "" H 15800 7650 60 0000 C CNN + 1 12950 5700 + 1 0 0 1 +$EndComp +Wire Wire Line + 15100 6800 14700 6800 +Wire Wire Line + 14700 6800 14700 2850 +Wire Wire Line + 12100 4000 14400 4000 +Wire Wire Line + 14400 4000 14400 6900 +Wire Wire Line + 14400 6900 15100 6900 +Wire Wire Line + 14050 7000 15100 7000 +Wire Wire Line + 14050 7000 14050 5000 +Wire Wire Line + 14050 5000 12100 5000 +Wire Wire Line + 12100 5900 13750 5900 +Wire Wire Line + 13750 5900 13750 7100 +Wire Wire Line + 13750 7100 15100 7100 +Wire Wire Line + 13500 7200 15100 7200 +Wire Wire Line + 13500 7200 13500 6900 +Wire Wire Line + 13500 6900 12100 6900 +Wire Wire Line + 15100 7300 12600 7300 +Wire Wire Line + 12600 7300 12600 7950 +Wire Wire Line + 12600 7950 12150 7950 +Wire Wire Line + 15100 7400 12800 7400 +Wire Wire Line + 12800 7400 12800 8950 +Wire Wire Line + 12800 8950 12150 8950 +Wire Wire Line + 12150 9850 13250 9850 +Wire Wire Line + 13250 9850 13250 7500 +Wire Wire Line + 13250 7500 15100 7500 +Wire Wire Line + 15100 7600 13750 7600 +Wire Wire Line + 13750 7600 13750 10850 +Wire Wire Line + 13750 10850 12150 10850 +$Comp +L one_input_tristate_buffer U10 +U 1 1 6999F63E +P 14800 5200 +F 0 "U10" H 17650 7000 60 0000 C CNN +F 1 "one_input_tristate_buffer" H 17650 7200 60 0000 C CNN +F 2 "" H 17650 7150 60 0000 C CNN +F 3 "" H 17650 7150 60 0000 C CNN + 1 14800 5200 + 1 0 0 1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 6999F785 +P 18750 7100 +F 0 "U11" H 18750 7000 60 0000 C CNN +F 1 "d_inverter" H 18750 7250 60 0000 C CNN +F 2 "" H 18800 7050 60 0000 C CNN +F 3 "" H 18800 7050 60 0000 C CNN + 1 18750 7100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 18350 7100 18450 7100 +Wire Wire Line + 19050 7100 19250 7100 +Wire Wire Line + 16950 7100 16950 7600 +Wire Wire Line + 16500 7600 19250 7600 +Wire Wire Line + 16950 7000 16700 7000 +Wire Wire Line + 16700 7000 16700 2850 +Connection ~ 14700 2850 +Connection ~ 16950 7600 +Wire Wire Line + 7000 2850 6250 2850 +$Comp +L PORT U1 +U 11 1 699A06DA +P 6450 11450 +F 0 "U1" H 6500 11550 30 0000 C CNN +F 1 "PORT" H 6450 11450 30 0000 C CNN +F 2 "" H 6450 11450 60 0000 C CNN +F 3 "" H 6450 11450 60 0000 C CNN + 11 6450 11450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 699A082F +P 5450 10650 +F 0 "U1" H 5500 10750 30 0000 C CNN +F 1 "PORT" H 5450 10650 30 0000 C CNN +F 2 "" H 5450 10650 60 0000 C CNN +F 3 "" H 5450 10650 60 0000 C CNN + 12 5450 10650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 699A0872 +P 5700 9650 +F 0 "U1" H 5750 9750 30 0000 C CNN +F 1 "PORT" H 5700 9650 30 0000 C CNN +F 2 "" H 5700 9650 60 0000 C CNN +F 3 "" H 5700 9650 60 0000 C CNN + 13 5700 9650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 699A08B9 +P 5750 8750 +F 0 "U1" H 5800 8850 30 0000 C CNN +F 1 "PORT" H 5750 8750 30 0000 C CNN +F 2 "" H 5750 8750 60 0000 C CNN +F 3 "" H 5750 8750 60 0000 C CNN + 14 5750 8750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 699A08FA +P 19500 7600 +F 0 "U1" H 19550 7700 30 0000 C CNN +F 1 "PORT" H 19500 7600 30 0000 C CNN +F 2 "" H 19500 7600 60 0000 C CNN +F 3 "" H 19500 7600 60 0000 C CNN + 6 19500 7600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 699A09A9 +P 6000 2850 +F 0 "U1" H 6050 2950 30 0000 C CNN +F 1 "PORT" H 6000 2850 30 0000 C CNN +F 2 "" H 6000 2850 60 0000 C CNN +F 3 "" H 6000 2850 60 0000 C CNN + 7 6000 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 699A09F2 +P 5850 4800 +F 0 "U1" H 5900 4900 30 0000 C CNN +F 1 "PORT" H 5850 4800 30 0000 C CNN +F 2 "" H 5850 4800 60 0000 C CNN +F 3 "" H 5850 4800 60 0000 C CNN + 3 5850 4800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 699A0A41 +P 1550 3800 +F 0 "U1" H 1600 3900 30 0000 C CNN +F 1 "PORT" H 1550 3800 30 0000 C CNN +F 2 "" H 1550 3800 60 0000 C CNN +F 3 "" H 1550 3800 60 0000 C CNN + 8 1550 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 699A0A8E +P 6300 12650 +F 0 "U1" H 6350 12750 30 0000 C CNN +F 1 "PORT" H 6300 12650 30 0000 C CNN +F 2 "" H 6300 12650 60 0000 C CNN +F 3 "" H 6300 12650 60 0000 C CNN + 9 6300 12650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 699A0BD0 +P 6650 12100 +F 0 "U1" H 6700 12200 30 0000 C CNN +F 1 "PORT" H 6650 12100 30 0000 C CNN +F 2 "" H 6650 12100 60 0000 C CNN +F 3 "" H 6650 12100 60 0000 C CNN + 10 6650 12100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 699A0CAB +P 5750 7750 +F 0 "U1" H 5800 7850 30 0000 C CNN +F 1 "PORT" H 5750 7750 30 0000 C CNN +F 2 "" H 5750 7750 60 0000 C CNN +F 3 "" H 5750 7750 60 0000 C CNN + 15 5750 7750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 699A0D61 +P 1600 5200 +F 0 "U1" H 1650 5300 30 0000 C CNN +F 1 "PORT" H 1600 5200 30 0000 C CNN +F 2 "" H 1600 5200 60 0000 C CNN +F 3 "" H 1600 5200 60 0000 C CNN + 16 1600 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 699A0EAC +P 5800 3800 +F 0 "U1" H 5850 3900 30 0000 C CNN +F 1 "PORT" H 5800 3800 30 0000 C CNN +F 2 "" H 5800 3800 60 0000 C CNN +F 3 "" H 5800 3800 60 0000 C CNN + 4 5800 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 699A0FE2 +P 5900 5700 +F 0 "U1" H 5950 5800 30 0000 C CNN +F 1 "PORT" H 5900 5700 30 0000 C CNN +F 2 "" H 5900 5700 60 0000 C CNN +F 3 "" H 5900 5700 60 0000 C CNN + 2 5900 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 699A103D +P 5900 6700 +F 0 "U1" H 5950 6800 30 0000 C CNN +F 1 "PORT" H 5900 6700 30 0000 C CNN +F 2 "" H 5900 6700 60 0000 C CNN +F 3 "" H 5900 6700 60 0000 C CNN + 1 5900 6700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 699A109E +P 19500 7100 +F 0 "U1" H 19550 7200 30 0000 C CNN +F 1 "PORT" H 19500 7100 30 0000 C CNN +F 2 "" H 19500 7100 60 0000 C CNN +F 3 "" H 19500 7100 60 0000 C CNN + 5 19500 7100 + -1 0 0 1 +$EndComp +NoConn ~ 1850 5200 +NoConn ~ 1800 3800 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74S251/SN74S251.sub b/library/SubcircuitLibrary/SN74S251/SN74S251.sub new file mode 100644 index 000000000..472f1a4a6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/SN74S251.sub @@ -0,0 +1,55 @@ +* Subcircuit SN74S251 +.subckt SN74S251 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\sn74s251\sn74s251.cir +.include 5_and.sub +x1 net-_u1-pad4_ net-_u3-pad2_ net-_u5-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad8_ 5_and +x2 net-_u1-pad3_ net-_u6-pad2_ net-_u5-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad7_ 5_and +x3 net-_u1-pad2_ net-_u3-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad6_ 5_and +x4 net-_u1-pad1_ net-_u6-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u10-pad2_ net-_u9-pad5_ 5_and +x5 net-_u1-pad15_ net-_u3-pad2_ net-_u5-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad4_ 5_and +x6 net-_u1-pad14_ net-_u6-pad2_ net-_u5-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad3_ 5_and +x7 net-_u1-pad13_ net-_u3-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad2_ 5_and +x8 net-_u1-pad12_ net-_u6-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u10-pad2_ net-_u9-pad1_ 5_and +* u2 net-_u1-pad7_ net-_u10-pad2_ d_inverter +* u8 net-_u4-pad2_ net-_u8-pad2_ d_inverter +* u4 net-_u1-pad9_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad10_ net-_u5-pad2_ d_inverter +* u7 net-_u5-pad2_ net-_u7-pad2_ d_inverter +* u6 net-_u3-pad2_ net-_u6-pad2_ d_inverter +* u3 net-_u1-pad11_ net-_u3-pad2_ d_inverter +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u9-pad3_ net-_u9-pad4_ net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ net-_u10-pad2_ net-_u1-pad6_ nor8_enable +* u10 net-_u1-pad6_ net-_u10-pad2_ net-_u10-pad3_ one_input_tristate_buffer +* u11 net-_u10-pad3_ net-_u1-pad5_ d_inverter +a1 net-_u1-pad7_ net-_u10-pad2_ u2 +a2 net-_u4-pad2_ net-_u8-pad2_ u8 +a3 net-_u1-pad9_ net-_u4-pad2_ u4 +a4 net-_u1-pad10_ net-_u5-pad2_ u5 +a5 net-_u5-pad2_ net-_u7-pad2_ u7 +a6 net-_u3-pad2_ net-_u6-pad2_ u6 +a7 net-_u1-pad11_ net-_u3-pad2_ u3 +a8 [net-_u9-pad1_ net-_u9-pad2_ net-_u9-pad3_ net-_u9-pad4_ net-_u9-pad5_ net-_u9-pad6_ net-_u9-pad7_ net-_u9-pad8_ ] [net-_u10-pad2_ ] [net-_u1-pad6_ ] u9 +a9 [net-_u1-pad6_ ] [net-_u10-pad2_ ] [net-_u10-pad3_ ] u10 +a10 net-_u10-pad3_ net-_u1-pad5_ u11 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: nor8_enable, NgSpice Name: nor8_enable +.model u9 nor8_enable(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: one_input_tristate_buffer, NgSpice Name: one_input_tristate_buffer +.model u10 one_input_tristate_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 instance_id=1 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74S251 \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S251/SN74S251_Previous_Values.xml b/library/SubcircuitLibrary/SN74S251/SN74S251_Previous_Values.xml new file mode 100644 index 000000000..979386599 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/SN74S251_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsecd_inverterd_inverterd_inverterd_inverterd_inverterd_inverterd_inverternor8_enableone_input_tristate_bufferd_inverterC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_andC:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\5_and \ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74S251/analysis b/library/SubcircuitLibrary/SN74S251/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/SN74S251/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/ULN2804/D.lib b/library/SubcircuitLibrary/ULN2804/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2804/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/ULN2804/NPN.lib b/library/SubcircuitLibrary/ULN2804/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/ULN2804/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/ULN2804/ULN2804-cache.lib b/library/SubcircuitLibrary/ULN2804/ULN2804-cache.lib new file mode 100644 index 000000000..d900cc5d9 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2804/ULN2804-cache.lib @@ -0,0 +1,128 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS capacitor_polarised +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ULN2804/ULN2804.cir b/library/SubcircuitLibrary/ULN2804/ULN2804.cir new file mode 100644 index 000000000..5add33a31 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2804/ULN2804.cir @@ -0,0 +1,75 @@ +* C:\Users\chand\eSim\FOSSEE\eSim\library\SubcircuitLibrary\ULN2804\ULN2804.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/21/26 13:13:00 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_C1-Pad1_ Net-_Q1-Pad3_ GND eSim_NPN +Q1 Net-_C1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R2 Net-_Q1-Pad3_ Net-_Q1-Pad2_ 7.2k +R3 GND Net-_Q1-Pad3_ 3k +R1 Net-_Q1-Pad2_ Net-_R1-Pad2_ 10.5k +C1 Net-_C1-Pad1_ GND 15pF +D1 GND Net-_C1-Pad1_ eSim_Diode +R4 VCC Net-_C1-Pad1_ 1k +U1 Net-_R1-Pad2_ Net-_R9-Pad2_ Net-_R17-Pad2_ Net-_R25-Pad2_ Net-_R5-Pad2_ Net-_R12-Pad2_ Net-_R20-Pad2_ Net-_R28-Pad2_ GND VCC Net-_C8-Pad1_ Net-_C6-Pad1_ Net-_C4-Pad1_ Net-_C2-Pad1_ Net-_C7-Pad1_ Net-_C5-Pad1_ Net-_C3-Pad1_ Net-_C1-Pad1_ PORT +Q7 Net-_C3-Pad1_ Net-_Q5-Pad3_ GND eSim_NPN +Q5 Net-_C3-Pad1_ Net-_Q5-Pad2_ Net-_Q5-Pad3_ eSim_NPN +R10 Net-_Q5-Pad3_ Net-_Q5-Pad2_ 7.2k +R11 GND Net-_Q5-Pad3_ 3k +R9 Net-_Q5-Pad2_ Net-_R9-Pad2_ 10.5k +C3 Net-_C3-Pad1_ GND 15pF +D3 GND Net-_C3-Pad1_ eSim_Diode +R15 VCC Net-_C3-Pad1_ 1k +Q11 Net-_C5-Pad1_ Net-_Q11-Pad2_ GND eSim_NPN +Q9 Net-_C5-Pad1_ Net-_Q9-Pad2_ Net-_Q11-Pad2_ eSim_NPN +R18 Net-_Q11-Pad2_ Net-_Q9-Pad2_ 7.2k +R19 GND Net-_Q11-Pad2_ 3k +R17 Net-_Q9-Pad2_ Net-_R17-Pad2_ 10.5k +C5 Net-_C5-Pad1_ GND 15pF +D5 GND Net-_C5-Pad1_ eSim_Diode +R23 VCC Net-_C5-Pad1_ 1k +Q15 Net-_C7-Pad1_ Net-_Q13-Pad3_ GND eSim_NPN +Q13 Net-_C7-Pad1_ Net-_Q13-Pad2_ Net-_Q13-Pad3_ eSim_NPN +R26 Net-_Q13-Pad3_ Net-_Q13-Pad2_ 7.2k +R27 GND Net-_Q13-Pad3_ 3k +R25 Net-_Q13-Pad2_ Net-_R25-Pad2_ 10.5k +C7 Net-_C7-Pad1_ GND 15pF +D7 GND Net-_C7-Pad1_ eSim_Diode +R31 VCC Net-_C7-Pad1_ 1k +Q4 Net-_C2-Pad1_ Net-_Q3-Pad3_ GND eSim_NPN +Q3 Net-_C2-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +R6 Net-_Q3-Pad3_ Net-_Q3-Pad2_ 7.2k +R7 GND Net-_Q3-Pad3_ 3k +R5 Net-_Q3-Pad2_ Net-_R5-Pad2_ 10.5k +C2 Net-_C2-Pad1_ GND 15pF +D2 GND Net-_C2-Pad1_ eSim_Diode +R8 VCC Net-_C2-Pad1_ 1k +Q8 Net-_C4-Pad1_ Net-_Q6-Pad3_ GND eSim_NPN +Q6 Net-_C4-Pad1_ Net-_Q6-Pad2_ Net-_Q6-Pad3_ eSim_NPN +R13 Net-_Q6-Pad3_ Net-_Q6-Pad2_ 7.2k +R14 GND Net-_Q6-Pad3_ 3k +R12 Net-_Q6-Pad2_ Net-_R12-Pad2_ 10.5k +C4 Net-_C4-Pad1_ GND 15pF +D4 GND Net-_C4-Pad1_ eSim_Diode +R16 VCC Net-_C4-Pad1_ 1k +Q12 Net-_C6-Pad1_ Net-_Q10-Pad3_ GND eSim_NPN +Q10 Net-_C6-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R21 Net-_Q10-Pad3_ Net-_Q10-Pad2_ 7.2k +R22 GND Net-_Q10-Pad3_ 3k +R20 Net-_Q10-Pad2_ Net-_R20-Pad2_ 10.5k +C6 Net-_C6-Pad1_ GND 15pF +D6 GND Net-_C6-Pad1_ eSim_Diode +R24 VCC Net-_C6-Pad1_ 1k +Q16 Net-_C8-Pad1_ Net-_Q14-Pad3_ GND eSim_NPN +Q14 Net-_C8-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R29 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.2k +R30 GND Net-_Q14-Pad3_ 3k +R28 Net-_Q14-Pad2_ Net-_R28-Pad2_ 10.5k +C8 Net-_C8-Pad1_ GND 15pF +D8 GND Net-_C8-Pad1_ eSim_Diode +R32 VCC Net-_C8-Pad1_ 1k + +.end diff --git a/library/SubcircuitLibrary/ULN2804/ULN2804.cir.out b/library/SubcircuitLibrary/ULN2804/ULN2804.cir.out new file mode 100644 index 000000000..f0c531f04 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2804/ULN2804.cir.out @@ -0,0 +1,78 @@ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\uln2804\uln2804.cir + +.include D.lib +.include NPN.lib +q2 net-_c1-pad1_ net-_q1-pad3_ gnd Q2N2222 +q1 net-_c1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r2 net-_q1-pad3_ net-_q1-pad2_ 7.2k +r3 gnd net-_q1-pad3_ 3k +r1 net-_q1-pad2_ net-_r1-pad2_ 10.5k +c1 net-_c1-pad1_ gnd 15pf +d1 gnd net-_c1-pad1_ 1N4148 +r4 vcc net-_c1-pad1_ 1k +* u1 net-_r1-pad2_ net-_r9-pad2_ net-_r17-pad2_ net-_r25-pad2_ net-_r5-pad2_ net-_r12-pad2_ net-_r20-pad2_ net-_r28-pad2_ gnd vcc net-_c8-pad1_ net-_c6-pad1_ net-_c4-pad1_ net-_c2-pad1_ net-_c7-pad1_ net-_c5-pad1_ net-_c3-pad1_ net-_c1-pad1_ port +q7 net-_c3-pad1_ net-_q5-pad3_ gnd Q2N2222 +q5 net-_c3-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222 +r10 net-_q5-pad3_ net-_q5-pad2_ 7.2k +r11 gnd net-_q5-pad3_ 3k +r9 net-_q5-pad2_ net-_r9-pad2_ 10.5k +c3 net-_c3-pad1_ gnd 15pf +d3 gnd net-_c3-pad1_ 1N4148 +r15 vcc net-_c3-pad1_ 1k +q11 net-_c5-pad1_ net-_q11-pad2_ gnd Q2N2222 +q9 net-_c5-pad1_ net-_q9-pad2_ net-_q11-pad2_ Q2N2222 +r18 net-_q11-pad2_ net-_q9-pad2_ 7.2k +r19 gnd net-_q11-pad2_ 3k +r17 net-_q9-pad2_ net-_r17-pad2_ 10.5k +c5 net-_c5-pad1_ gnd 15pf +d5 gnd net-_c5-pad1_ 1N4148 +r23 vcc net-_c5-pad1_ 1k +q15 net-_c7-pad1_ net-_q13-pad3_ gnd Q2N2222 +q13 net-_c7-pad1_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222 +r26 net-_q13-pad3_ net-_q13-pad2_ 7.2k +r27 gnd net-_q13-pad3_ 3k +r25 net-_q13-pad2_ net-_r25-pad2_ 10.5k +c7 net-_c7-pad1_ gnd 15pf +d7 gnd net-_c7-pad1_ 1N4148 +r31 vcc net-_c7-pad1_ 1k +q4 net-_c2-pad1_ net-_q3-pad3_ gnd Q2N2222 +q3 net-_c2-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +r6 net-_q3-pad3_ net-_q3-pad2_ 7.2k +r7 gnd net-_q3-pad3_ 3k +r5 net-_q3-pad2_ net-_r5-pad2_ 10.5k +c2 net-_c2-pad1_ gnd 15pf +d2 gnd net-_c2-pad1_ 1N4148 +r8 vcc net-_c2-pad1_ 1k +q8 net-_c4-pad1_ net-_q6-pad3_ gnd Q2N2222 +q6 net-_c4-pad1_ net-_q6-pad2_ net-_q6-pad3_ Q2N2222 +r13 net-_q6-pad3_ net-_q6-pad2_ 7.2k +r14 gnd net-_q6-pad3_ 3k +r12 net-_q6-pad2_ net-_r12-pad2_ 10.5k +c4 net-_c4-pad1_ gnd 15pf +d4 gnd net-_c4-pad1_ 1N4148 +r16 vcc net-_c4-pad1_ 1k +q12 net-_c6-pad1_ net-_q10-pad3_ gnd Q2N2222 +q10 net-_c6-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +r21 net-_q10-pad3_ net-_q10-pad2_ 7.2k +r22 gnd net-_q10-pad3_ 3k +r20 net-_q10-pad2_ net-_r20-pad2_ 10.5k +c6 net-_c6-pad1_ gnd 15pf +d6 gnd net-_c6-pad1_ 1N4148 +r24 vcc net-_c6-pad1_ 1k +q16 net-_c8-pad1_ net-_q14-pad3_ gnd Q2N2222 +q14 net-_c8-pad1_ net-_q14-pad2_ net-_q14-pad3_ Q2N2222 +r29 net-_q14-pad3_ net-_q14-pad2_ 7.2k +r30 gnd net-_q14-pad3_ 3k +r28 net-_q14-pad2_ net-_r28-pad2_ 10.5k +c8 net-_c8-pad1_ gnd 15pf +d8 gnd net-_c8-pad1_ 1N4148 +r32 vcc net-_c8-pad1_ 1k +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ULN2804/ULN2804.pro b/library/SubcircuitLibrary/ULN2804/ULN2804.pro new file mode 100644 index 000000000..e27a398be --- /dev/null +++ b/library/SubcircuitLibrary/ULN2804/ULN2804.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/ULN2804/ULN2804.sch b/library/SubcircuitLibrary/ULN2804/ULN2804.sch new file mode 100644 index 000000000..2afcdd071 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2804/ULN2804.sch @@ -0,0 +1,1430 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q2 +U 1 1 69993468 +P 7050 5650 +F 0 "Q2" H 6950 5700 50 0000 R CNN +F 1 "eSim_NPN" H 7000 5800 50 0000 R CNN +F 2 "" H 7250 5750 29 0000 C CNN +F 3 "" H 7050 5650 60 0000 C CNN + 1 7050 5650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 69994EE6 +P 6150 5150 +F 0 "Q1" H 6050 5200 50 0000 R CNN +F 1 "eSim_NPN" H 6100 5300 50 0000 R CNN +F 2 "" H 6350 5250 29 0000 C CNN +F 3 "" H 6150 5150 60 0000 C CNN + 1 6150 5150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 69994F60 +P 5650 5900 +F 0 "R2" H 5700 6030 50 0000 C CNN +F 1 "7.2k" H 5700 5850 50 0000 C CNN +F 2 "" H 5700 5880 30 0000 C CNN +F 3 "" V 5700 5950 30 0000 C CNN + 1 5650 5900 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 69994FD3 +P 5650 6350 +F 0 "R3" H 5700 6480 50 0000 C CNN +F 1 "3k" H 5700 6300 50 0000 C CNN +F 2 "" H 5700 6330 30 0000 C CNN +F 3 "" V 5700 6400 30 0000 C CNN + 1 5650 6350 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 69995054 +P 5650 4850 +F 0 "R1" H 5700 4980 50 0000 C CNN +F 1 "10.5k" H 5700 4800 50 0000 C CNN +F 2 "" H 5700 4830 30 0000 C CNN +F 3 "" V 5700 4900 30 0000 C CNN + 1 5650 4850 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C1 +U 1 1 6999523F +P 7500 5150 +F 0 "C1" H 7525 5250 50 0000 L CNN +F 1 "15pF" H 7525 5050 50 0000 L CNN +F 2 "" H 7500 5150 50 0001 C CNN +F 3 "" H 7500 5150 50 0001 C CNN + 1 7500 5150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 6999526D +P 8000 5150 +F 0 "D1" H 8000 5250 50 0000 C CNN +F 1 "eSim_Diode" H 8000 5050 50 0000 C CNN +F 2 "" H 8000 5150 60 0000 C CNN +F 3 "" H 8000 5150 60 0000 C CNN + 1 8000 5150 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 6999529F +P 7350 4350 +F 0 "R4" H 7400 4480 50 0000 C CNN +F 1 "1k" H 7400 4300 50 0000 C CNN +F 2 "" H 7400 4330 30 0000 C CNN +F 3 "" V 7400 4400 30 0000 C CNN + 1 7350 4350 + 0 -1 1 0 +$EndComp +Text GLabel 7500 5550 3 60 Input ~ 0 +GND +Text GLabel 8000 5600 3 60 Input ~ 0 +GND +Text GLabel 6350 6700 3 60 Input ~ 0 +GND +$Comp +L PORT U1 +U 9 1 699956C6 +P 1550 1650 +F 0 "U1" H 1600 1750 30 0000 C CNN +F 1 "PORT" H 1550 1650 30 0000 C CNN +F 2 "" H 1550 1650 60 0000 C CNN +F 3 "" H 1550 1650 60 0000 C CNN + 9 1550 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 69995703 +P 1600 2150 +F 0 "U1" H 1650 2250 30 0000 C CNN +F 1 "PORT" H 1600 2150 30 0000 C CNN +F 2 "" H 1600 2150 60 0000 C CNN +F 3 "" H 1600 2150 60 0000 C CNN + 10 1600 2150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6999572C +P 18500 8600 +F 0 "U1" H 18550 8700 30 0000 C CNN +F 1 "PORT" H 18500 8600 30 0000 C CNN +F 2 "" H 18500 8600 60 0000 C CNN +F 3 "" H 18500 8600 60 0000 C CNN + 11 18500 8600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 17 1 6999577F +P 11800 4900 +F 0 "U1" H 11850 5000 30 0000 C CNN +F 1 "PORT" H 11800 4900 30 0000 C CNN +F 2 "" H 11800 4900 60 0000 C CNN +F 3 "" H 11800 4900 60 0000 C CNN + 17 11800 4900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 699957A2 +P 15100 8500 +F 0 "U1" H 15150 8600 30 0000 C CNN +F 1 "PORT" H 15100 8500 30 0000 C CNN +F 2 "" H 15100 8500 60 0000 C CNN +F 3 "" H 15100 8500 60 0000 C CNN + 12 15100 8500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 16 1 699957E1 +P 15000 4800 +F 0 "U1" H 15050 4900 30 0000 C CNN +F 1 "PORT" H 15000 4800 30 0000 C CNN +F 2 "" H 15000 4800 60 0000 C CNN +F 3 "" H 15000 4800 60 0000 C CNN + 16 15000 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 69995808 +P 11900 8600 +F 0 "U1" H 11950 8700 30 0000 C CNN +F 1 "PORT" H 11900 8600 30 0000 C CNN +F 2 "" H 11900 8600 60 0000 C CNN +F 3 "" H 11900 8600 60 0000 C CNN + 13 11900 8600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 6999582E +P 9000 4300 +F 0 "U1" H 9050 4400 30 0000 C CNN +F 1 "PORT" H 9000 4300 30 0000 C CNN +F 2 "" H 9000 4300 60 0000 C CNN +F 3 "" H 9000 4300 60 0000 C CNN + 2 9000 4300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 18 1 69995855 +P 8400 4800 +F 0 "U1" H 8450 4900 30 0000 C CNN +F 1 "PORT" H 8400 4800 30 0000 C CNN +F 2 "" H 8400 4800 60 0000 C CNN +F 3 "" H 8400 4800 60 0000 C CNN + 18 8400 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 6999587D +P 18400 4900 +F 0 "U1" H 18450 5000 30 0000 C CNN +F 1 "PORT" H 18400 4900 30 0000 C CNN +F 2 "" H 18400 4900 60 0000 C CNN +F 3 "" H 18400 4900 60 0000 C CNN + 15 18400 4900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 699958A6 +P 5700 7900 +F 0 "U1" H 5750 8000 30 0000 C CNN +F 1 "PORT" H 5700 7900 30 0000 C CNN +F 2 "" H 5700 7900 60 0000 C CNN +F 3 "" H 5700 7900 60 0000 C CNN + 5 5700 7900 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 699958D0 +P 8500 8500 +F 0 "U1" H 8550 8600 30 0000 C CNN +F 1 "PORT" H 8500 8500 30 0000 C CNN +F 2 "" H 8500 8500 60 0000 C CNN +F 3 "" H 8500 8500 60 0000 C CNN + 14 8500 8500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 699958FB +P 9100 8000 +F 0 "U1" H 9150 8100 30 0000 C CNN +F 1 "PORT" H 9100 8000 30 0000 C CNN +F 2 "" H 9100 8000 60 0000 C CNN +F 3 "" H 9100 8000 60 0000 C CNN + 6 9100 8000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 69995970 +P 12300 7900 +F 0 "U1" H 12350 8000 30 0000 C CNN +F 1 "PORT" H 12300 7900 30 0000 C CNN +F 2 "" H 12300 7900 60 0000 C CNN +F 3 "" H 12300 7900 60 0000 C CNN + 7 12300 7900 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 699959D3 +P 15700 8000 +F 0 "U1" H 15750 8100 30 0000 C CNN +F 1 "PORT" H 15700 8000 30 0000 C CNN +F 2 "" H 15700 8000 60 0000 C CNN +F 3 "" H 15700 8000 60 0000 C CNN + 8 15700 8000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 69995A34 +P 12200 4200 +F 0 "U1" H 12250 4300 30 0000 C CNN +F 1 "PORT" H 12200 4200 30 0000 C CNN +F 2 "" H 12200 4200 60 0000 C CNN +F 3 "" H 12200 4200 60 0000 C CNN + 3 12200 4200 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 69995A91 +P 15600 4300 +F 0 "U1" H 15650 4400 30 0000 C CNN +F 1 "PORT" H 15600 4300 30 0000 C CNN +F 2 "" H 15600 4300 60 0000 C CNN +F 3 "" H 15600 4300 60 0000 C CNN + 4 15600 4300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 69995AEA +P 5600 4200 +F 0 "U1" H 5650 4300 30 0000 C CNN +F 1 "PORT" H 5600 4200 30 0000 C CNN +F 2 "" H 5600 4200 60 0000 C CNN +F 3 "" H 5600 4200 60 0000 C CNN + 1 5600 4200 + 0 1 1 0 +$EndComp +Text GLabel 1950 2150 2 60 Input ~ 0 +VCC +Text GLabel 7300 3950 1 60 Input ~ 0 +VCC +Wire Wire Line + 6250 5350 6250 5650 +Wire Wire Line + 6250 5650 6850 5650 +Wire Wire Line + 6250 4950 6250 4800 +Connection ~ 7150 4800 +Wire Wire Line + 7150 5850 7150 6550 +Wire Wire Line + 5600 4950 5600 5700 +Connection ~ 5600 5150 +Wire Wire Line + 5600 6000 5600 6150 +Wire Wire Line + 5600 6450 5600 6550 +Wire Wire Line + 5600 6550 7150 6550 +Wire Wire Line + 5600 6100 6450 6100 +Wire Wire Line + 6450 6100 6450 5650 +Connection ~ 6450 5650 +Connection ~ 5600 6100 +Wire Wire Line + 7300 4550 7300 4800 +Wire Wire Line + 8000 5000 8000 4800 +Wire Wire Line + 7500 5000 7500 4800 +Connection ~ 7500 4800 +Wire Wire Line + 5600 4650 5600 4450 +Wire Wire Line + 5600 5150 5950 5150 +Wire Wire Line + 7500 5300 7500 5550 +Wire Wire Line + 8000 5300 8000 5600 +Wire Wire Line + 7300 4250 7300 3950 +Wire Wire Line + 6350 6700 6350 6550 +Connection ~ 6350 6550 +Wire Wire Line + 7150 4800 7150 5450 +Wire Wire Line + 6250 4800 8150 4800 +Connection ~ 7300 4800 +Connection ~ 8000 4800 +Wire Wire Line + 1850 2150 1950 2150 +$Comp +L eSim_NPN Q7 +U 1 1 699A89B0 +P 10450 5750 +F 0 "Q7" H 10350 5800 50 0000 R CNN +F 1 "eSim_NPN" H 10400 5900 50 0000 R CNN +F 2 "" H 10650 5850 29 0000 C CNN +F 3 "" H 10450 5750 60 0000 C CNN + 1 10450 5750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 699A89B6 +P 9550 5250 +F 0 "Q5" H 9450 5300 50 0000 R CNN +F 1 "eSim_NPN" H 9500 5400 50 0000 R CNN +F 2 "" H 9750 5350 29 0000 C CNN +F 3 "" H 9550 5250 60 0000 C CNN + 1 9550 5250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R10 +U 1 1 699A89BC +P 9050 6000 +F 0 "R10" H 9100 6130 50 0000 C CNN +F 1 "7.2k" H 9100 5950 50 0000 C CNN +F 2 "" H 9100 5980 30 0000 C CNN +F 3 "" V 9100 6050 30 0000 C CNN + 1 9050 6000 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 699A89C2 +P 9050 6450 +F 0 "R11" H 9100 6580 50 0000 C CNN +F 1 "3k" H 9100 6400 50 0000 C CNN +F 2 "" H 9100 6430 30 0000 C CNN +F 3 "" V 9100 6500 30 0000 C CNN + 1 9050 6450 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R9 +U 1 1 699A89C8 +P 9050 4950 +F 0 "R9" H 9100 5080 50 0000 C CNN +F 1 "10.5k" H 9100 4900 50 0000 C CNN +F 2 "" H 9100 4930 30 0000 C CNN +F 3 "" V 9100 5000 30 0000 C CNN + 1 9050 4950 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C3 +U 1 1 699A89CE +P 10900 5250 +F 0 "C3" H 10925 5350 50 0000 L CNN +F 1 "15pF" H 10925 5150 50 0000 L CNN +F 2 "" H 10900 5250 50 0001 C CNN +F 3 "" H 10900 5250 50 0001 C CNN + 1 10900 5250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 699A89D4 +P 11400 5250 +F 0 "D3" H 11400 5350 50 0000 C CNN +F 1 "eSim_Diode" H 11400 5150 50 0000 C CNN +F 2 "" H 11400 5250 60 0000 C CNN +F 3 "" H 11400 5250 60 0000 C CNN + 1 11400 5250 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R15 +U 1 1 699A89DA +P 10750 4450 +F 0 "R15" H 10800 4580 50 0000 C CNN +F 1 "1k" H 10800 4400 50 0000 C CNN +F 2 "" H 10800 4430 30 0000 C CNN +F 3 "" V 10800 4500 30 0000 C CNN + 1 10750 4450 + 0 -1 1 0 +$EndComp +Text GLabel 10900 5650 3 60 Input ~ 0 +GND +Text GLabel 11400 5700 3 60 Input ~ 0 +GND +Text GLabel 9750 6800 3 60 Input ~ 0 +GND +Text GLabel 10700 4050 1 60 Input ~ 0 +VCC +Wire Wire Line + 9650 5450 9650 5750 +Wire Wire Line + 9650 5750 10250 5750 +Wire Wire Line + 9650 5050 9650 4900 +Connection ~ 10550 4900 +Wire Wire Line + 10550 5950 10550 6650 +Wire Wire Line + 9000 5050 9000 5800 +Connection ~ 9000 5250 +Wire Wire Line + 9000 6100 9000 6250 +Wire Wire Line + 9000 6550 9000 6650 +Wire Wire Line + 9000 6650 10550 6650 +Wire Wire Line + 9000 6200 9850 6200 +Wire Wire Line + 9850 6200 9850 5750 +Connection ~ 9850 5750 +Connection ~ 9000 6200 +Wire Wire Line + 10700 4650 10700 4900 +Wire Wire Line + 11400 5100 11400 4900 +Wire Wire Line + 10900 5100 10900 4900 +Connection ~ 10900 4900 +Wire Wire Line + 9000 4750 9000 4550 +Wire Wire Line + 9000 5250 9350 5250 +Wire Wire Line + 10900 5400 10900 5650 +Wire Wire Line + 11400 5400 11400 5700 +Wire Wire Line + 10700 4350 10700 4050 +Wire Wire Line + 9750 6800 9750 6650 +Connection ~ 9750 6650 +Wire Wire Line + 10550 4900 10550 5550 +Wire Wire Line + 9650 4900 11550 4900 +Connection ~ 10700 4900 +Connection ~ 11400 4900 +$Comp +L eSim_NPN Q11 +U 1 1 699A8BB9 +P 13650 5650 +F 0 "Q11" H 13550 5700 50 0000 R CNN +F 1 "eSim_NPN" H 13600 5800 50 0000 R CNN +F 2 "" H 13850 5750 29 0000 C CNN +F 3 "" H 13650 5650 60 0000 C CNN + 1 13650 5650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 699A8BBF +P 12750 5150 +F 0 "Q9" H 12650 5200 50 0000 R CNN +F 1 "eSim_NPN" H 12700 5300 50 0000 R CNN +F 2 "" H 12950 5250 29 0000 C CNN +F 3 "" H 12750 5150 60 0000 C CNN + 1 12750 5150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R18 +U 1 1 699A8BC5 +P 12250 5900 +F 0 "R18" H 12300 6030 50 0000 C CNN +F 1 "7.2k" H 12300 5850 50 0000 C CNN +F 2 "" H 12300 5880 30 0000 C CNN +F 3 "" V 12300 5950 30 0000 C CNN + 1 12250 5900 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R19 +U 1 1 699A8BCB +P 12250 6350 +F 0 "R19" H 12300 6480 50 0000 C CNN +F 1 "3k" H 12300 6300 50 0000 C CNN +F 2 "" H 12300 6330 30 0000 C CNN +F 3 "" V 12300 6400 30 0000 C CNN + 1 12250 6350 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R17 +U 1 1 699A8BD1 +P 12250 4850 +F 0 "R17" H 12300 4980 50 0000 C CNN +F 1 "10.5k" H 12300 4800 50 0000 C CNN +F 2 "" H 12300 4830 30 0000 C CNN +F 3 "" V 12300 4900 30 0000 C CNN + 1 12250 4850 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C5 +U 1 1 699A8BD7 +P 14100 5150 +F 0 "C5" H 14125 5250 50 0000 L CNN +F 1 "15pF" H 14125 5050 50 0000 L CNN +F 2 "" H 14100 5150 50 0001 C CNN +F 3 "" H 14100 5150 50 0001 C CNN + 1 14100 5150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 699A8BDD +P 14600 5150 +F 0 "D5" H 14600 5250 50 0000 C CNN +F 1 "eSim_Diode" H 14600 5050 50 0000 C CNN +F 2 "" H 14600 5150 60 0000 C CNN +F 3 "" H 14600 5150 60 0000 C CNN + 1 14600 5150 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R23 +U 1 1 699A8BE3 +P 13950 4350 +F 0 "R23" H 14000 4480 50 0000 C CNN +F 1 "1k" H 14000 4300 50 0000 C CNN +F 2 "" H 14000 4330 30 0000 C CNN +F 3 "" V 14000 4400 30 0000 C CNN + 1 13950 4350 + 0 -1 1 0 +$EndComp +Text GLabel 14100 5550 3 60 Input ~ 0 +GND +Text GLabel 14600 5600 3 60 Input ~ 0 +GND +Text GLabel 12950 6700 3 60 Input ~ 0 +GND +Text GLabel 13900 3950 1 60 Input ~ 0 +VCC +Wire Wire Line + 12850 5350 12850 5650 +Wire Wire Line + 12850 5650 13450 5650 +Wire Wire Line + 12850 4950 12850 4800 +Connection ~ 13750 4800 +Wire Wire Line + 13750 5850 13750 6550 +Wire Wire Line + 12200 4950 12200 5700 +Connection ~ 12200 5150 +Wire Wire Line + 12200 6000 12200 6150 +Wire Wire Line + 12200 6450 12200 6550 +Wire Wire Line + 12200 6550 13750 6550 +Wire Wire Line + 12200 6100 13050 6100 +Wire Wire Line + 13050 6100 13050 5650 +Connection ~ 13050 5650 +Connection ~ 12200 6100 +Wire Wire Line + 13900 4550 13900 4800 +Wire Wire Line + 14600 5000 14600 4800 +Wire Wire Line + 14100 5000 14100 4800 +Connection ~ 14100 4800 +Wire Wire Line + 12200 4650 12200 4450 +Wire Wire Line + 12200 5150 12550 5150 +Wire Wire Line + 14100 5300 14100 5550 +Wire Wire Line + 14600 5300 14600 5600 +Wire Wire Line + 13900 4250 13900 3950 +Wire Wire Line + 12950 6700 12950 6550 +Connection ~ 12950 6550 +Wire Wire Line + 13750 4800 13750 5450 +Wire Wire Line + 12850 4800 14750 4800 +Connection ~ 13900 4800 +Connection ~ 14600 4800 +$Comp +L eSim_NPN Q15 +U 1 1 699A8C0A +P 17050 5750 +F 0 "Q15" H 16950 5800 50 0000 R CNN +F 1 "eSim_NPN" H 17000 5900 50 0000 R CNN +F 2 "" H 17250 5850 29 0000 C CNN +F 3 "" H 17050 5750 60 0000 C CNN + 1 17050 5750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 699A8C10 +P 16150 5250 +F 0 "Q13" H 16050 5300 50 0000 R CNN +F 1 "eSim_NPN" H 16100 5400 50 0000 R CNN +F 2 "" H 16350 5350 29 0000 C CNN +F 3 "" H 16150 5250 60 0000 C CNN + 1 16150 5250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R26 +U 1 1 699A8C16 +P 15650 6000 +F 0 "R26" H 15700 6130 50 0000 C CNN +F 1 "7.2k" H 15700 5950 50 0000 C CNN +F 2 "" H 15700 5980 30 0000 C CNN +F 3 "" V 15700 6050 30 0000 C CNN + 1 15650 6000 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R27 +U 1 1 699A8C1C +P 15650 6450 +F 0 "R27" H 15700 6580 50 0000 C CNN +F 1 "3k" H 15700 6400 50 0000 C CNN +F 2 "" H 15700 6430 30 0000 C CNN +F 3 "" V 15700 6500 30 0000 C CNN + 1 15650 6450 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R25 +U 1 1 699A8C22 +P 15650 4950 +F 0 "R25" H 15700 5080 50 0000 C CNN +F 1 "10.5k" H 15700 4900 50 0000 C CNN +F 2 "" H 15700 4930 30 0000 C CNN +F 3 "" V 15700 5000 30 0000 C CNN + 1 15650 4950 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C7 +U 1 1 699A8C28 +P 17500 5250 +F 0 "C7" H 17525 5350 50 0000 L CNN +F 1 "15pF" H 17525 5150 50 0000 L CNN +F 2 "" H 17500 5250 50 0001 C CNN +F 3 "" H 17500 5250 50 0001 C CNN + 1 17500 5250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 699A8C2E +P 18000 5250 +F 0 "D7" H 18000 5350 50 0000 C CNN +F 1 "eSim_Diode" H 18000 5150 50 0000 C CNN +F 2 "" H 18000 5250 60 0000 C CNN +F 3 "" H 18000 5250 60 0000 C CNN + 1 18000 5250 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R31 +U 1 1 699A8C34 +P 17350 4450 +F 0 "R31" H 17400 4580 50 0000 C CNN +F 1 "1k" H 17400 4400 50 0000 C CNN +F 2 "" H 17400 4430 30 0000 C CNN +F 3 "" V 17400 4500 30 0000 C CNN + 1 17350 4450 + 0 -1 1 0 +$EndComp +Text GLabel 17500 5650 3 60 Input ~ 0 +GND +Text GLabel 18000 5700 3 60 Input ~ 0 +GND +Text GLabel 16350 6800 3 60 Input ~ 0 +GND +Text GLabel 17300 4050 1 60 Input ~ 0 +VCC +Wire Wire Line + 16250 5450 16250 5750 +Wire Wire Line + 16250 5750 16850 5750 +Wire Wire Line + 16250 5050 16250 4900 +Connection ~ 17150 4900 +Wire Wire Line + 17150 5950 17150 6650 +Wire Wire Line + 15600 5050 15600 5800 +Connection ~ 15600 5250 +Wire Wire Line + 15600 6100 15600 6250 +Wire Wire Line + 15600 6550 15600 6650 +Wire Wire Line + 15600 6650 17150 6650 +Wire Wire Line + 15600 6200 16450 6200 +Wire Wire Line + 16450 6200 16450 5750 +Connection ~ 16450 5750 +Connection ~ 15600 6200 +Wire Wire Line + 17300 4650 17300 4900 +Wire Wire Line + 18000 5100 18000 4900 +Wire Wire Line + 17500 5100 17500 4900 +Connection ~ 17500 4900 +Wire Wire Line + 15600 4750 15600 4550 +Wire Wire Line + 15600 5250 15950 5250 +Wire Wire Line + 17500 5400 17500 5650 +Wire Wire Line + 18000 5400 18000 5700 +Wire Wire Line + 17300 4350 17300 4050 +Wire Wire Line + 16350 6800 16350 6650 +Connection ~ 16350 6650 +Wire Wire Line + 17150 4900 17150 5550 +Wire Wire Line + 16250 4900 18150 4900 +Connection ~ 17300 4900 +Connection ~ 18000 4900 +$Comp +L eSim_NPN Q4 +U 1 1 699A90B5 +P 7150 9350 +F 0 "Q4" H 7050 9400 50 0000 R CNN +F 1 "eSim_NPN" H 7100 9500 50 0000 R CNN +F 2 "" H 7350 9450 29 0000 C CNN +F 3 "" H 7150 9350 60 0000 C CNN + 1 7150 9350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 699A90BB +P 6250 8850 +F 0 "Q3" H 6150 8900 50 0000 R CNN +F 1 "eSim_NPN" H 6200 9000 50 0000 R CNN +F 2 "" H 6450 8950 29 0000 C CNN +F 3 "" H 6250 8850 60 0000 C CNN + 1 6250 8850 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 699A90C1 +P 5750 9600 +F 0 "R6" H 5800 9730 50 0000 C CNN +F 1 "7.2k" H 5800 9550 50 0000 C CNN +F 2 "" H 5800 9580 30 0000 C CNN +F 3 "" V 5800 9650 30 0000 C CNN + 1 5750 9600 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 699A90C7 +P 5750 10050 +F 0 "R7" H 5800 10180 50 0000 C CNN +F 1 "3k" H 5800 10000 50 0000 C CNN +F 2 "" H 5800 10030 30 0000 C CNN +F 3 "" V 5800 10100 30 0000 C CNN + 1 5750 10050 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 699A90CD +P 5750 8550 +F 0 "R5" H 5800 8680 50 0000 C CNN +F 1 "10.5k" H 5800 8500 50 0000 C CNN +F 2 "" H 5800 8530 30 0000 C CNN +F 3 "" V 5800 8600 30 0000 C CNN + 1 5750 8550 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C2 +U 1 1 699A90D3 +P 7600 8850 +F 0 "C2" H 7625 8950 50 0000 L CNN +F 1 "15pF" H 7625 8750 50 0000 L CNN +F 2 "" H 7600 8850 50 0001 C CNN +F 3 "" H 7600 8850 50 0001 C CNN + 1 7600 8850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 699A90D9 +P 8100 8850 +F 0 "D2" H 8100 8950 50 0000 C CNN +F 1 "eSim_Diode" H 8100 8750 50 0000 C CNN +F 2 "" H 8100 8850 60 0000 C CNN +F 3 "" H 8100 8850 60 0000 C CNN + 1 8100 8850 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 699A90DF +P 7450 8050 +F 0 "R8" H 7500 8180 50 0000 C CNN +F 1 "1k" H 7500 8000 50 0000 C CNN +F 2 "" H 7500 8030 30 0000 C CNN +F 3 "" V 7500 8100 30 0000 C CNN + 1 7450 8050 + 0 -1 1 0 +$EndComp +Text GLabel 7600 9250 3 60 Input ~ 0 +GND +Text GLabel 8100 9300 3 60 Input ~ 0 +GND +Text GLabel 6450 10400 3 60 Input ~ 0 +GND +Text GLabel 7400 7650 1 60 Input ~ 0 +VCC +Wire Wire Line + 6350 9050 6350 9350 +Wire Wire Line + 6350 9350 6950 9350 +Wire Wire Line + 6350 8650 6350 8500 +Connection ~ 7250 8500 +Wire Wire Line + 7250 9550 7250 10250 +Wire Wire Line + 5700 8650 5700 9400 +Connection ~ 5700 8850 +Wire Wire Line + 5700 9700 5700 9850 +Wire Wire Line + 5700 10150 5700 10250 +Wire Wire Line + 5700 10250 7250 10250 +Wire Wire Line + 5700 9800 6550 9800 +Wire Wire Line + 6550 9800 6550 9350 +Connection ~ 6550 9350 +Connection ~ 5700 9800 +Wire Wire Line + 7400 8250 7400 8500 +Wire Wire Line + 8100 8700 8100 8500 +Wire Wire Line + 7600 8700 7600 8500 +Connection ~ 7600 8500 +Wire Wire Line + 5700 8350 5700 8150 +Wire Wire Line + 5700 8850 6050 8850 +Wire Wire Line + 7600 9000 7600 9250 +Wire Wire Line + 8100 9000 8100 9300 +Wire Wire Line + 7400 7950 7400 7650 +Wire Wire Line + 6450 10400 6450 10250 +Connection ~ 6450 10250 +Wire Wire Line + 7250 8500 7250 9150 +Wire Wire Line + 6350 8500 8250 8500 +Connection ~ 7400 8500 +Connection ~ 8100 8500 +$Comp +L eSim_NPN Q8 +U 1 1 699A9106 +P 10550 9450 +F 0 "Q8" H 10450 9500 50 0000 R CNN +F 1 "eSim_NPN" H 10500 9600 50 0000 R CNN +F 2 "" H 10750 9550 29 0000 C CNN +F 3 "" H 10550 9450 60 0000 C CNN + 1 10550 9450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 699A910C +P 9650 8950 +F 0 "Q6" H 9550 9000 50 0000 R CNN +F 1 "eSim_NPN" H 9600 9100 50 0000 R CNN +F 2 "" H 9850 9050 29 0000 C CNN +F 3 "" H 9650 8950 60 0000 C CNN + 1 9650 8950 + 1 0 0 -1 +$EndComp +$Comp +L resistor R13 +U 1 1 699A9112 +P 9150 9700 +F 0 "R13" H 9200 9830 50 0000 C CNN +F 1 "7.2k" H 9200 9650 50 0000 C CNN +F 2 "" H 9200 9680 30 0000 C CNN +F 3 "" V 9200 9750 30 0000 C CNN + 1 9150 9700 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R14 +U 1 1 699A9118 +P 9150 10150 +F 0 "R14" H 9200 10280 50 0000 C CNN +F 1 "3k" H 9200 10100 50 0000 C CNN +F 2 "" H 9200 10130 30 0000 C CNN +F 3 "" V 9200 10200 30 0000 C CNN + 1 9150 10150 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 699A911E +P 9150 8650 +F 0 "R12" H 9200 8780 50 0000 C CNN +F 1 "10.5k" H 9200 8600 50 0000 C CNN +F 2 "" H 9200 8630 30 0000 C CNN +F 3 "" V 9200 8700 30 0000 C CNN + 1 9150 8650 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C4 +U 1 1 699A9124 +P 11000 8950 +F 0 "C4" H 11025 9050 50 0000 L CNN +F 1 "15pF" H 11025 8850 50 0000 L CNN +F 2 "" H 11000 8950 50 0001 C CNN +F 3 "" H 11000 8950 50 0001 C CNN + 1 11000 8950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 699A912A +P 11500 8950 +F 0 "D4" H 11500 9050 50 0000 C CNN +F 1 "eSim_Diode" H 11500 8850 50 0000 C CNN +F 2 "" H 11500 8950 60 0000 C CNN +F 3 "" H 11500 8950 60 0000 C CNN + 1 11500 8950 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R16 +U 1 1 699A9130 +P 10850 8150 +F 0 "R16" H 10900 8280 50 0000 C CNN +F 1 "1k" H 10900 8100 50 0000 C CNN +F 2 "" H 10900 8130 30 0000 C CNN +F 3 "" V 10900 8200 30 0000 C CNN + 1 10850 8150 + 0 -1 1 0 +$EndComp +Text GLabel 11000 9350 3 60 Input ~ 0 +GND +Text GLabel 11500 9400 3 60 Input ~ 0 +GND +Text GLabel 9850 10500 3 60 Input ~ 0 +GND +Text GLabel 10800 7750 1 60 Input ~ 0 +VCC +Wire Wire Line + 9750 9150 9750 9450 +Wire Wire Line + 9750 9450 10350 9450 +Wire Wire Line + 9750 8750 9750 8600 +Connection ~ 10650 8600 +Wire Wire Line + 10650 9650 10650 10350 +Wire Wire Line + 9100 8750 9100 9500 +Connection ~ 9100 8950 +Wire Wire Line + 9100 9800 9100 9950 +Wire Wire Line + 9100 10250 9100 10350 +Wire Wire Line + 9100 10350 10650 10350 +Wire Wire Line + 9100 9900 9950 9900 +Wire Wire Line + 9950 9900 9950 9450 +Connection ~ 9950 9450 +Connection ~ 9100 9900 +Wire Wire Line + 10800 8350 10800 8600 +Wire Wire Line + 11500 8800 11500 8600 +Wire Wire Line + 11000 8800 11000 8600 +Connection ~ 11000 8600 +Wire Wire Line + 9100 8450 9100 8250 +Wire Wire Line + 9100 8950 9450 8950 +Wire Wire Line + 11000 9100 11000 9350 +Wire Wire Line + 11500 9100 11500 9400 +Wire Wire Line + 10800 8050 10800 7750 +Wire Wire Line + 9850 10500 9850 10350 +Connection ~ 9850 10350 +Wire Wire Line + 10650 8600 10650 9250 +Wire Wire Line + 9750 8600 11650 8600 +Connection ~ 10800 8600 +Connection ~ 11500 8600 +$Comp +L eSim_NPN Q12 +U 1 1 699A9157 +P 13750 9350 +F 0 "Q12" H 13650 9400 50 0000 R CNN +F 1 "eSim_NPN" H 13700 9500 50 0000 R CNN +F 2 "" H 13950 9450 29 0000 C CNN +F 3 "" H 13750 9350 60 0000 C CNN + 1 13750 9350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 699A915D +P 12850 8850 +F 0 "Q10" H 12750 8900 50 0000 R CNN +F 1 "eSim_NPN" H 12800 9000 50 0000 R CNN +F 2 "" H 13050 8950 29 0000 C CNN +F 3 "" H 12850 8850 60 0000 C CNN + 1 12850 8850 + 1 0 0 -1 +$EndComp +$Comp +L resistor R21 +U 1 1 699A9163 +P 12350 9600 +F 0 "R21" H 12400 9730 50 0000 C CNN +F 1 "7.2k" H 12400 9550 50 0000 C CNN +F 2 "" H 12400 9580 30 0000 C CNN +F 3 "" V 12400 9650 30 0000 C CNN + 1 12350 9600 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R22 +U 1 1 699A9169 +P 12350 10050 +F 0 "R22" H 12400 10180 50 0000 C CNN +F 1 "3k" H 12400 10000 50 0000 C CNN +F 2 "" H 12400 10030 30 0000 C CNN +F 3 "" V 12400 10100 30 0000 C CNN + 1 12350 10050 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R20 +U 1 1 699A916F +P 12350 8550 +F 0 "R20" H 12400 8680 50 0000 C CNN +F 1 "10.5k" H 12400 8500 50 0000 C CNN +F 2 "" H 12400 8530 30 0000 C CNN +F 3 "" V 12400 8600 30 0000 C CNN + 1 12350 8550 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C6 +U 1 1 699A9175 +P 14200 8850 +F 0 "C6" H 14225 8950 50 0000 L CNN +F 1 "15pF" H 14225 8750 50 0000 L CNN +F 2 "" H 14200 8850 50 0001 C CNN +F 3 "" H 14200 8850 50 0001 C CNN + 1 14200 8850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 699A917B +P 14700 8850 +F 0 "D6" H 14700 8950 50 0000 C CNN +F 1 "eSim_Diode" H 14700 8750 50 0000 C CNN +F 2 "" H 14700 8850 60 0000 C CNN +F 3 "" H 14700 8850 60 0000 C CNN + 1 14700 8850 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R24 +U 1 1 699A9181 +P 14050 8050 +F 0 "R24" H 14100 8180 50 0000 C CNN +F 1 "1k" H 14100 8000 50 0000 C CNN +F 2 "" H 14100 8030 30 0000 C CNN +F 3 "" V 14100 8100 30 0000 C CNN + 1 14050 8050 + 0 -1 1 0 +$EndComp +Text GLabel 14200 9250 3 60 Input ~ 0 +GND +Text GLabel 14700 9300 3 60 Input ~ 0 +GND +Text GLabel 13050 10400 3 60 Input ~ 0 +GND +Text GLabel 14000 7650 1 60 Input ~ 0 +VCC +Wire Wire Line + 12950 9050 12950 9350 +Wire Wire Line + 12950 9350 13550 9350 +Wire Wire Line + 12950 8650 12950 8500 +Connection ~ 13850 8500 +Wire Wire Line + 13850 9550 13850 10250 +Wire Wire Line + 12300 8650 12300 9400 +Connection ~ 12300 8850 +Wire Wire Line + 12300 9700 12300 9850 +Wire Wire Line + 12300 10150 12300 10250 +Wire Wire Line + 12300 10250 13850 10250 +Wire Wire Line + 12300 9800 13150 9800 +Wire Wire Line + 13150 9800 13150 9350 +Connection ~ 13150 9350 +Connection ~ 12300 9800 +Wire Wire Line + 14000 8250 14000 8500 +Wire Wire Line + 14700 8700 14700 8500 +Wire Wire Line + 14200 8700 14200 8500 +Connection ~ 14200 8500 +Wire Wire Line + 12300 8350 12300 8150 +Wire Wire Line + 12300 8850 12650 8850 +Wire Wire Line + 14200 9000 14200 9250 +Wire Wire Line + 14700 9000 14700 9300 +Wire Wire Line + 14000 7950 14000 7650 +Wire Wire Line + 13050 10400 13050 10250 +Connection ~ 13050 10250 +Wire Wire Line + 13850 8500 13850 9150 +Wire Wire Line + 12950 8500 14850 8500 +Connection ~ 14000 8500 +Connection ~ 14700 8500 +$Comp +L eSim_NPN Q16 +U 1 1 699A91A8 +P 17150 9450 +F 0 "Q16" H 17050 9500 50 0000 R CNN +F 1 "eSim_NPN" H 17100 9600 50 0000 R CNN +F 2 "" H 17350 9550 29 0000 C CNN +F 3 "" H 17150 9450 60 0000 C CNN + 1 17150 9450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 699A91AE +P 16250 8950 +F 0 "Q14" H 16150 9000 50 0000 R CNN +F 1 "eSim_NPN" H 16200 9100 50 0000 R CNN +F 2 "" H 16450 9050 29 0000 C CNN +F 3 "" H 16250 8950 60 0000 C CNN + 1 16250 8950 + 1 0 0 -1 +$EndComp +$Comp +L resistor R29 +U 1 1 699A91B4 +P 15750 9700 +F 0 "R29" H 15800 9830 50 0000 C CNN +F 1 "7.2k" H 15800 9650 50 0000 C CNN +F 2 "" H 15800 9680 30 0000 C CNN +F 3 "" V 15800 9750 30 0000 C CNN + 1 15750 9700 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R30 +U 1 1 699A91BA +P 15750 10150 +F 0 "R30" H 15800 10280 50 0000 C CNN +F 1 "3k" H 15800 10100 50 0000 C CNN +F 2 "" H 15800 10130 30 0000 C CNN +F 3 "" V 15800 10200 30 0000 C CNN + 1 15750 10150 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R28 +U 1 1 699A91C0 +P 15750 8650 +F 0 "R28" H 15800 8780 50 0000 C CNN +F 1 "10.5k" H 15800 8600 50 0000 C CNN +F 2 "" H 15800 8630 30 0000 C CNN +F 3 "" V 15800 8700 30 0000 C CNN + 1 15750 8650 + 0 -1 -1 0 +$EndComp +$Comp +L capacitor_polarised C8 +U 1 1 699A91C6 +P 17600 8950 +F 0 "C8" H 17625 9050 50 0000 L CNN +F 1 "15pF" H 17625 8850 50 0000 L CNN +F 2 "" H 17600 8950 50 0001 C CNN +F 3 "" H 17600 8950 50 0001 C CNN + 1 17600 8950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D8 +U 1 1 699A91CC +P 18100 8950 +F 0 "D8" H 18100 9050 50 0000 C CNN +F 1 "eSim_Diode" H 18100 8850 50 0000 C CNN +F 2 "" H 18100 8950 60 0000 C CNN +F 3 "" H 18100 8950 60 0000 C CNN + 1 18100 8950 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R32 +U 1 1 699A91D2 +P 17450 8150 +F 0 "R32" H 17500 8280 50 0000 C CNN +F 1 "1k" H 17500 8100 50 0000 C CNN +F 2 "" H 17500 8130 30 0000 C CNN +F 3 "" V 17500 8200 30 0000 C CNN + 1 17450 8150 + 0 -1 1 0 +$EndComp +Text GLabel 17600 9350 3 60 Input ~ 0 +GND +Text GLabel 18100 9400 3 60 Input ~ 0 +GND +Text GLabel 16450 10500 3 60 Input ~ 0 +GND +Text GLabel 17400 7750 1 60 Input ~ 0 +VCC +Wire Wire Line + 16350 9150 16350 9450 +Wire Wire Line + 16350 9450 16950 9450 +Wire Wire Line + 16350 8750 16350 8600 +Connection ~ 17250 8600 +Wire Wire Line + 17250 9650 17250 10350 +Wire Wire Line + 15700 8750 15700 9500 +Connection ~ 15700 8950 +Wire Wire Line + 15700 9800 15700 9950 +Wire Wire Line + 15700 10250 15700 10350 +Wire Wire Line + 15700 10350 17250 10350 +Wire Wire Line + 15700 9900 16550 9900 +Wire Wire Line + 16550 9900 16550 9450 +Connection ~ 16550 9450 +Connection ~ 15700 9900 +Wire Wire Line + 17400 8350 17400 8600 +Wire Wire Line + 18100 8800 18100 8600 +Wire Wire Line + 17600 8800 17600 8600 +Connection ~ 17600 8600 +Wire Wire Line + 15700 8450 15700 8250 +Wire Wire Line + 15700 8950 16050 8950 +Wire Wire Line + 17600 9100 17600 9350 +Wire Wire Line + 18100 9100 18100 9400 +Wire Wire Line + 17400 8050 17400 7750 +Wire Wire Line + 16450 10500 16450 10350 +Connection ~ 16450 10350 +Wire Wire Line + 17250 8600 17250 9250 +Wire Wire Line + 16350 8600 18250 8600 +Connection ~ 17400 8600 +Connection ~ 18100 8600 +Text GLabel 1900 1650 2 60 Input ~ 0 +GND +Wire Wire Line + 1800 1650 1900 1650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ULN2804/ULN2804.sub b/library/SubcircuitLibrary/ULN2804/ULN2804.sub new file mode 100644 index 000000000..f950d7fd1 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2804/ULN2804.sub @@ -0,0 +1,72 @@ +* Subcircuit ULN2804 +.subckt ULN2804 net-_r1-pad2_ net-_r9-pad2_ net-_r17-pad2_ net-_r25-pad2_ net-_r5-pad2_ net-_r12-pad2_ net-_r20-pad2_ net-_r28-pad2_ gnd vcc net-_c8-pad1_ net-_c6-pad1_ net-_c4-pad1_ net-_c2-pad1_ net-_c7-pad1_ net-_c5-pad1_ net-_c3-pad1_ net-_c1-pad1_ +* c:\users\chand\esim\fossee\esim\library\subcircuitlibrary\uln2804\uln2804.cir +.include D.lib +.include NPN.lib +q2 net-_c1-pad1_ net-_q1-pad3_ gnd Q2N2222 +q1 net-_c1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r2 net-_q1-pad3_ net-_q1-pad2_ 7.2k +r3 gnd net-_q1-pad3_ 3k +r1 net-_q1-pad2_ net-_r1-pad2_ 10.5k +c1 net-_c1-pad1_ gnd 15pf +d1 gnd net-_c1-pad1_ 1N4148 +r4 vcc net-_c1-pad1_ 1k +q7 net-_c3-pad1_ net-_q5-pad3_ gnd Q2N2222 +q5 net-_c3-pad1_ net-_q5-pad2_ net-_q5-pad3_ Q2N2222 +r10 net-_q5-pad3_ net-_q5-pad2_ 7.2k +r11 gnd net-_q5-pad3_ 3k +r9 net-_q5-pad2_ net-_r9-pad2_ 10.5k +c3 net-_c3-pad1_ gnd 15pf +d3 gnd net-_c3-pad1_ 1N4148 +r15 vcc net-_c3-pad1_ 1k +q11 net-_c5-pad1_ net-_q11-pad2_ gnd Q2N2222 +q9 net-_c5-pad1_ net-_q9-pad2_ net-_q11-pad2_ Q2N2222 +r18 net-_q11-pad2_ net-_q9-pad2_ 7.2k +r19 gnd net-_q11-pad2_ 3k +r17 net-_q9-pad2_ net-_r17-pad2_ 10.5k +c5 net-_c5-pad1_ gnd 15pf +d5 gnd net-_c5-pad1_ 1N4148 +r23 vcc net-_c5-pad1_ 1k +q15 net-_c7-pad1_ net-_q13-pad3_ gnd Q2N2222 +q13 net-_c7-pad1_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222 +r26 net-_q13-pad3_ net-_q13-pad2_ 7.2k +r27 gnd net-_q13-pad3_ 3k +r25 net-_q13-pad2_ net-_r25-pad2_ 10.5k +c7 net-_c7-pad1_ gnd 15pf +d7 gnd net-_c7-pad1_ 1N4148 +r31 vcc net-_c7-pad1_ 1k +q4 net-_c2-pad1_ net-_q3-pad3_ gnd Q2N2222 +q3 net-_c2-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +r6 net-_q3-pad3_ net-_q3-pad2_ 7.2k +r7 gnd net-_q3-pad3_ 3k +r5 net-_q3-pad2_ net-_r5-pad2_ 10.5k +c2 net-_c2-pad1_ gnd 15pf +d2 gnd net-_c2-pad1_ 1N4148 +r8 vcc net-_c2-pad1_ 1k +q8 net-_c4-pad1_ net-_q6-pad3_ gnd Q2N2222 +q6 net-_c4-pad1_ net-_q6-pad2_ net-_q6-pad3_ Q2N2222 +r13 net-_q6-pad3_ net-_q6-pad2_ 7.2k +r14 gnd net-_q6-pad3_ 3k +r12 net-_q6-pad2_ net-_r12-pad2_ 10.5k +c4 net-_c4-pad1_ gnd 15pf +d4 gnd net-_c4-pad1_ 1N4148 +r16 vcc net-_c4-pad1_ 1k +q12 net-_c6-pad1_ net-_q10-pad3_ gnd Q2N2222 +q10 net-_c6-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +r21 net-_q10-pad3_ net-_q10-pad2_ 7.2k +r22 gnd net-_q10-pad3_ 3k +r20 net-_q10-pad2_ net-_r20-pad2_ 10.5k +c6 net-_c6-pad1_ gnd 15pf +d6 gnd net-_c6-pad1_ 1N4148 +r24 vcc net-_c6-pad1_ 1k +q16 net-_c8-pad1_ net-_q14-pad3_ gnd Q2N2222 +q14 net-_c8-pad1_ net-_q14-pad2_ net-_q14-pad3_ Q2N2222 +r29 net-_q14-pad3_ net-_q14-pad2_ 7.2k +r30 gnd net-_q14-pad3_ 3k +r28 net-_q14-pad2_ net-_r28-pad2_ 10.5k +c8 net-_c8-pad1_ gnd 15pf +d8 gnd net-_c8-pad1_ 1N4148 +r32 vcc net-_c8-pad1_ 1k +* Control Statements + +.ends ULN2804 \ No newline at end of file diff --git a/library/SubcircuitLibrary/ULN2804/ULN2804_Previous_Values.xml b/library/SubcircuitLibrary/ULN2804/ULN2804_Previous_Values.xml new file mode 100644 index 000000000..4e65e4f62 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2804/ULN2804_Previous_Values.xml @@ -0,0 +1 @@ +C:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\Users\chand\eSim\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperessecsecsec \ No newline at end of file diff --git a/library/SubcircuitLibrary/ULN2804/analysis b/library/SubcircuitLibrary/ULN2804/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/ULN2804/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file