mkTopModule.v

//
// Generated by Bluespec Compiler, version 2014.07.A (build 34078, 2014-07-30)
//
// On Sun Jan 21 14:48:26 CET 2018
//
//
// Ports:
// Name                         I/O  size props
// led_ifc_leds                   O    16 reg
// serial_ifc_serialOut           O     1 const
// display_ifc_disableSegmentsDisplay  O     7
// display_ifc_disableDotDisplay  O     1 const
// display_ifc_disableDigitDisplay  O     4
// CLK                            I     1 clock
// RST_N                          I     1 reset
// buttons_ifc_buttonL_left_input  I     1 reg
// buttons_ifc_buttonR_right_input  I     1 reg
// buttons_ifc_buttonU_upper_input  I     1 reg
// buttons_ifc_buttonD_down_input  I     1 reg
// buttons_ifc_buttonC_center_input  I     1 reg
// switch_ifc_switches_switch_status  I    16
// serial_ifc_serialIn_serial_input  I     1 unused
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkTopModule(CLK,
		   RST_N,

		   buttons_ifc_buttonL_left_input,

		   buttons_ifc_buttonR_right_input,

		   buttons_ifc_buttonU_upper_input,

		   buttons_ifc_buttonD_down_input,

		   buttons_ifc_buttonC_center_input,

		   switch_ifc_switches_switch_status,

		   led_ifc_leds,

		   serial_ifc_serialOut,

		   serial_ifc_serialIn_serial_input,

		   display_ifc_disableSegmentsDisplay,

		   display_ifc_disableDotDisplay,

		   display_ifc_disableDigitDisplay);
  input  CLK;
  input  RST_N;

  // action method buttons_ifc_buttonL
  input  buttons_ifc_buttonL_left_input;

  // action method buttons_ifc_buttonR
  input  buttons_ifc_buttonR_right_input;

  // action method buttons_ifc_buttonU
  input  buttons_ifc_buttonU_upper_input;

  // action method buttons_ifc_buttonD
  input  buttons_ifc_buttonD_down_input;

  // action method buttons_ifc_buttonC
  input  buttons_ifc_buttonC_center_input;

  // action method switch_ifc_switches
  input  [15 : 0] switch_ifc_switches_switch_status;

  // value method led_ifc_leds
  output [15 : 0] led_ifc_leds;

  // value method serial_ifc_serialOut
  output serial_ifc_serialOut;

  // action method serial_ifc_serialIn
  input  serial_ifc_serialIn_serial_input;

  // value method display_ifc_disableSegmentsDisplay
  output [6 : 0] display_ifc_disableSegmentsDisplay;

  // value method display_ifc_disableDotDisplay
  output display_ifc_disableDotDisplay;

  // value method display_ifc_disableDigitDisplay
  output [3 : 0] display_ifc_disableDigitDisplay;

  // signals for module outputs
  reg [6 : 0] display_ifc_disableSegmentsDisplay;
  wire [15 : 0] led_ifc_leds;
  wire [3 : 0] display_ifc_disableDigitDisplay;
  wire display_ifc_disableDotDisplay, serial_ifc_serialOut;

  // inlined wires
  reg [15 : 0] cycler_cyclingFIFO_wDataIn$wget;
  wire [15 : 0] cycler_cyclingFIFO_wDataOut$wget;
  wire cyclerFeeder_start_wire$whas,
       cyclerFeeder_state_set_pw$whas,
       cycler_cyclingFIFO_pwEnqueue$whas,
       cycler_cyclingFIFO_wDataIn$whas;

  // register alu_isDone
  reg alu_isDone;
  wire alu_isDone$D_IN, alu_isDone$EN;

  // register alu_isQueued
  reg alu_isQueued;
  wire alu_isQueued$D_IN, alu_isQueued$EN;

  // register alu_leftOp
  reg [32 : 0] alu_leftOp;
  wire [32 : 0] alu_leftOp$D_IN;
  wire alu_leftOp$EN;

  // register alu_op
  reg [3 : 0] alu_op;
  wire [3 : 0] alu_op$D_IN;
  wire alu_op$EN;

  // register alu_powerModule_currentBase
  reg [32 : 0] alu_powerModule_currentBase;
  reg [32 : 0] alu_powerModule_currentBase$D_IN;
  wire alu_powerModule_currentBase$EN;

  // register alu_powerModule_currentExponent
  reg [31 : 0] alu_powerModule_currentExponent;
  reg [31 : 0] alu_powerModule_currentExponent$D_IN;
  wire alu_powerModule_currentExponent$EN;

  // register alu_powerModule_result
  reg [32 : 0] alu_powerModule_result;
  reg [32 : 0] alu_powerModule_result$D_IN;
  wire alu_powerModule_result$EN;

  // register alu_result
  reg [32 : 0] alu_result;
  reg [32 : 0] alu_result$D_IN;
  wire alu_result$EN;

  // register alu_rightOp
  reg [32 : 0] alu_rightOp;
  wire [32 : 0] alu_rightOp$D_IN;
  wire alu_rightOp$EN;

  // register buttonStatus_0
  reg buttonStatus_0;
  wire buttonStatus_0$D_IN, buttonStatus_0$EN;

  // register buttonStatus_1
  reg buttonStatus_1;
  wire buttonStatus_1$D_IN, buttonStatus_1$EN;

  // register buttonStatus_2
  reg buttonStatus_2;
  wire buttonStatus_2$D_IN, buttonStatus_2$EN;

  // register buttonStatus_3
  reg buttonStatus_3;
  wire buttonStatus_3$D_IN, buttonStatus_3$EN;

  // register buttonStatus_4
  reg buttonStatus_4;
  wire buttonStatus_4$D_IN, buttonStatus_4$EN;

  // register clockDiv_ctr
  reg [27 : 0] clockDiv_ctr;
  wire [27 : 0] clockDiv_ctr$D_IN;
  wire clockDiv_ctr$EN;

  // register computeBuf
  reg [32 : 0] computeBuf;
  wire [32 : 0] computeBuf$D_IN;
  wire computeBuf$EN;

  // register currentDigitIndex
  reg [1 : 0] currentDigitIndex;
  wire [1 : 0] currentDigitIndex$D_IN;
  wire currentDigitIndex$EN;

  // register currentIsSigned
  reg currentIsSigned;
  wire currentIsSigned$D_IN, currentIsSigned$EN;

  // register currentNumberS
  reg [10 : 0] currentNumberS;
  wire [10 : 0] currentNumberS$D_IN;
  wire currentNumberS$EN;

  // register currentNumberU
  reg [3 : 0] currentNumberU;
  wire [3 : 0] currentNumberU$D_IN;
  wire currentNumberU$EN;

  // register cyclerFeeder_start_reg
  reg cyclerFeeder_start_reg;
  wire cyclerFeeder_start_reg$D_IN, cyclerFeeder_start_reg$EN;

  // register cyclerFeeder_start_reg_1
  reg cyclerFeeder_start_reg_1;
  wire cyclerFeeder_start_reg_1$D_IN, cyclerFeeder_start_reg_1$EN;

  // register cyclerFeeder_state_can_overlap
  reg cyclerFeeder_state_can_overlap;
  wire cyclerFeeder_state_can_overlap$D_IN, cyclerFeeder_state_can_overlap$EN;

  // register cyclerFeeder_state_fired
  reg cyclerFeeder_state_fired;
  wire cyclerFeeder_state_fired$D_IN, cyclerFeeder_state_fired$EN;

  // register cyclerFeeder_state_mkFSMstate
  reg [3 : 0] cyclerFeeder_state_mkFSMstate;
  reg [3 : 0] cyclerFeeder_state_mkFSMstate$D_IN;
  wire cyclerFeeder_state_mkFSMstate$EN;

  // register cycler_clockDiv_ctr
  reg [31 : 0] cycler_clockDiv_ctr;
  wire [31 : 0] cycler_clockDiv_ctr$D_IN;
  wire cycler_clockDiv_ctr$EN;

  // register cycler_cyclingFIFO_rCache
  reg [25 : 0] cycler_cyclingFIFO_rCache;
  wire [25 : 0] cycler_cyclingFIFO_rCache$D_IN;
  wire cycler_cyclingFIFO_rCache$EN;

  // register cycler_cyclingFIFO_rRdPtr
  reg [8 : 0] cycler_cyclingFIFO_rRdPtr;
  wire [8 : 0] cycler_cyclingFIFO_rRdPtr$D_IN;
  wire cycler_cyclingFIFO_rRdPtr$EN;

  // register cycler_cyclingFIFO_rWrPtr
  reg [8 : 0] cycler_cyclingFIFO_rWrPtr;
  wire [8 : 0] cycler_cyclingFIFO_rWrPtr$D_IN;
  wire cycler_cyclingFIFO_rWrPtr$EN;

  // register cycler_displayer_bcdDecodedInput_0
  reg [3 : 0] cycler_displayer_bcdDecodedInput_0;
  wire [3 : 0] cycler_displayer_bcdDecodedInput_0$D_IN;
  wire cycler_displayer_bcdDecodedInput_0$EN;

  // register cycler_displayer_bcdDecodedInput_1
  reg [3 : 0] cycler_displayer_bcdDecodedInput_1;
  wire [3 : 0] cycler_displayer_bcdDecodedInput_1$D_IN;
  wire cycler_displayer_bcdDecodedInput_1$EN;

  // register cycler_displayer_bcdDecodedInput_2
  reg [3 : 0] cycler_displayer_bcdDecodedInput_2;
  wire [3 : 0] cycler_displayer_bcdDecodedInput_2$D_IN;
  wire cycler_displayer_bcdDecodedInput_2$EN;

  // register cycler_displayer_bcdDecodedInput_3
  reg [3 : 0] cycler_displayer_bcdDecodedInput_3;
  wire [3 : 0] cycler_displayer_bcdDecodedInput_3$D_IN;
  wire cycler_displayer_bcdDecodedInput_3$EN;

  // register cycler_displayer_clockDiv_ctr
  reg [18 : 0] cycler_displayer_clockDiv_ctr;
  wire [18 : 0] cycler_displayer_clockDiv_ctr$D_IN;
  wire cycler_displayer_clockDiv_ctr$EN;

  // register cycler_displayer_currentDigitIndex
  reg [1 : 0] cycler_displayer_currentDigitIndex;
  wire [1 : 0] cycler_displayer_currentDigitIndex$D_IN;
  wire cycler_displayer_currentDigitIndex$EN;

  // register cycler_displayer_doubleDabbleCtr
  reg [3 : 0] cycler_displayer_doubleDabbleCtr;
  wire [3 : 0] cycler_displayer_doubleDabbleCtr$D_IN;
  wire cycler_displayer_doubleDabbleCtr$EN;

  // register cycler_displayer_isNegative
  reg cycler_displayer_isNegative;
  wire cycler_displayer_isNegative$D_IN, cycler_displayer_isNegative$EN;

  // register cycler_displayer_readyToDisplay
  reg cycler_displayer_readyToDisplay;
  wire cycler_displayer_readyToDisplay$D_IN,
       cycler_displayer_readyToDisplay$EN;

  // register cycler_displayer_toDisplay
  reg [13 : 0] cycler_displayer_toDisplay;
  wire [13 : 0] cycler_displayer_toDisplay$D_IN;
  wire cycler_displayer_toDisplay$EN;

  // register displayModule_bcdDecodedInput_0
  reg [3 : 0] displayModule_bcdDecodedInput_0;
  wire [3 : 0] displayModule_bcdDecodedInput_0$D_IN;
  wire displayModule_bcdDecodedInput_0$EN;

  // register displayModule_bcdDecodedInput_1
  reg [3 : 0] displayModule_bcdDecodedInput_1;
  wire [3 : 0] displayModule_bcdDecodedInput_1$D_IN;
  wire displayModule_bcdDecodedInput_1$EN;

  // register displayModule_bcdDecodedInput_2
  reg [3 : 0] displayModule_bcdDecodedInput_2;
  wire [3 : 0] displayModule_bcdDecodedInput_2$D_IN;
  wire displayModule_bcdDecodedInput_2$EN;

  // register displayModule_bcdDecodedInput_3
  reg [3 : 0] displayModule_bcdDecodedInput_3;
  wire [3 : 0] displayModule_bcdDecodedInput_3$D_IN;
  wire displayModule_bcdDecodedInput_3$EN;

  // register displayModule_clockDiv_ctr
  reg [18 : 0] displayModule_clockDiv_ctr;
  wire [18 : 0] displayModule_clockDiv_ctr$D_IN;
  wire displayModule_clockDiv_ctr$EN;

  // register displayModule_currentDigitIndex
  reg [1 : 0] displayModule_currentDigitIndex;
  wire [1 : 0] displayModule_currentDigitIndex$D_IN;
  wire displayModule_currentDigitIndex$EN;

  // register displayModule_doubleDabbleCtr
  reg [3 : 0] displayModule_doubleDabbleCtr;
  wire [3 : 0] displayModule_doubleDabbleCtr$D_IN;
  wire displayModule_doubleDabbleCtr$EN;

  // register displayModule_isNegative
  reg displayModule_isNegative;
  wire displayModule_isNegative$D_IN, displayModule_isNegative$EN;

  // register displayModule_readyToDisplay
  reg displayModule_readyToDisplay;
  wire displayModule_readyToDisplay$D_IN, displayModule_readyToDisplay$EN;

  // register displayModule_toDisplay
  reg [13 : 0] displayModule_toDisplay;
  wire [13 : 0] displayModule_toDisplay$D_IN;
  wire displayModule_toDisplay$EN;

  // register ledStatus
  reg [15 : 0] ledStatus;
  wire [15 : 0] ledStatus$D_IN;
  wire ledStatus$EN;

  // register leftInt_holdsNewValue
  reg leftInt_holdsNewValue;
  wire leftInt_holdsNewValue$D_IN, leftInt_holdsNewValue$EN;

  // register leftInt_valueHolder
  reg [31 : 0] leftInt_valueHolder;
  wire [31 : 0] leftInt_valueHolder$D_IN;
  wire leftInt_valueHolder$EN;

  // register rightInt_holdsNewValue
  reg rightInt_holdsNewValue;
  wire rightInt_holdsNewValue$D_IN, rightInt_holdsNewValue$EN;

  // register rightInt_valueHolder
  reg [31 : 0] rightInt_valueHolder;
  wire [31 : 0] rightInt_valueHolder$D_IN;
  wire rightInt_valueHolder$EN;

  // register toCompute_holdsNewValue
  reg toCompute_holdsNewValue;
  wire toCompute_holdsNewValue$D_IN, toCompute_holdsNewValue$EN;

  // register toCompute_valueHolder
  reg [2 : 0] toCompute_valueHolder;
  wire [2 : 0] toCompute_valueHolder$D_IN;
  wire toCompute_valueHolder$EN;

  // ports of submodule cycler_cyclingFIFO_memory
  wire [15 : 0] cycler_cyclingFIFO_memory$DIA,
		cycler_cyclingFIFO_memory$DIB,
		cycler_cyclingFIFO_memory$DOB;
  wire [7 : 0] cycler_cyclingFIFO_memory$ADDRA,
	       cycler_cyclingFIFO_memory$ADDRB;
  wire cycler_cyclingFIFO_memory$ENA,
       cycler_cyclingFIFO_memory$ENB,
       cycler_cyclingFIFO_memory$WEA,
       cycler_cyclingFIFO_memory$WEB;

  // rule scheduling signals
  wire WILL_FIRE_RL_alu_fetchComputedPower,
       WILL_FIRE_RL_alu_powerModule_signedStep,
       WILL_FIRE_RL_alu_powerModule_unsignedStep,
       WILL_FIRE_RL_alu_signedOperation,
       WILL_FIRE_RL_alu_signedOperationDiv,
       WILL_FIRE_RL_alu_startComputePower,
       WILL_FIRE_RL_alu_unsignedOperation,
       WILL_FIRE_RL_alu_unsignedOperationDiv,
       WILL_FIRE_RL_computeAndDisplay,
       WILL_FIRE_RL_cyclerFeeder_action_l111c9,
       WILL_FIRE_RL_cyclerFeeder_action_l120c16,
       WILL_FIRE_RL_cyclerFeeder_action_l121c18,
       WILL_FIRE_RL_cyclerFeeder_action_l122c18,
       WILL_FIRE_RL_cyclerFeeder_action_l123c9,
       WILL_FIRE_RL_cyclerFeeder_action_l127c9,
       WILL_FIRE_RL_cyclerFeeder_fsm_start,
       WILL_FIRE_RL_cyclerFeeder_idle_l110c5,
       WILL_FIRE_RL_cycler_cycle,
       WILL_FIRE_RL_cycler_displayer_doubleDabble;

  // inputs to muxes for submodule ports
  reg [3 : 0] MUX_cycler_displayer_bcdDecodedInput_0$write_1__VAL_1,
	      MUX_cycler_displayer_bcdDecodedInput_1$write_1__VAL_1,
	      MUX_cycler_displayer_bcdDecodedInput_2$write_1__VAL_1;
  wire [32 : 0] MUX_alu_powerModule_currentBase$write_1__VAL_2,
		MUX_alu_powerModule_currentBase$write_1__VAL_3,
		MUX_alu_powerModule_result$write_1__VAL_1,
		MUX_alu_powerModule_result$write_1__VAL_2,
		MUX_alu_powerModule_result$write_1__VAL_3,
		MUX_alu_result$write_1__VAL_2,
		MUX_alu_result$write_1__VAL_3;
  wire [31 : 0] MUX_alu_powerModule_currentExponent$write_1__VAL_1,
		MUX_alu_powerModule_currentExponent$write_1__VAL_2;
  wire [15 : 0] MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_1,
		MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_2,
		MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_4,
		MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_5;
  wire [13 : 0] MUX_cycler_displayer_toDisplay$write_1__VAL_1,
		MUX_cycler_displayer_toDisplay$write_1__VAL_2;
  wire [3 : 0] MUX_alu_op$write_1__VAL_2,
	       MUX_cycler_displayer_bcdDecodedInput_0$write_1__VAL_2,
	       MUX_cycler_displayer_bcdDecodedInput_1$write_1__VAL_2,
	       MUX_cycler_displayer_bcdDecodedInput_2$write_1__VAL_2,
	       MUX_cycler_displayer_bcdDecodedInput_3$write_1__VAL_1,
	       MUX_cycler_displayer_bcdDecodedInput_3$write_1__VAL_2,
	       MUX_cycler_displayer_doubleDabbleCtr$write_1__VAL_2;
  wire MUX_alu_powerModule_result$write_1__SEL_2,
       MUX_alu_powerModule_result$write_1__SEL_3,
       MUX_cycler_displayer_bcdDecodedInput_0$write_1__SEL_1,
       MUX_cycler_displayer_bcdDecodedInput_1$write_1__SEL_1,
       MUX_cycler_displayer_bcdDecodedInput_2$write_1__SEL_1,
       MUX_cycler_displayer_bcdDecodedInput_3$write_1__SEL_1,
       MUX_cycler_displayer_doubleDabbleCtr$write_1__SEL_1,
       MUX_cycler_displayer_readyToDisplay$write_1__VAL_1,
       MUX_toCompute_holdsNewValue$write_1__SEL_1;

  // remaining internal signals
  reg [31 : 0] IF_alu_op_0_BITS_2_TO_0_2_EQ_0_04_THEN_alu_lef_ETC___d119;
  reg [3 : 0] CASE_cycler_cyclingFIFO_wDataOutwget_BITS_15__ETC__q5,
	      IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d303,
	      IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_3_ETC___d318,
	      IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_5_ETC___d331,
	      IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_7_ETC___d350,
	      SEL_ARR_cycler_displayer_bcdDecodedInput_0_54__ETC___d159,
	      SEL_ARR_displayModule_bcdDecodedInput_0_0_disp_ETC___d15;
  reg [1 : 0] CASE_cycler_cyclingFIFO_memoryDOB_BITS_15_TO__ETC__q3,
	      CASE_cycler_cyclingFIFO_rCache_BITS_15_TO_14_0_ETC__q2,
	      CASE_cycler_cyclingFIFO_wDataInwget_BITS_15_T_ETC__q6,
	      CASE_cycler_cyclingFIFO_wDataOutwget_BITS_15__ETC__q4;
  wire [63 : 0] alu_leftOp_6_BITS_31_TO_0_05_MUL_alu_rightOp_8_ETC___d107,
		alu_powerModule_currentBase_3_BITS_31_TO_0_3_M_ETC___d79,
		alu_powerModule_result_0_BITS_31_TO_0_2_MUL_al_ETC___d74;
  wire [15 : 0] IF_NOT_cycler_cyclingFIFO_wDataIn_whas__12_13__ETC___d226;
  wire [10 : 0] IF_cycler_cyclingFIFO_wDataOut_wget__77_BIT_10_ETC___d292;
  wire [8 : 0] x__h9721, x__h9833;
  wire [3 : 0] IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d301,
	       IF_cycler_displayer_bcdDecodedInput_0_54_ULE_4_ETC___d167,
	       IF_cycler_displayer_bcdDecodedInput_1_55_ULE_4_ETC___d176,
	       IF_cycler_displayer_bcdDecodedInput_2_56_ULE_4_ETC___d184,
	       IF_cycler_displayer_bcdDecodedInput_3_ULE_4_TH_ETC__q1,
	       IF_displayModule_bcdDecodedInput_0_0_ULE_4_1_T_ETC___d23,
	       IF_displayModule_bcdDecodedInput_1_1_ULE_4_0_T_ETC___d32,
	       IF_displayModule_bcdDecodedInput_2_2_ULE_4_8_T_ETC___d40,
	       IF_displayModule_bcdDecodedInput_3_ULE_4_THEN__ETC__q7,
	       x__h32724;
  wire [2 : 0] IF_buttonStatus_1_71_THEN_2_ELSE_IF_buttonStat_ETC___d400;
  wire IF_computeBuf_68_BIT_31_70_THEN_NEG_computeBuf_ETC___d474,
       IF_cycler_cyclingFIFO_wDataOut_wget__77_BIT_10_ETC___d293,
       NOT_0_CONCAT_switch_ifc_switches_switch_status_ETC___d508,
       NOT_0_CONCAT_switch_ifc_switches_switch_status_ETC___d512,
       NOT_buttonStatus_0_65_70_AND_buttonStatus_1_71_ETC___d396,
       NOT_buttonStatus_1_71_75_AND_buttonStatus_2_76_ETC___d394,
       NOT_buttonStatus_2_76_80_AND_buttonStatus_3_81_ETC___d392,
       NOT_cycler_cyclingFIFO_rRdPtr_read__32_PLUS_12_ETC___d271,
       _dfoo1,
       alu_rightOp_8_BITS_31_TO_0_06_SLE_0___d137,
       computeBuf_68_BITS_31_TO_0_71_ULE_9999___d479,
       cyclerFeeder_abort_whas__05_AND_cyclerFeeder_a_ETC___d494,
       cycler_cyclingFIFO_wDataOut_wget__77_BITS_13_T_ETC___d297,
       cycler_cyclingFIFO_wDataOut_wget__77_BITS_15_T_ETC___d348;

  // value method led_ifc_leds
  assign led_ifc_leds = ledStatus ;

  // value method serial_ifc_serialOut
  assign serial_ifc_serialOut = 1'd1 ;

  // value method display_ifc_disableSegmentsDisplay
  always@(SEL_ARR_cycler_displayer_bcdDecodedInput_0_54__ETC___d159)
  begin
    case (SEL_ARR_cycler_displayer_bcdDecodedInput_0_54__ETC___d159)
      4'd0: display_ifc_disableSegmentsDisplay = 7'b1000000;
      4'd1: display_ifc_disableSegmentsDisplay = 7'b1111001;
      4'd2: display_ifc_disableSegmentsDisplay = 7'b0100100;
      4'd3: display_ifc_disableSegmentsDisplay = 7'b0110000;
      4'd4: display_ifc_disableSegmentsDisplay = 7'b0011001;
      4'd5: display_ifc_disableSegmentsDisplay = 7'b0010010;
      4'd6: display_ifc_disableSegmentsDisplay = 7'b0000010;
      4'd7: display_ifc_disableSegmentsDisplay = 7'b1111000;
      4'd8: display_ifc_disableSegmentsDisplay = 7'b0;
      4'd9: display_ifc_disableSegmentsDisplay = 7'b0010000;
      4'd10: display_ifc_disableSegmentsDisplay = 7'b0111111;
      4'd11: display_ifc_disableSegmentsDisplay = 7'b1110111;
      default: display_ifc_disableSegmentsDisplay = 7'b1111111;
    endcase
  end

  // value method display_ifc_disableDotDisplay
  assign display_ifc_disableDotDisplay = 1'd1 ;

  // value method display_ifc_disableDigitDisplay
  assign display_ifc_disableDigitDisplay =
	     cycler_displayer_readyToDisplay ? ~x__h32724 : 4'd1 ;

  // submodule cycler_cyclingFIFO_memory
  BRAM2 #(.PIPELINED(1'd0),
	  .ADDR_WIDTH(32'd8),
	  .DATA_WIDTH(32'd16),
	  .MEMSIZE(9'd256)) cycler_cyclingFIFO_memory(.CLKA(CLK),
						      .CLKB(CLK),
						      .ADDRA(cycler_cyclingFIFO_memory$ADDRA),
						      .ADDRB(cycler_cyclingFIFO_memory$ADDRB),
						      .DIA(cycler_cyclingFIFO_memory$DIA),
						      .DIB(cycler_cyclingFIFO_memory$DIB),
						      .WEA(cycler_cyclingFIFO_memory$WEA),
						      .WEB(cycler_cyclingFIFO_memory$WEB),
						      .ENA(cycler_cyclingFIFO_memory$ENA),
						      .ENB(cycler_cyclingFIFO_memory$ENB),
						      .DOA(),
						      .DOB(cycler_cyclingFIFO_memory$DOB));

  // rule RL_computeAndDisplay
  assign WILL_FIRE_RL_computeAndDisplay =
	     cyclerFeeder_abort_whas__05_AND_cyclerFeeder_a_ETC___d494 &&
	     !cyclerFeeder_start_reg &&
	     (toCompute_holdsNewValue || leftInt_holdsNewValue ||
	      rightInt_holdsNewValue) ;

  // rule RL_alu_signedOperation
  assign WILL_FIRE_RL_alu_signedOperation =
	     alu_leftOp[32] && alu_rightOp[32] && alu_op[3] &&
	     alu_op[2:0] != 3'd6 &&
	     !alu_isDone &&
	     alu_op[2:0] != 3'd1 ;

  // rule RL_alu_unsignedOperation
  assign WILL_FIRE_RL_alu_unsignedOperation =
	     !alu_leftOp[32] && !alu_rightOp[32] && alu_op[3] &&
	     alu_op[2:0] != 3'd6 &&
	     !alu_isDone &&
	     alu_op[2:0] != 3'd1 ;

  // rule RL_alu_signedOperationDiv
  assign WILL_FIRE_RL_alu_signedOperationDiv =
	     alu_leftOp[32] && alu_rightOp[32] && alu_op[3] && !alu_isDone &&
	     alu_op[2:0] == 3'd1 ;

  // rule RL_alu_unsignedOperationDiv
  assign WILL_FIRE_RL_alu_unsignedOperationDiv =
	     !alu_leftOp[32] && !alu_rightOp[32] && alu_op[3] &&
	     !alu_isDone &&
	     alu_op[2:0] == 3'd1 ;

  // rule RL_alu_fetchComputedPower
  assign WILL_FIRE_RL_alu_fetchComputedPower =
	     alu_powerModule_currentExponent == 32'd0 && alu_op[3] &&
	     alu_op[2:0] == 3'd6 &&
	     alu_isQueued ;

  // rule RL_alu_powerModule_unsignedStep
  assign WILL_FIRE_RL_alu_powerModule_unsignedStep =
	     !alu_powerModule_result[32] &&
	     !alu_powerModule_currentBase[32] &&
	     alu_powerModule_currentExponent != 32'd0 ;

  // rule RL_alu_powerModule_signedStep
  assign WILL_FIRE_RL_alu_powerModule_signedStep =
	     alu_powerModule_result[32] && alu_powerModule_currentBase[32] &&
	     alu_powerModule_currentExponent != 32'd0 ;

  // rule RL_alu_startComputePower
  assign WILL_FIRE_RL_alu_startComputePower =
	     alu_op[3] && alu_op[2:0] == 3'd6 && !alu_isDone &&
	     !alu_isQueued ;

  // rule RL_cycler_displayer_doubleDabble
  assign WILL_FIRE_RL_cycler_displayer_doubleDabble =
	     cycler_displayer_doubleDabbleCtr < 4'd14 &&
	     !cycler_displayer_readyToDisplay ;

  // rule RL_cycler_cycle
  assign WILL_FIRE_RL_cycler_cycle =
	     cycler_cyclingFIFO_rRdPtr != cycler_cyclingFIFO_rWrPtr &&
	     NOT_cycler_cyclingFIFO_rRdPtr_read__32_PLUS_12_ETC___d271 &&
	     cycler_clockDiv_ctr == 32'd0 ;

  // rule RL_cyclerFeeder_action_l120c16
  assign WILL_FIRE_RL_cyclerFeeder_action_l120c16 =
	     NOT_cycler_cyclingFIFO_rRdPtr_read__32_PLUS_12_ETC___d271 &&
	     cyclerFeeder_state_mkFSMstate == 4'd2 &&
	     !WILL_FIRE_RL_cycler_cycle ;

  // rule RL_cyclerFeeder_action_l121c18
  assign WILL_FIRE_RL_cyclerFeeder_action_l121c18 =
	     NOT_cycler_cyclingFIFO_rRdPtr_read__32_PLUS_12_ETC___d271 &&
	     cyclerFeeder_state_mkFSMstate == 4'd3 &&
	     !WILL_FIRE_RL_cycler_cycle ;

  // rule RL_cyclerFeeder_action_l122c18
  assign WILL_FIRE_RL_cyclerFeeder_action_l122c18 =
	     NOT_cycler_cyclingFIFO_rRdPtr_read__32_PLUS_12_ETC___d271 &&
	     cyclerFeeder_state_mkFSMstate == 4'd4 &&
	     !WILL_FIRE_RL_cycler_cycle ;

  // rule RL_cyclerFeeder_action_l123c9
  assign WILL_FIRE_RL_cyclerFeeder_action_l123c9 =
	     alu_isDone && cyclerFeeder_state_mkFSMstate == 4'd5 &&
	     !WILL_FIRE_RL_alu_fetchComputedPower ;

  // rule RL_cyclerFeeder_action_l127c9
  assign WILL_FIRE_RL_cyclerFeeder_action_l127c9 =
	     NOT_cycler_cyclingFIFO_rRdPtr_read__32_PLUS_12_ETC___d271 &&
	     cyclerFeeder_state_mkFSMstate == 4'd6 &&
	     !WILL_FIRE_RL_cycler_cycle ;

  // rule RL_cyclerFeeder_fsm_start
  assign WILL_FIRE_RL_cyclerFeeder_fsm_start =
	     cyclerFeeder_abort_whas__05_AND_cyclerFeeder_a_ETC___d494 &&
	     cyclerFeeder_start_reg ;

  // rule RL_cyclerFeeder_action_l111c9
  assign WILL_FIRE_RL_cyclerFeeder_action_l111c9 =
	     !alu_isDone && cyclerFeeder_start_wire$whas &&
	     (cyclerFeeder_state_mkFSMstate == 4'd0 ||
	      cyclerFeeder_state_mkFSMstate == 4'd7) &&
	     !WILL_FIRE_RL_alu_fetchComputedPower &&
	     !WILL_FIRE_RL_alu_unsignedOperationDiv &&
	     !WILL_FIRE_RL_alu_unsignedOperation &&
	     !WILL_FIRE_RL_alu_signedOperationDiv &&
	     !WILL_FIRE_RL_alu_signedOperation ;

  // rule RL_cyclerFeeder_idle_l110c5
  assign WILL_FIRE_RL_cyclerFeeder_idle_l110c5 =
	     !cyclerFeeder_start_wire$whas &&
	     cyclerFeeder_state_mkFSMstate == 4'd7 ;

  // inputs to muxes for submodule ports
  assign MUX_alu_powerModule_result$write_1__SEL_2 =
	     WILL_FIRE_RL_alu_powerModule_signedStep &&
	     alu_powerModule_currentExponent[0] ;
  assign MUX_alu_powerModule_result$write_1__SEL_3 =
	     WILL_FIRE_RL_alu_powerModule_unsignedStep &&
	     alu_powerModule_currentExponent[0] ;
  assign MUX_cycler_displayer_bcdDecodedInput_0$write_1__SEL_1 =
	     WILL_FIRE_RL_cycler_cycle &&
	     (cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd0 ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd1 ||
	      cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd1 ||
	      cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd0 ||
	      cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd2) ;
  assign MUX_cycler_displayer_bcdDecodedInput_1$write_1__SEL_1 =
	     WILL_FIRE_RL_cycler_cycle &&
	     (cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd0 ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd1 ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd2 &&
	      (cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd1 ||
	       cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd0 ||
	       cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd2) ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] != 2'd2 &&
	      (cycler_cyclingFIFO_wDataOut$wget[3:2] == 2'd1 ||
	       cycler_cyclingFIFO_wDataOut$wget[3:2] == 2'd0 ||
	       cycler_cyclingFIFO_wDataOut$wget[3:2] == 2'd2)) ;
  assign MUX_cycler_displayer_bcdDecodedInput_2$write_1__SEL_1 =
	     WILL_FIRE_RL_cycler_cycle &&
	     (cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd0 ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd1 ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd2 &&
	      (cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd1 ||
	       cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd0 ||
	       cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd2) ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] != 2'd2 &&
	      (cycler_cyclingFIFO_wDataOut$wget[5:4] == 2'd1 ||
	       cycler_cyclingFIFO_wDataOut$wget[5:4] == 2'd0 ||
	       cycler_cyclingFIFO_wDataOut$wget[5:4] == 2'd2)) ;
  assign MUX_cycler_displayer_bcdDecodedInput_3$write_1__SEL_1 =
	     WILL_FIRE_RL_cycler_cycle && _dfoo1 ;
  assign MUX_cycler_displayer_doubleDabbleCtr$write_1__SEL_1 =
	     WILL_FIRE_RL_cycler_cycle &&
	     (cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd0 ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd1) &&
	     (cycler_cyclingFIFO_wDataOut$wget[15:14] != 2'd1 ||
	      IF_cycler_cyclingFIFO_wDataOut_wget__77_BIT_10_ETC___d293) &&
	     (cycler_cyclingFIFO_wDataOut$wget[15:14] != 2'd0 ||
	      cycler_cyclingFIFO_wDataOut_wget__77_BITS_13_T_ETC___d297) ;
  assign MUX_toCompute_holdsNewValue$write_1__SEL_1 =
	     buttonStatus_0 && toCompute_valueHolder != 3'd3 ||
	     NOT_buttonStatus_0_65_70_AND_buttonStatus_1_71_ETC___d396 ;
  assign MUX_alu_op$write_1__VAL_2 = { 1'd1, toCompute_valueHolder } ;
  assign MUX_alu_powerModule_currentBase$write_1__VAL_2 =
	     { 1'd1,
	       alu_powerModule_currentBase_3_BITS_31_TO_0_3_M_ETC___d79[31:0] } ;
  assign MUX_alu_powerModule_currentBase$write_1__VAL_3 =
	     { 1'd0,
	       alu_powerModule_currentBase_3_BITS_31_TO_0_3_M_ETC___d79[31:0] } ;
  assign MUX_alu_powerModule_currentExponent$write_1__VAL_1 =
	     (alu_rightOp[32] &&
	      !alu_rightOp_8_BITS_31_TO_0_06_SLE_0___d137) ?
	       alu_rightOp[31:0] :
	       ((alu_rightOp[32] &&
		 alu_rightOp_8_BITS_31_TO_0_06_SLE_0___d137) ?
		  32'd0 :
		  alu_rightOp[31:0]) ;
  assign MUX_alu_powerModule_currentExponent$write_1__VAL_2 =
	     { 1'd0, alu_powerModule_currentExponent[31:1] } ;
  assign MUX_alu_powerModule_result$write_1__VAL_1 =
	     alu_leftOp[32] ? 33'h100000001 : 33'd1 ;
  assign MUX_alu_powerModule_result$write_1__VAL_2 =
	     { 1'd1,
	       alu_powerModule_result_0_BITS_31_TO_0_2_MUL_al_ETC___d74[31:0] } ;
  assign MUX_alu_powerModule_result$write_1__VAL_3 =
	     { 1'd0,
	       alu_powerModule_result_0_BITS_31_TO_0_2_MUL_al_ETC___d74[31:0] } ;
  assign MUX_alu_result$write_1__VAL_2 =
	     { 1'd1,
	       IF_alu_op_0_BITS_2_TO_0_2_EQ_0_04_THEN_alu_lef_ETC___d119 } ;
  assign MUX_alu_result$write_1__VAL_3 =
	     { 1'd0,
	       IF_alu_op_0_BITS_2_TO_0_2_EQ_0_04_THEN_alu_lef_ETC___d119 } ;
  assign MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_1 =
	     { 2'd0, leftInt_valueHolder[13:0] } ;
  assign MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_2 =
	     { 2'd0, rightInt_valueHolder[13:0] } ;
  assign MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_4 =
	     { CASE_cycler_cyclingFIFO_wDataOutwget_BITS_15__ETC__q4,
	       cycler_cyclingFIFO_wDataOut$wget[13:0] } ;
  assign MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_5 =
	     computeBuf[32] ?
	       (IF_computeBuf_68_BIT_31_70_THEN_NEG_computeBuf_ETC___d474 ?
		  { 2'd1, computeBuf[13:0] } :
		  16'd43689) :
	       (computeBuf_68_BITS_31_TO_0_71_ULE_9999___d479 ?
		  { 2'd0, computeBuf[13:0] } :
		  16'd43689) ;
  always@(cycler_cyclingFIFO_wDataOut$wget or
	  IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d303 or
	  IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d301)
  begin
    case (cycler_cyclingFIFO_wDataOut$wget[15:14])
      2'd0, 2'd1:
	  MUX_cycler_displayer_bcdDecodedInput_0$write_1__VAL_1 =
	      IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d301;
      default: MUX_cycler_displayer_bcdDecodedInput_0$write_1__VAL_1 =
		   IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d303;
    endcase
  end
  assign MUX_cycler_displayer_bcdDecodedInput_0$write_1__VAL_2 =
	     { IF_cycler_displayer_bcdDecodedInput_0_54_ULE_4_ETC___d167[2:0],
	       1'd0 } +
	     { 3'd0, cycler_displayer_toDisplay[13] } ;
  always@(cycler_cyclingFIFO_wDataOut$wget or
	  IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_3_ETC___d318 or
	  IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d301 or
	  IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d303)
  begin
    case (cycler_cyclingFIFO_wDataOut$wget[15:14])
      2'd0, 2'd1:
	  MUX_cycler_displayer_bcdDecodedInput_1$write_1__VAL_1 =
	      IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d301;
      2'd2:
	  MUX_cycler_displayer_bcdDecodedInput_1$write_1__VAL_1 =
	      IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d303;
      2'd3:
	  MUX_cycler_displayer_bcdDecodedInput_1$write_1__VAL_1 =
	      IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_3_ETC___d318;
    endcase
  end
  assign MUX_cycler_displayer_bcdDecodedInput_1$write_1__VAL_2 =
	     { IF_cycler_displayer_bcdDecodedInput_1_55_ULE_4_ETC___d176[2:0],
	       1'd0 } +
	     { 3'd0,
	       IF_cycler_displayer_bcdDecodedInput_0_54_ULE_4_ETC___d167[3] } ;
  always@(cycler_cyclingFIFO_wDataOut$wget or
	  IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_5_ETC___d331 or
	  IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d301 or
	  IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d303)
  begin
    case (cycler_cyclingFIFO_wDataOut$wget[15:14])
      2'd0, 2'd1:
	  MUX_cycler_displayer_bcdDecodedInput_2$write_1__VAL_1 =
	      IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d301;
      2'd2:
	  MUX_cycler_displayer_bcdDecodedInput_2$write_1__VAL_1 =
	      IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d303;
      2'd3:
	  MUX_cycler_displayer_bcdDecodedInput_2$write_1__VAL_1 =
	      IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_5_ETC___d331;
    endcase
  end
  assign MUX_cycler_displayer_bcdDecodedInput_2$write_1__VAL_2 =
	     { IF_cycler_displayer_bcdDecodedInput_2_56_ULE_4_ETC___d184[2:0],
	       1'd0 } +
	     { 3'd0,
	       IF_cycler_displayer_bcdDecodedInput_1_55_ULE_4_ETC___d176[3] } ;
  assign MUX_cycler_displayer_bcdDecodedInput_3$write_1__VAL_1 =
	     cycler_cyclingFIFO_wDataOut_wget__77_BITS_15_T_ETC___d348 ?
	       CASE_cycler_cyclingFIFO_wDataOutwget_BITS_15__ETC__q5 :
	       ((cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd1 &&
		 cycler_cyclingFIFO_wDataOut$wget[10]) ?
		  4'd10 :
		  4'd0) ;
  assign MUX_cycler_displayer_bcdDecodedInput_3$write_1__VAL_2 =
	     cycler_displayer_isNegative ?
	       cycler_displayer_bcdDecodedInput_3 :
	       { IF_cycler_displayer_bcdDecodedInput_3_ULE_4_TH_ETC__q1[2:0],
		 1'd0 } +
	       { 3'd0,
		 IF_cycler_displayer_bcdDecodedInput_2_56_ULE_4_ETC___d184[3] } ;
  assign MUX_cycler_displayer_doubleDabbleCtr$write_1__VAL_2 =
	     cycler_displayer_doubleDabbleCtr + 4'd1 ;
  assign MUX_cycler_displayer_readyToDisplay$write_1__VAL_1 =
	     cycler_cyclingFIFO_wDataOut$wget[15:14] != 2'd0 &&
	     cycler_cyclingFIFO_wDataOut$wget[15:14] != 2'd1 ||
	     cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd1 &&
	     !IF_cycler_cyclingFIFO_wDataOut_wget__77_BIT_10_ETC___d293 ||
	     cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd0 &&
	     !cycler_cyclingFIFO_wDataOut_wget__77_BITS_13_T_ETC___d297 ;
  assign MUX_cycler_displayer_toDisplay$write_1__VAL_1 =
	     (cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd0) ?
	       cycler_cyclingFIFO_wDataOut$wget[13:0] :
	       { 3'd0,
		 IF_cycler_cyclingFIFO_wDataOut_wget__77_BIT_10_ETC___d292 } ;
  assign MUX_cycler_displayer_toDisplay$write_1__VAL_2 =
	     { cycler_displayer_toDisplay[12:0], 1'd0 } ;

  // inlined wires
  always@(WILL_FIRE_RL_cyclerFeeder_action_l121c18 or
	  MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_1 or
	  WILL_FIRE_RL_cyclerFeeder_action_l122c18 or
	  MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_2 or
	  WILL_FIRE_RL_cyclerFeeder_action_l120c16 or
	  WILL_FIRE_RL_cycler_cycle or
	  MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_4 or
	  WILL_FIRE_RL_cyclerFeeder_action_l127c9 or
	  MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_5)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_cyclerFeeder_action_l121c18:
	  cycler_cyclingFIFO_wDataIn$wget =
	      MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_1;
      WILL_FIRE_RL_cyclerFeeder_action_l122c18:
	  cycler_cyclingFIFO_wDataIn$wget =
	      MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_2;
      WILL_FIRE_RL_cyclerFeeder_action_l120c16:
	  cycler_cyclingFIFO_wDataIn$wget = 16'd43690;
      WILL_FIRE_RL_cycler_cycle:
	  cycler_cyclingFIFO_wDataIn$wget =
	      MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_4;
      WILL_FIRE_RL_cyclerFeeder_action_l127c9:
	  cycler_cyclingFIFO_wDataIn$wget =
	      MUX_cycler_cyclingFIFO_wDataIn$wset_1__VAL_5;
      default: cycler_cyclingFIFO_wDataIn$wget =
		   16'b1010101010101010 /* unspecified value */ ;
    endcase
  end
  assign cycler_cyclingFIFO_wDataIn$whas =
	     WILL_FIRE_RL_cyclerFeeder_action_l121c18 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l122c18 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l120c16 ||
	     WILL_FIRE_RL_cycler_cycle ||
	     WILL_FIRE_RL_cyclerFeeder_action_l127c9 ;
  assign cycler_cyclingFIFO_wDataOut$wget =
	     (cycler_cyclingFIFO_rCache[25] &&
	      cycler_cyclingFIFO_rCache[24:16] == cycler_cyclingFIFO_rRdPtr) ?
	       { CASE_cycler_cyclingFIFO_rCache_BITS_15_TO_14_0_ETC__q2,
		 cycler_cyclingFIFO_rCache[13:0] } :
	       { CASE_cycler_cyclingFIFO_memoryDOB_BITS_15_TO__ETC__q3,
		 cycler_cyclingFIFO_memory$DOB[13:0] } ;
  assign cyclerFeeder_start_wire$whas =
	     WILL_FIRE_RL_cyclerFeeder_fsm_start ||
	     cyclerFeeder_start_reg_1 && !cyclerFeeder_state_fired ;
  assign cycler_cyclingFIFO_pwEnqueue$whas =
	     WILL_FIRE_RL_cycler_cycle ||
	     WILL_FIRE_RL_cyclerFeeder_action_l127c9 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l122c18 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l121c18 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l120c16 ;
  assign cyclerFeeder_state_set_pw$whas =
	     WILL_FIRE_RL_cyclerFeeder_idle_l110c5 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l127c9 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l123c9 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l122c18 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l121c18 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l120c16 ||
	     cyclerFeeder_state_mkFSMstate == 4'd1 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l111c9 ;

  // register alu_isDone
  assign alu_isDone$D_IN = !WILL_FIRE_RL_cyclerFeeder_action_l123c9 ;
  assign alu_isDone$EN =
	     WILL_FIRE_RL_cyclerFeeder_action_l123c9 ||
	     WILL_FIRE_RL_alu_unsignedOperationDiv ||
	     WILL_FIRE_RL_alu_signedOperationDiv ||
	     WILL_FIRE_RL_alu_unsignedOperation ||
	     WILL_FIRE_RL_alu_signedOperation ||
	     WILL_FIRE_RL_alu_fetchComputedPower ;

  // register alu_isQueued
  assign alu_isQueued$D_IN = !WILL_FIRE_RL_alu_fetchComputedPower ;
  assign alu_isQueued$EN =
	     WILL_FIRE_RL_alu_fetchComputedPower ||
	     WILL_FIRE_RL_alu_startComputePower ;

  // register alu_leftOp
  assign alu_leftOp$D_IN = { 1'd0, leftInt_valueHolder } ;
  assign alu_leftOp$EN = WILL_FIRE_RL_cyclerFeeder_action_l111c9 ;

  // register alu_op
  assign alu_op$D_IN =
	     WILL_FIRE_RL_cyclerFeeder_action_l123c9 ?
	       4'd2 :
	       MUX_alu_op$write_1__VAL_2 ;
  assign alu_op$EN =
	     WILL_FIRE_RL_cyclerFeeder_action_l123c9 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l111c9 ;

  // register alu_powerModule_currentBase
  always@(WILL_FIRE_RL_alu_startComputePower or
	  alu_leftOp or
	  WILL_FIRE_RL_alu_powerModule_signedStep or
	  MUX_alu_powerModule_currentBase$write_1__VAL_2 or
	  WILL_FIRE_RL_alu_powerModule_unsignedStep or
	  MUX_alu_powerModule_currentBase$write_1__VAL_3)
  case (1'b1)
    WILL_FIRE_RL_alu_startComputePower:
	alu_powerModule_currentBase$D_IN = alu_leftOp;
    WILL_FIRE_RL_alu_powerModule_signedStep:
	alu_powerModule_currentBase$D_IN =
	    MUX_alu_powerModule_currentBase$write_1__VAL_2;
    WILL_FIRE_RL_alu_powerModule_unsignedStep:
	alu_powerModule_currentBase$D_IN =
	    MUX_alu_powerModule_currentBase$write_1__VAL_3;
    default: alu_powerModule_currentBase$D_IN =
		 33'h0AAAAAAAA /* unspecified value */ ;
  endcase
  assign alu_powerModule_currentBase$EN =
	     WILL_FIRE_RL_alu_startComputePower ||
	     WILL_FIRE_RL_alu_powerModule_unsignedStep ||
	     WILL_FIRE_RL_alu_powerModule_signedStep ;

  // register alu_powerModule_currentExponent
  always@(WILL_FIRE_RL_alu_startComputePower or
	  MUX_alu_powerModule_currentExponent$write_1__VAL_1 or
	  WILL_FIRE_RL_alu_powerModule_signedStep or
	  MUX_alu_powerModule_currentExponent$write_1__VAL_2 or
	  WILL_FIRE_RL_alu_powerModule_unsignedStep)
  case (1'b1)
    WILL_FIRE_RL_alu_startComputePower:
	alu_powerModule_currentExponent$D_IN =
	    MUX_alu_powerModule_currentExponent$write_1__VAL_1;
    WILL_FIRE_RL_alu_powerModule_signedStep:
	alu_powerModule_currentExponent$D_IN =
	    MUX_alu_powerModule_currentExponent$write_1__VAL_2;
    WILL_FIRE_RL_alu_powerModule_unsignedStep:
	alu_powerModule_currentExponent$D_IN =
	    MUX_alu_powerModule_currentExponent$write_1__VAL_2;
    default: alu_powerModule_currentExponent$D_IN =
		 32'hAAAAAAAA /* unspecified value */ ;
  endcase
  assign alu_powerModule_currentExponent$EN =
	     WILL_FIRE_RL_alu_powerModule_signedStep ||
	     WILL_FIRE_RL_alu_powerModule_unsignedStep ||
	     WILL_FIRE_RL_alu_startComputePower ;

  // register alu_powerModule_result
  always@(WILL_FIRE_RL_alu_startComputePower or
	  MUX_alu_powerModule_result$write_1__VAL_1 or
	  MUX_alu_powerModule_result$write_1__SEL_2 or
	  MUX_alu_powerModule_result$write_1__VAL_2 or
	  MUX_alu_powerModule_result$write_1__SEL_3 or
	  MUX_alu_powerModule_result$write_1__VAL_3)
  case (1'b1)
    WILL_FIRE_RL_alu_startComputePower:
	alu_powerModule_result$D_IN =
	    MUX_alu_powerModule_result$write_1__VAL_1;
    MUX_alu_powerModule_result$write_1__SEL_2:
	alu_powerModule_result$D_IN =
	    MUX_alu_powerModule_result$write_1__VAL_2;
    MUX_alu_powerModule_result$write_1__SEL_3:
	alu_powerModule_result$D_IN =
	    MUX_alu_powerModule_result$write_1__VAL_3;
    default: alu_powerModule_result$D_IN =
		 33'h0AAAAAAAA /* unspecified value */ ;
  endcase
  assign alu_powerModule_result$EN =
	     WILL_FIRE_RL_alu_powerModule_unsignedStep &&
	     alu_powerModule_currentExponent[0] ||
	     WILL_FIRE_RL_alu_powerModule_signedStep &&
	     alu_powerModule_currentExponent[0] ||
	     WILL_FIRE_RL_alu_startComputePower ;

  // register alu_result
  always@(WILL_FIRE_RL_alu_fetchComputedPower or
	  alu_powerModule_result or
	  WILL_FIRE_RL_alu_signedOperation or
	  MUX_alu_result$write_1__VAL_2 or
	  WILL_FIRE_RL_alu_unsignedOperation or
	  MUX_alu_result$write_1__VAL_3 or
	  WILL_FIRE_RL_alu_unsignedOperationDiv or
	  WILL_FIRE_RL_alu_signedOperationDiv)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_alu_fetchComputedPower:
	  alu_result$D_IN = alu_powerModule_result;
      WILL_FIRE_RL_alu_signedOperation:
	  alu_result$D_IN = MUX_alu_result$write_1__VAL_2;
      WILL_FIRE_RL_alu_unsignedOperation:
	  alu_result$D_IN = MUX_alu_result$write_1__VAL_3;
      WILL_FIRE_RL_alu_unsignedOperationDiv: alu_result$D_IN = 33'd1;
      WILL_FIRE_RL_alu_signedOperationDiv: alu_result$D_IN = 33'h100000001;
      default: alu_result$D_IN = 33'h0AAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign alu_result$EN =
	     WILL_FIRE_RL_alu_fetchComputedPower ||
	     WILL_FIRE_RL_alu_signedOperation ||
	     WILL_FIRE_RL_alu_unsignedOperation ||
	     WILL_FIRE_RL_alu_unsignedOperationDiv ||
	     WILL_FIRE_RL_alu_signedOperationDiv ;

  // register alu_rightOp
  assign alu_rightOp$D_IN = { 1'd0, rightInt_valueHolder } ;
  assign alu_rightOp$EN = WILL_FIRE_RL_cyclerFeeder_action_l111c9 ;

  // register buttonStatus_0
  assign buttonStatus_0$D_IN = buttons_ifc_buttonL_left_input ;
  assign buttonStatus_0$EN = 1'd1 ;

  // register buttonStatus_1
  assign buttonStatus_1$D_IN = buttons_ifc_buttonR_right_input ;
  assign buttonStatus_1$EN = 1'd1 ;

  // register buttonStatus_2
  assign buttonStatus_2$D_IN = buttons_ifc_buttonU_upper_input ;
  assign buttonStatus_2$EN = 1'd1 ;

  // register buttonStatus_3
  assign buttonStatus_3$D_IN = buttons_ifc_buttonD_down_input ;
  assign buttonStatus_3$EN = 1'd1 ;

  // register buttonStatus_4
  assign buttonStatus_4$D_IN = buttons_ifc_buttonC_center_input ;
  assign buttonStatus_4$EN = 1'd1 ;

  // register clockDiv_ctr
  assign clockDiv_ctr$D_IN = clockDiv_ctr + 28'd1 ;
  assign clockDiv_ctr$EN = 1'd1 ;

  // register computeBuf
  assign computeBuf$D_IN = alu_result ;
  assign computeBuf$EN = WILL_FIRE_RL_cyclerFeeder_action_l123c9 ;

  // register currentDigitIndex
  assign currentDigitIndex$D_IN = 2'h0 ;
  assign currentDigitIndex$EN = 1'b0 ;

  // register currentIsSigned
  assign currentIsSigned$D_IN = 1'b0 ;
  assign currentIsSigned$EN = 1'b0 ;

  // register currentNumberS
  assign currentNumberS$D_IN = 11'h0 ;
  assign currentNumberS$EN = 1'b0 ;

  // register currentNumberU
  assign currentNumberU$D_IN = 4'h0 ;
  assign currentNumberU$EN = 1'b0 ;

  // register cyclerFeeder_start_reg
  assign cyclerFeeder_start_reg$D_IN = !WILL_FIRE_RL_cyclerFeeder_fsm_start ;
  assign cyclerFeeder_start_reg$EN =
	     WILL_FIRE_RL_cyclerFeeder_fsm_start ||
	     WILL_FIRE_RL_computeAndDisplay ;

  // register cyclerFeeder_start_reg_1
  assign cyclerFeeder_start_reg_1$D_IN = cyclerFeeder_start_wire$whas ;
  assign cyclerFeeder_start_reg_1$EN = 1'd1 ;

  // register cyclerFeeder_state_can_overlap
  assign cyclerFeeder_state_can_overlap$D_IN =
	     cyclerFeeder_state_set_pw$whas ||
	     cyclerFeeder_state_can_overlap ;
  assign cyclerFeeder_state_can_overlap$EN = 1'd1 ;

  // register cyclerFeeder_state_fired
  assign cyclerFeeder_state_fired$D_IN = cyclerFeeder_state_set_pw$whas ;
  assign cyclerFeeder_state_fired$EN = 1'd1 ;

  // register cyclerFeeder_state_mkFSMstate
  always@(WILL_FIRE_RL_cyclerFeeder_idle_l110c5 or
	  WILL_FIRE_RL_cyclerFeeder_action_l111c9 or
	  cyclerFeeder_state_mkFSMstate or
	  WILL_FIRE_RL_cyclerFeeder_action_l120c16 or
	  WILL_FIRE_RL_cyclerFeeder_action_l121c18 or
	  WILL_FIRE_RL_cyclerFeeder_action_l122c18 or
	  WILL_FIRE_RL_cyclerFeeder_action_l123c9 or
	  WILL_FIRE_RL_cyclerFeeder_action_l127c9)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_cyclerFeeder_idle_l110c5:
	  cyclerFeeder_state_mkFSMstate$D_IN = 4'd0;
      WILL_FIRE_RL_cyclerFeeder_action_l111c9:
	  cyclerFeeder_state_mkFSMstate$D_IN = 4'd1;
      cyclerFeeder_state_mkFSMstate == 4'd1:
	  cyclerFeeder_state_mkFSMstate$D_IN = 4'd2;
      WILL_FIRE_RL_cyclerFeeder_action_l120c16:
	  cyclerFeeder_state_mkFSMstate$D_IN = 4'd3;
      WILL_FIRE_RL_cyclerFeeder_action_l121c18:
	  cyclerFeeder_state_mkFSMstate$D_IN = 4'd4;
      WILL_FIRE_RL_cyclerFeeder_action_l122c18:
	  cyclerFeeder_state_mkFSMstate$D_IN = 4'd5;
      WILL_FIRE_RL_cyclerFeeder_action_l123c9:
	  cyclerFeeder_state_mkFSMstate$D_IN = 4'd6;
      WILL_FIRE_RL_cyclerFeeder_action_l127c9:
	  cyclerFeeder_state_mkFSMstate$D_IN = 4'd7;
      default: cyclerFeeder_state_mkFSMstate$D_IN =
		   4'b1010 /* unspecified value */ ;
    endcase
  end
  assign cyclerFeeder_state_mkFSMstate$EN =
	     WILL_FIRE_RL_cyclerFeeder_idle_l110c5 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l111c9 ||
	     cyclerFeeder_state_mkFSMstate == 4'd1 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l120c16 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l121c18 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l122c18 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l123c9 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l127c9 ;

  // register cycler_clockDiv_ctr
  assign cycler_clockDiv_ctr$D_IN =
	     (cycler_clockDiv_ctr < 32'd33554431) ?
	       cycler_clockDiv_ctr + 32'd1 :
	       32'd0 ;
  assign cycler_clockDiv_ctr$EN = 1'd1 ;

  // register cycler_cyclingFIFO_rCache
  assign cycler_cyclingFIFO_rCache$D_IN =
	     { 1'd1,
	       cycler_cyclingFIFO_rWrPtr,
	       IF_NOT_cycler_cyclingFIFO_wDataIn_whas__12_13__ETC___d226 } ;
  assign cycler_cyclingFIFO_rCache$EN =
	     cyclerFeeder_state_mkFSMstate != 4'd1 &&
	     cycler_cyclingFIFO_pwEnqueue$whas ;

  // register cycler_cyclingFIFO_rRdPtr
  assign cycler_cyclingFIFO_rRdPtr$D_IN =
	     (cyclerFeeder_state_mkFSMstate == 4'd1) ? 9'd0 : x__h9833 ;
  assign cycler_cyclingFIFO_rRdPtr$EN =
	     cyclerFeeder_state_mkFSMstate == 4'd1 ||
	     WILL_FIRE_RL_cycler_cycle ;

  // register cycler_cyclingFIFO_rWrPtr
  assign cycler_cyclingFIFO_rWrPtr$D_IN =
	     (cyclerFeeder_state_mkFSMstate == 4'd1) ? 9'd0 : x__h9721 ;
  assign cycler_cyclingFIFO_rWrPtr$EN =
	     cyclerFeeder_state_mkFSMstate == 4'd1 ||
	     cycler_cyclingFIFO_pwEnqueue$whas ;

  // register cycler_displayer_bcdDecodedInput_0
  assign cycler_displayer_bcdDecodedInput_0$D_IN =
	     MUX_cycler_displayer_bcdDecodedInput_0$write_1__SEL_1 ?
	       MUX_cycler_displayer_bcdDecodedInput_0$write_1__VAL_1 :
	       MUX_cycler_displayer_bcdDecodedInput_0$write_1__VAL_2 ;
  assign cycler_displayer_bcdDecodedInput_0$EN =
	     WILL_FIRE_RL_cycler_cycle &&
	     (cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd0 ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd1 ||
	      cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd1 ||
	      cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd0 ||
	      cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd2) ||
	     WILL_FIRE_RL_cycler_displayer_doubleDabble ;

  // register cycler_displayer_bcdDecodedInput_1
  assign cycler_displayer_bcdDecodedInput_1$D_IN =
	     MUX_cycler_displayer_bcdDecodedInput_1$write_1__SEL_1 ?
	       MUX_cycler_displayer_bcdDecodedInput_1$write_1__VAL_1 :
	       MUX_cycler_displayer_bcdDecodedInput_1$write_1__VAL_2 ;
  assign cycler_displayer_bcdDecodedInput_1$EN =
	     WILL_FIRE_RL_cycler_cycle &&
	     (cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd0 ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd1 ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd2 &&
	      (cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd1 ||
	       cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd0 ||
	       cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd2) ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] != 2'd2 &&
	      (cycler_cyclingFIFO_wDataOut$wget[3:2] == 2'd1 ||
	       cycler_cyclingFIFO_wDataOut$wget[3:2] == 2'd0 ||
	       cycler_cyclingFIFO_wDataOut$wget[3:2] == 2'd2)) ||
	     WILL_FIRE_RL_cycler_displayer_doubleDabble ;

  // register cycler_displayer_bcdDecodedInput_2
  assign cycler_displayer_bcdDecodedInput_2$D_IN =
	     MUX_cycler_displayer_bcdDecodedInput_2$write_1__SEL_1 ?
	       MUX_cycler_displayer_bcdDecodedInput_2$write_1__VAL_1 :
	       MUX_cycler_displayer_bcdDecodedInput_2$write_1__VAL_2 ;
  assign cycler_displayer_bcdDecodedInput_2$EN =
	     WILL_FIRE_RL_cycler_cycle &&
	     (cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd0 ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd1 ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd2 &&
	      (cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd1 ||
	       cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd0 ||
	       cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd2) ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] != 2'd2 &&
	      (cycler_cyclingFIFO_wDataOut$wget[5:4] == 2'd1 ||
	       cycler_cyclingFIFO_wDataOut$wget[5:4] == 2'd0 ||
	       cycler_cyclingFIFO_wDataOut$wget[5:4] == 2'd2)) ||
	     WILL_FIRE_RL_cycler_displayer_doubleDabble ;

  // register cycler_displayer_bcdDecodedInput_3
  assign cycler_displayer_bcdDecodedInput_3$D_IN =
	     MUX_cycler_displayer_bcdDecodedInput_3$write_1__SEL_1 ?
	       MUX_cycler_displayer_bcdDecodedInput_3$write_1__VAL_1 :
	       MUX_cycler_displayer_bcdDecodedInput_3$write_1__VAL_2 ;
  assign cycler_displayer_bcdDecodedInput_3$EN =
	     WILL_FIRE_RL_cycler_cycle && _dfoo1 ||
	     WILL_FIRE_RL_cycler_displayer_doubleDabble ;

  // register cycler_displayer_clockDiv_ctr
  assign cycler_displayer_clockDiv_ctr$D_IN =
	     cycler_displayer_clockDiv_ctr + 19'd1 ;
  assign cycler_displayer_clockDiv_ctr$EN = 1'd1 ;

  // register cycler_displayer_currentDigitIndex
  assign cycler_displayer_currentDigitIndex$D_IN =
	     cycler_displayer_currentDigitIndex + 2'd1 ;
  assign cycler_displayer_currentDigitIndex$EN =
	     cycler_displayer_readyToDisplay &&
	     cycler_displayer_clockDiv_ctr == 19'd0 ;

  // register cycler_displayer_doubleDabbleCtr
  assign cycler_displayer_doubleDabbleCtr$D_IN =
	     MUX_cycler_displayer_doubleDabbleCtr$write_1__SEL_1 ?
	       4'd0 :
	       MUX_cycler_displayer_doubleDabbleCtr$write_1__VAL_2 ;
  assign cycler_displayer_doubleDabbleCtr$EN =
	     MUX_cycler_displayer_doubleDabbleCtr$write_1__SEL_1 ||
	     WILL_FIRE_RL_cycler_displayer_doubleDabble ;

  // register cycler_displayer_isNegative
  assign cycler_displayer_isNegative$D_IN =
	     cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd1 &&
	     cycler_cyclingFIFO_wDataOut$wget[10] ;
  assign cycler_displayer_isNegative$EN =
	     MUX_cycler_displayer_doubleDabbleCtr$write_1__SEL_1 ;

  // register cycler_displayer_readyToDisplay
  assign cycler_displayer_readyToDisplay$D_IN =
	     WILL_FIRE_RL_cycler_cycle ?
	       MUX_cycler_displayer_readyToDisplay$write_1__VAL_1 :
	       cycler_displayer_doubleDabbleCtr == 4'd13 ;
  assign cycler_displayer_readyToDisplay$EN =
	     WILL_FIRE_RL_cycler_displayer_doubleDabble ||
	     WILL_FIRE_RL_cycler_cycle ;

  // register cycler_displayer_toDisplay
  assign cycler_displayer_toDisplay$D_IN =
	     MUX_cycler_displayer_doubleDabbleCtr$write_1__SEL_1 ?
	       MUX_cycler_displayer_toDisplay$write_1__VAL_1 :
	       MUX_cycler_displayer_toDisplay$write_1__VAL_2 ;
  assign cycler_displayer_toDisplay$EN =
	     MUX_cycler_displayer_doubleDabbleCtr$write_1__SEL_1 ||
	     WILL_FIRE_RL_cycler_displayer_doubleDabble ;

  // register displayModule_bcdDecodedInput_0
  assign displayModule_bcdDecodedInput_0$D_IN =
	     { IF_displayModule_bcdDecodedInput_0_0_ULE_4_1_T_ETC___d23[2:0],
	       1'd0 } +
	     { 3'd0, displayModule_toDisplay[13] } ;
  assign displayModule_bcdDecodedInput_0$EN =
	     displayModule_doubleDabbleCtr < 4'd14 &&
	     !displayModule_readyToDisplay ;

  // register displayModule_bcdDecodedInput_1
  assign displayModule_bcdDecodedInput_1$D_IN =
	     { IF_displayModule_bcdDecodedInput_1_1_ULE_4_0_T_ETC___d32[2:0],
	       1'd0 } +
	     { 3'd0,
	       IF_displayModule_bcdDecodedInput_0_0_ULE_4_1_T_ETC___d23[3] } ;
  assign displayModule_bcdDecodedInput_1$EN =
	     displayModule_doubleDabbleCtr < 4'd14 &&
	     !displayModule_readyToDisplay ;

  // register displayModule_bcdDecodedInput_2
  assign displayModule_bcdDecodedInput_2$D_IN =
	     { IF_displayModule_bcdDecodedInput_2_2_ULE_4_8_T_ETC___d40[2:0],
	       1'd0 } +
	     { 3'd0,
	       IF_displayModule_bcdDecodedInput_1_1_ULE_4_0_T_ETC___d32[3] } ;
  assign displayModule_bcdDecodedInput_2$EN =
	     displayModule_doubleDabbleCtr < 4'd14 &&
	     !displayModule_readyToDisplay ;

  // register displayModule_bcdDecodedInput_3
  assign displayModule_bcdDecodedInput_3$D_IN =
	     displayModule_isNegative ?
	       displayModule_bcdDecodedInput_3 :
	       { IF_displayModule_bcdDecodedInput_3_ULE_4_THEN__ETC__q7[2:0],
		 1'd0 } +
	       { 3'd0,
		 IF_displayModule_bcdDecodedInput_2_2_ULE_4_8_T_ETC___d40[3] } ;
  assign displayModule_bcdDecodedInput_3$EN =
	     displayModule_doubleDabbleCtr < 4'd14 &&
	     !displayModule_readyToDisplay ;

  // register displayModule_clockDiv_ctr
  assign displayModule_clockDiv_ctr$D_IN =
	     displayModule_clockDiv_ctr + 19'd1 ;
  assign displayModule_clockDiv_ctr$EN = 1'd1 ;

  // register displayModule_currentDigitIndex
  assign displayModule_currentDigitIndex$D_IN =
	     displayModule_currentDigitIndex + 2'd1 ;
  assign displayModule_currentDigitIndex$EN =
	     displayModule_readyToDisplay &&
	     displayModule_clockDiv_ctr == 19'd0 ;

  // register displayModule_doubleDabbleCtr
  assign displayModule_doubleDabbleCtr$D_IN =
	     displayModule_doubleDabbleCtr + 4'd1 ;
  assign displayModule_doubleDabbleCtr$EN =
	     displayModule_doubleDabbleCtr < 4'd14 &&
	     !displayModule_readyToDisplay ;

  // register displayModule_isNegative
  assign displayModule_isNegative$D_IN = 1'b0 ;
  assign displayModule_isNegative$EN = 1'b0 ;

  // register displayModule_readyToDisplay
  assign displayModule_readyToDisplay$D_IN =
	     displayModule_doubleDabbleCtr == 4'd13 ;
  assign displayModule_readyToDisplay$EN =
	     displayModule_doubleDabbleCtr < 4'd14 &&
	     !displayModule_readyToDisplay ;

  // register displayModule_toDisplay
  assign displayModule_toDisplay$D_IN =
	     { displayModule_toDisplay[12:0], 1'd0 } ;
  assign displayModule_toDisplay$EN =
	     displayModule_doubleDabbleCtr < 4'd14 &&
	     !displayModule_readyToDisplay ;

  // register ledStatus
  assign ledStatus$D_IN = switch_ifc_switches_switch_status ;
  assign ledStatus$EN = 1'd1 ;

  // register leftInt_holdsNewValue
  assign leftInt_holdsNewValue$D_IN =
	     NOT_0_CONCAT_switch_ifc_switches_switch_status_ETC___d508 ;
  assign leftInt_holdsNewValue$EN =
	     NOT_0_CONCAT_switch_ifc_switches_switch_status_ETC___d508 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l121c18 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l111c9 ;

  // register leftInt_valueHolder
  assign leftInt_valueHolder$D_IN =
	     { 24'd0, switch_ifc_switches_switch_status[15:8] } ;
  assign leftInt_valueHolder$EN =
	     NOT_0_CONCAT_switch_ifc_switches_switch_status_ETC___d508 ;

  // register rightInt_holdsNewValue
  assign rightInt_holdsNewValue$D_IN =
	     NOT_0_CONCAT_switch_ifc_switches_switch_status_ETC___d512 ;
  assign rightInt_holdsNewValue$EN =
	     NOT_0_CONCAT_switch_ifc_switches_switch_status_ETC___d512 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l122c18 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l111c9 ;

  // register rightInt_valueHolder
  assign rightInt_valueHolder$D_IN =
	     { 24'd0, switch_ifc_switches_switch_status[7:0] } ;
  assign rightInt_valueHolder$EN =
	     NOT_0_CONCAT_switch_ifc_switches_switch_status_ETC___d512 ;

  // register toCompute_holdsNewValue
  assign toCompute_holdsNewValue$D_IN =
	     MUX_toCompute_holdsNewValue$write_1__SEL_1 ;
  assign toCompute_holdsNewValue$EN =
	     buttonStatus_0 && toCompute_valueHolder != 3'd3 ||
	     NOT_buttonStatus_0_65_70_AND_buttonStatus_1_71_ETC___d396 ||
	     WILL_FIRE_RL_cyclerFeeder_action_l111c9 ;

  // register toCompute_valueHolder
  assign toCompute_valueHolder$D_IN =
	     buttonStatus_0 ?
	       3'd3 :
	       IF_buttonStatus_1_71_THEN_2_ELSE_IF_buttonStat_ETC___d400 ;
  assign toCompute_valueHolder$EN =
	     MUX_toCompute_holdsNewValue$write_1__SEL_1 ;

  // submodule cycler_cyclingFIFO_memory
  assign cycler_cyclingFIFO_memory$ADDRA = cycler_cyclingFIFO_rWrPtr[7:0] ;
  assign cycler_cyclingFIFO_memory$ADDRB =
	     WILL_FIRE_RL_cycler_cycle ?
	       x__h9833[7:0] :
	       cycler_cyclingFIFO_rRdPtr[7:0] ;
  assign cycler_cyclingFIFO_memory$DIA =
	     IF_NOT_cycler_cyclingFIFO_wDataIn_whas__12_13__ETC___d226 ;
  assign cycler_cyclingFIFO_memory$DIB =
	     16'b1010101010101010 /* unspecified value */  ;
  assign cycler_cyclingFIFO_memory$WEA = cycler_cyclingFIFO_pwEnqueue$whas ;
  assign cycler_cyclingFIFO_memory$WEB = 1'd0 ;
  assign cycler_cyclingFIFO_memory$ENA =
	     cyclerFeeder_state_mkFSMstate != 4'd1 ;
  assign cycler_cyclingFIFO_memory$ENB =
	     cyclerFeeder_state_mkFSMstate != 4'd1 ;

  // remaining internal signals
  assign IF_NOT_cycler_cyclingFIFO_wDataIn_whas__12_13__ETC___d226 =
	     (!cycler_cyclingFIFO_wDataIn$whas ||
	      cycler_cyclingFIFO_wDataIn$wget[15:14] == 2'd0) ?
	       { 2'd0,
		 cycler_cyclingFIFO_wDataIn$whas ?
		   cycler_cyclingFIFO_wDataIn$wget[13:0] :
		   14'd0 } :
	       { CASE_cycler_cyclingFIFO_wDataInwget_BITS_15_T_ETC__q6,
		 cycler_cyclingFIFO_wDataIn$wget[13:0] } ;
  assign IF_buttonStatus_1_71_THEN_2_ELSE_IF_buttonStat_ETC___d400 =
	     buttonStatus_1 ?
	       3'd2 :
	       (buttonStatus_2 ? 3'd0 : (buttonStatus_3 ? 3'd1 : 3'd6)) ;
  assign IF_computeBuf_68_BIT_31_70_THEN_NEG_computeBuf_ETC___d474 =
	     ((computeBuf[31] ? -computeBuf[31:0] : computeBuf[31:0]) ^
	      32'h80000000) <=
	     32'h800003E7 ;
  assign IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d301 =
	     (cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd1 &&
	      !IF_cycler_cyclingFIFO_wDataOut_wget__77_BIT_10_ETC___d293 ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd0 &&
	      !cycler_cyclingFIFO_wDataOut_wget__77_BITS_13_T_ETC___d297) ?
	       4'd10 :
	       4'd0 ;
  assign IF_cycler_cyclingFIFO_wDataOut_wget__77_BIT_10_ETC___d292 =
	     cycler_cyclingFIFO_wDataOut$wget[10] ?
	       -cycler_cyclingFIFO_wDataOut$wget[10:0] :
	       cycler_cyclingFIFO_wDataOut$wget[10:0] ;
  assign IF_cycler_cyclingFIFO_wDataOut_wget__77_BIT_10_ETC___d293 =
	     (IF_cycler_cyclingFIFO_wDataOut_wget__77_BIT_10_ETC___d292 ^
	      11'h400) <=
	     11'd2023 ;
  assign IF_cycler_displayer_bcdDecodedInput_0_54_ULE_4_ETC___d167 =
	     (cycler_displayer_bcdDecodedInput_0 <= 4'd4) ?
	       cycler_displayer_bcdDecodedInput_0 :
	       cycler_displayer_bcdDecodedInput_0 + 4'd3 ;
  assign IF_cycler_displayer_bcdDecodedInput_1_55_ULE_4_ETC___d176 =
	     (cycler_displayer_bcdDecodedInput_1 <= 4'd4) ?
	       cycler_displayer_bcdDecodedInput_1 :
	       cycler_displayer_bcdDecodedInput_1 + 4'd3 ;
  assign IF_cycler_displayer_bcdDecodedInput_2_56_ULE_4_ETC___d184 =
	     (cycler_displayer_bcdDecodedInput_2 <= 4'd4) ?
	       cycler_displayer_bcdDecodedInput_2 :
	       cycler_displayer_bcdDecodedInput_2 + 4'd3 ;
  assign IF_cycler_displayer_bcdDecodedInput_3_ULE_4_TH_ETC__q1 =
	     (cycler_displayer_bcdDecodedInput_3 <= 4'd4) ?
	       cycler_displayer_bcdDecodedInput_3 :
	       cycler_displayer_bcdDecodedInput_3 + 4'd3 ;
  assign IF_displayModule_bcdDecodedInput_0_0_ULE_4_1_T_ETC___d23 =
	     (displayModule_bcdDecodedInput_0 <= 4'd4) ?
	       displayModule_bcdDecodedInput_0 :
	       displayModule_bcdDecodedInput_0 + 4'd3 ;
  assign IF_displayModule_bcdDecodedInput_1_1_ULE_4_0_T_ETC___d32 =
	     (displayModule_bcdDecodedInput_1 <= 4'd4) ?
	       displayModule_bcdDecodedInput_1 :
	       displayModule_bcdDecodedInput_1 + 4'd3 ;
  assign IF_displayModule_bcdDecodedInput_2_2_ULE_4_8_T_ETC___d40 =
	     (displayModule_bcdDecodedInput_2 <= 4'd4) ?
	       displayModule_bcdDecodedInput_2 :
	       displayModule_bcdDecodedInput_2 + 4'd3 ;
  assign IF_displayModule_bcdDecodedInput_3_ULE_4_THEN__ETC__q7 =
	     (displayModule_bcdDecodedInput_3 <= 4'd4) ?
	       displayModule_bcdDecodedInput_3 :
	       displayModule_bcdDecodedInput_3 + 4'd3 ;
  assign NOT_0_CONCAT_switch_ifc_switches_switch_status_ETC___d508 =
	     { 24'd0, switch_ifc_switches_switch_status[15:8] } !=
	     leftInt_valueHolder ;
  assign NOT_0_CONCAT_switch_ifc_switches_switch_status_ETC___d512 =
	     { 24'd0, switch_ifc_switches_switch_status[7:0] } !=
	     rightInt_valueHolder ;
  assign NOT_buttonStatus_0_65_70_AND_buttonStatus_1_71_ETC___d396 =
	     !buttonStatus_0 &&
	     (buttonStatus_1 && toCompute_valueHolder != 3'd2 ||
	      NOT_buttonStatus_1_71_75_AND_buttonStatus_2_76_ETC___d394) ;
  assign NOT_buttonStatus_1_71_75_AND_buttonStatus_2_76_ETC___d394 =
	     !buttonStatus_1 &&
	     (buttonStatus_2 && toCompute_valueHolder != 3'd0 ||
	      NOT_buttonStatus_2_76_80_AND_buttonStatus_3_81_ETC___d392) ;
  assign NOT_buttonStatus_2_76_80_AND_buttonStatus_3_81_ETC___d392 =
	     !buttonStatus_2 &&
	     (buttonStatus_3 && toCompute_valueHolder != 3'd1 ||
	      !buttonStatus_3 && buttonStatus_4 &&
	      toCompute_valueHolder != 3'd6) ;
  assign NOT_cycler_cyclingFIFO_rRdPtr_read__32_PLUS_12_ETC___d271 =
	     cycler_cyclingFIFO_rRdPtr + 9'd128 != cycler_cyclingFIFO_rWrPtr ;
  assign _dfoo1 =
	     cycler_cyclingFIFO_wDataOut_wget__77_BITS_15_T_ETC___d348 ||
	     (cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd0 ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd1) &&
	     (cycler_cyclingFIFO_wDataOut$wget[15:14] != 2'd1 ||
	      IF_cycler_cyclingFIFO_wDataOut_wget__77_BIT_10_ETC___d293) &&
	     (cycler_cyclingFIFO_wDataOut$wget[15:14] != 2'd0 ||
	      cycler_cyclingFIFO_wDataOut_wget__77_BITS_13_T_ETC___d297) ;
  assign alu_leftOp_6_BITS_31_TO_0_05_MUL_alu_rightOp_8_ETC___d107 =
	     alu_leftOp[31:0] * alu_rightOp[31:0] ;
  assign alu_powerModule_currentBase_3_BITS_31_TO_0_3_M_ETC___d79 =
	     alu_powerModule_currentBase[31:0] *
	     alu_powerModule_currentBase[31:0] ;
  assign alu_powerModule_result_0_BITS_31_TO_0_2_MUL_al_ETC___d74 =
	     alu_powerModule_result[31:0] *
	     alu_powerModule_currentBase[31:0] ;
  assign alu_rightOp_8_BITS_31_TO_0_06_SLE_0___d137 =
	     (alu_rightOp[31:0] ^ 32'h80000000) <= 32'h80000000 ;
  assign computeBuf_68_BITS_31_TO_0_71_ULE_9999___d479 =
	     computeBuf[31:0] <= 32'd9999 ;
  assign cyclerFeeder_abort_whas__05_AND_cyclerFeeder_a_ETC___d494 =
	     (cyclerFeeder_state_mkFSMstate == 4'd0 ||
	      cyclerFeeder_state_mkFSMstate == 4'd7) &&
	     (!cyclerFeeder_start_reg_1 || cyclerFeeder_state_fired) ;
  assign cycler_cyclingFIFO_wDataOut_wget__77_BITS_13_T_ETC___d297 =
	     cycler_cyclingFIFO_wDataOut$wget[13:0] <= 14'd9999 ;
  assign cycler_cyclingFIFO_wDataOut_wget__77_BITS_15_T_ETC___d348 =
	     cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd1 &&
	     !IF_cycler_cyclingFIFO_wDataOut_wget__77_BIT_10_ETC___d293 ||
	     cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd0 &&
	     !cycler_cyclingFIFO_wDataOut_wget__77_BITS_13_T_ETC___d297 ||
	     cycler_cyclingFIFO_wDataOut$wget[15:14] != 2'd0 &&
	     cycler_cyclingFIFO_wDataOut$wget[15:14] != 2'd1 &&
	     (cycler_cyclingFIFO_wDataOut$wget[15:14] == 2'd2 &&
	      (cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd1 ||
	       cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd0 ||
	       cycler_cyclingFIFO_wDataOut$wget[1:0] == 2'd2) ||
	      cycler_cyclingFIFO_wDataOut$wget[15:14] != 2'd2 &&
	      (cycler_cyclingFIFO_wDataOut$wget[7:6] == 2'd1 ||
	       cycler_cyclingFIFO_wDataOut$wget[7:6] == 2'd0 ||
	       cycler_cyclingFIFO_wDataOut$wget[7:6] == 2'd2)) ;
  assign x__h32724 = 4'd1 << cycler_displayer_currentDigitIndex ;
  assign x__h9721 = cycler_cyclingFIFO_rWrPtr + 9'd1 ;
  assign x__h9833 = cycler_cyclingFIFO_rRdPtr + 9'd1 ;
  always@(alu_op or
	  alu_leftOp or
	  alu_rightOp or
	  alu_leftOp_6_BITS_31_TO_0_05_MUL_alu_rightOp_8_ETC___d107)
  begin
    case (alu_op[2:0])
      3'd0:
	  IF_alu_op_0_BITS_2_TO_0_2_EQ_0_04_THEN_alu_lef_ETC___d119 =
	      alu_leftOp_6_BITS_31_TO_0_05_MUL_alu_rightOp_8_ETC___d107[31:0];
      3'd2:
	  IF_alu_op_0_BITS_2_TO_0_2_EQ_0_04_THEN_alu_lef_ETC___d119 =
	      alu_leftOp[31:0] - alu_rightOp[31:0];
      3'd3:
	  IF_alu_op_0_BITS_2_TO_0_2_EQ_0_04_THEN_alu_lef_ETC___d119 =
	      alu_leftOp[31:0] + alu_rightOp[31:0];
      3'd4:
	  IF_alu_op_0_BITS_2_TO_0_2_EQ_0_04_THEN_alu_lef_ETC___d119 =
	      alu_leftOp[31:0] & alu_rightOp[31:0];
      default: IF_alu_op_0_BITS_2_TO_0_2_EQ_0_04_THEN_alu_lef_ETC___d119 =
		   alu_leftOp[31:0] | alu_rightOp[31:0];
    endcase
  end
  always@(cycler_displayer_currentDigitIndex or
	  cycler_displayer_bcdDecodedInput_0 or
	  cycler_displayer_bcdDecodedInput_1 or
	  cycler_displayer_bcdDecodedInput_2 or
	  cycler_displayer_bcdDecodedInput_3)
  begin
    case (cycler_displayer_currentDigitIndex)
      2'd0:
	  SEL_ARR_cycler_displayer_bcdDecodedInput_0_54__ETC___d159 =
	      cycler_displayer_bcdDecodedInput_0;
      2'd1:
	  SEL_ARR_cycler_displayer_bcdDecodedInput_0_54__ETC___d159 =
	      cycler_displayer_bcdDecodedInput_1;
      2'd2:
	  SEL_ARR_cycler_displayer_bcdDecodedInput_0_54__ETC___d159 =
	      cycler_displayer_bcdDecodedInput_2;
      2'd3:
	  SEL_ARR_cycler_displayer_bcdDecodedInput_0_54__ETC___d159 =
	      cycler_displayer_bcdDecodedInput_3;
    endcase
  end
  always@(displayModule_currentDigitIndex or
	  displayModule_bcdDecodedInput_0 or
	  displayModule_bcdDecodedInput_1 or
	  displayModule_bcdDecodedInput_2 or displayModule_bcdDecodedInput_3)
  begin
    case (displayModule_currentDigitIndex)
      2'd0:
	  SEL_ARR_displayModule_bcdDecodedInput_0_0_disp_ETC___d15 =
	      displayModule_bcdDecodedInput_0;
      2'd1:
	  SEL_ARR_displayModule_bcdDecodedInput_0_0_disp_ETC___d15 =
	      displayModule_bcdDecodedInput_1;
      2'd2:
	  SEL_ARR_displayModule_bcdDecodedInput_0_0_disp_ETC___d15 =
	      displayModule_bcdDecodedInput_2;
      2'd3:
	  SEL_ARR_displayModule_bcdDecodedInput_0_0_disp_ETC___d15 =
	      displayModule_bcdDecodedInput_3;
    endcase
  end
  always@(cycler_cyclingFIFO_rCache)
  begin
    case (cycler_cyclingFIFO_rCache[15:14])
      2'd0, 2'd1, 2'd2:
	  CASE_cycler_cyclingFIFO_rCache_BITS_15_TO_14_0_ETC__q2 =
	      cycler_cyclingFIFO_rCache[15:14];
      2'd3: CASE_cycler_cyclingFIFO_rCache_BITS_15_TO_14_0_ETC__q2 = 2'd3;
    endcase
  end
  always@(cycler_cyclingFIFO_memory$DOB)
  begin
    case (cycler_cyclingFIFO_memory$DOB[15:14])
      2'd0, 2'd1, 2'd2:
	  CASE_cycler_cyclingFIFO_memoryDOB_BITS_15_TO__ETC__q3 =
	      cycler_cyclingFIFO_memory$DOB[15:14];
      2'd3: CASE_cycler_cyclingFIFO_memoryDOB_BITS_15_TO__ETC__q3 = 2'd3;
    endcase
  end
  always@(cycler_cyclingFIFO_wDataOut$wget)
  begin
    case (cycler_cyclingFIFO_wDataOut$wget[1:0])
      2'd0: IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d303 = 4'd11;
      2'd1: IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d303 = 4'd10;
      default: IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d303 =
		   4'd15;
    endcase
  end
  always@(cycler_cyclingFIFO_wDataOut$wget)
  begin
    case (cycler_cyclingFIFO_wDataOut$wget[3:2])
      2'd0: IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_3_ETC___d318 = 4'd11;
      2'd1: IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_3_ETC___d318 = 4'd10;
      default: IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_3_ETC___d318 =
		   4'd15;
    endcase
  end
  always@(cycler_cyclingFIFO_wDataOut$wget)
  begin
    case (cycler_cyclingFIFO_wDataOut$wget[5:4])
      2'd0: IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_5_ETC___d331 = 4'd11;
      2'd1: IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_5_ETC___d331 = 4'd10;
      default: IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_5_ETC___d331 =
		   4'd15;
    endcase
  end
  always@(cycler_cyclingFIFO_wDataOut$wget)
  begin
    case (cycler_cyclingFIFO_wDataOut$wget[7:6])
      2'd0: IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_7_ETC___d350 = 4'd11;
      2'd1: IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_7_ETC___d350 = 4'd10;
      default: IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_7_ETC___d350 =
		   4'd15;
    endcase
  end
  always@(cycler_cyclingFIFO_wDataOut$wget)
  begin
    case (cycler_cyclingFIFO_wDataOut$wget[15:14])
      2'd0, 2'd1, 2'd2:
	  CASE_cycler_cyclingFIFO_wDataOutwget_BITS_15__ETC__q4 =
	      cycler_cyclingFIFO_wDataOut$wget[15:14];
      2'd3: CASE_cycler_cyclingFIFO_wDataOutwget_BITS_15__ETC__q4 = 2'd3;
    endcase
  end
  always@(cycler_cyclingFIFO_wDataOut$wget or
	  IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_7_ETC___d350 or
	  IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d303)
  begin
    case (cycler_cyclingFIFO_wDataOut$wget[15:14])
      2'd0, 2'd1:
	  CASE_cycler_cyclingFIFO_wDataOutwget_BITS_15__ETC__q5 = 4'd10;
      2'd2:
	  CASE_cycler_cyclingFIFO_wDataOutwget_BITS_15__ETC__q5 =
	      IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_1_ETC___d303;
      2'd3:
	  CASE_cycler_cyclingFIFO_wDataOutwget_BITS_15__ETC__q5 =
	      IF_cycler_cyclingFIFO_wDataOut_wget__77_BITS_7_ETC___d350;
    endcase
  end
  always@(cycler_cyclingFIFO_wDataIn$wget)
  begin
    case (cycler_cyclingFIFO_wDataIn$wget[15:14])
      2'd1, 2'd2:
	  CASE_cycler_cyclingFIFO_wDataInwget_BITS_15_T_ETC__q6 =
	      cycler_cyclingFIFO_wDataIn$wget[15:14];
      default: CASE_cycler_cyclingFIFO_wDataInwget_BITS_15_T_ETC__q6 = 2'd3;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        alu_isDone <= `BSV_ASSIGNMENT_DELAY 1'd0;
	alu_isQueued <= `BSV_ASSIGNMENT_DELAY 1'd0;
	alu_op <= `BSV_ASSIGNMENT_DELAY 4'd2;
	buttonStatus_0 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	buttonStatus_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	buttonStatus_2 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	buttonStatus_3 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	buttonStatus_4 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	clockDiv_ctr <= `BSV_ASSIGNMENT_DELAY 28'd0;
	currentDigitIndex <= `BSV_ASSIGNMENT_DELAY 2'd0;
	currentIsSigned <= `BSV_ASSIGNMENT_DELAY 1'd0;
	currentNumberS <= `BSV_ASSIGNMENT_DELAY 11'd0;
	currentNumberU <= `BSV_ASSIGNMENT_DELAY 4'd0;
	cyclerFeeder_start_reg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	cyclerFeeder_start_reg_1 <= `BSV_ASSIGNMENT_DELAY 1'd0;
	cyclerFeeder_state_can_overlap <= `BSV_ASSIGNMENT_DELAY 1'd1;
	cyclerFeeder_state_fired <= `BSV_ASSIGNMENT_DELAY 1'd0;
	cyclerFeeder_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY 4'd0;
	cycler_clockDiv_ctr <= `BSV_ASSIGNMENT_DELAY 32'd0;
	cycler_cyclingFIFO_rCache <= `BSV_ASSIGNMENT_DELAY 26'd11184810;
	cycler_cyclingFIFO_rRdPtr <= `BSV_ASSIGNMENT_DELAY 9'd0;
	cycler_cyclingFIFO_rWrPtr <= `BSV_ASSIGNMENT_DELAY 9'd0;
	cycler_displayer_bcdDecodedInput_0 <= `BSV_ASSIGNMENT_DELAY 4'd15;
	cycler_displayer_bcdDecodedInput_1 <= `BSV_ASSIGNMENT_DELAY 4'd15;
	cycler_displayer_bcdDecodedInput_2 <= `BSV_ASSIGNMENT_DELAY 4'd15;
	cycler_displayer_bcdDecodedInput_3 <= `BSV_ASSIGNMENT_DELAY 4'd15;
	cycler_displayer_clockDiv_ctr <= `BSV_ASSIGNMENT_DELAY 19'd0;
	cycler_displayer_currentDigitIndex <= `BSV_ASSIGNMENT_DELAY 2'd0;
	cycler_displayer_isNegative <= `BSV_ASSIGNMENT_DELAY 1'd0;
	cycler_displayer_readyToDisplay <= `BSV_ASSIGNMENT_DELAY 1'd0;
	displayModule_bcdDecodedInput_0 <= `BSV_ASSIGNMENT_DELAY 4'd15;
	displayModule_bcdDecodedInput_1 <= `BSV_ASSIGNMENT_DELAY 4'd15;
	displayModule_bcdDecodedInput_2 <= `BSV_ASSIGNMENT_DELAY 4'd15;
	displayModule_bcdDecodedInput_3 <= `BSV_ASSIGNMENT_DELAY 4'd15;
	displayModule_clockDiv_ctr <= `BSV_ASSIGNMENT_DELAY 19'd0;
	displayModule_currentDigitIndex <= `BSV_ASSIGNMENT_DELAY 2'd0;
	displayModule_isNegative <= `BSV_ASSIGNMENT_DELAY 1'd0;
	displayModule_readyToDisplay <= `BSV_ASSIGNMENT_DELAY 1'd0;
	ledStatus <= `BSV_ASSIGNMENT_DELAY 16'd0;
	leftInt_holdsNewValue <= `BSV_ASSIGNMENT_DELAY 1'd0;
	leftInt_valueHolder <= `BSV_ASSIGNMENT_DELAY 32'd0;
	rightInt_holdsNewValue <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rightInt_valueHolder <= `BSV_ASSIGNMENT_DELAY 32'd0;
	toCompute_holdsNewValue <= `BSV_ASSIGNMENT_DELAY 1'd0;
	toCompute_valueHolder <= `BSV_ASSIGNMENT_DELAY 3'd3;
      end
    else
      begin
        if (alu_isDone$EN)
	  alu_isDone <= `BSV_ASSIGNMENT_DELAY alu_isDone$D_IN;
	if (alu_isQueued$EN)
	  alu_isQueued <= `BSV_ASSIGNMENT_DELAY alu_isQueued$D_IN;
	if (alu_op$EN) alu_op <= `BSV_ASSIGNMENT_DELAY alu_op$D_IN;
	if (buttonStatus_0$EN)
	  buttonStatus_0 <= `BSV_ASSIGNMENT_DELAY buttonStatus_0$D_IN;
	if (buttonStatus_1$EN)
	  buttonStatus_1 <= `BSV_ASSIGNMENT_DELAY buttonStatus_1$D_IN;
	if (buttonStatus_2$EN)
	  buttonStatus_2 <= `BSV_ASSIGNMENT_DELAY buttonStatus_2$D_IN;
	if (buttonStatus_3$EN)
	  buttonStatus_3 <= `BSV_ASSIGNMENT_DELAY buttonStatus_3$D_IN;
	if (buttonStatus_4$EN)
	  buttonStatus_4 <= `BSV_ASSIGNMENT_DELAY buttonStatus_4$D_IN;
	if (clockDiv_ctr$EN)
	  clockDiv_ctr <= `BSV_ASSIGNMENT_DELAY clockDiv_ctr$D_IN;
	if (currentDigitIndex$EN)
	  currentDigitIndex <= `BSV_ASSIGNMENT_DELAY currentDigitIndex$D_IN;
	if (currentIsSigned$EN)
	  currentIsSigned <= `BSV_ASSIGNMENT_DELAY currentIsSigned$D_IN;
	if (currentNumberS$EN)
	  currentNumberS <= `BSV_ASSIGNMENT_DELAY currentNumberS$D_IN;
	if (currentNumberU$EN)
	  currentNumberU <= `BSV_ASSIGNMENT_DELAY currentNumberU$D_IN;
	if (cyclerFeeder_start_reg$EN)
	  cyclerFeeder_start_reg <= `BSV_ASSIGNMENT_DELAY
	      cyclerFeeder_start_reg$D_IN;
	if (cyclerFeeder_start_reg_1$EN)
	  cyclerFeeder_start_reg_1 <= `BSV_ASSIGNMENT_DELAY
	      cyclerFeeder_start_reg_1$D_IN;
	if (cyclerFeeder_state_can_overlap$EN)
	  cyclerFeeder_state_can_overlap <= `BSV_ASSIGNMENT_DELAY
	      cyclerFeeder_state_can_overlap$D_IN;
	if (cyclerFeeder_state_fired$EN)
	  cyclerFeeder_state_fired <= `BSV_ASSIGNMENT_DELAY
	      cyclerFeeder_state_fired$D_IN;
	if (cyclerFeeder_state_mkFSMstate$EN)
	  cyclerFeeder_state_mkFSMstate <= `BSV_ASSIGNMENT_DELAY
	      cyclerFeeder_state_mkFSMstate$D_IN;
	if (cycler_clockDiv_ctr$EN)
	  cycler_clockDiv_ctr <= `BSV_ASSIGNMENT_DELAY
	      cycler_clockDiv_ctr$D_IN;
	if (cycler_cyclingFIFO_rCache$EN)
	  cycler_cyclingFIFO_rCache <= `BSV_ASSIGNMENT_DELAY
	      cycler_cyclingFIFO_rCache$D_IN;
	if (cycler_cyclingFIFO_rRdPtr$EN)
	  cycler_cyclingFIFO_rRdPtr <= `BSV_ASSIGNMENT_DELAY
	      cycler_cyclingFIFO_rRdPtr$D_IN;
	if (cycler_cyclingFIFO_rWrPtr$EN)
	  cycler_cyclingFIFO_rWrPtr <= `BSV_ASSIGNMENT_DELAY
	      cycler_cyclingFIFO_rWrPtr$D_IN;
	if (cycler_displayer_bcdDecodedInput_0$EN)
	  cycler_displayer_bcdDecodedInput_0 <= `BSV_ASSIGNMENT_DELAY
	      cycler_displayer_bcdDecodedInput_0$D_IN;
	if (cycler_displayer_bcdDecodedInput_1$EN)
	  cycler_displayer_bcdDecodedInput_1 <= `BSV_ASSIGNMENT_DELAY
	      cycler_displayer_bcdDecodedInput_1$D_IN;
	if (cycler_displayer_bcdDecodedInput_2$EN)
	  cycler_displayer_bcdDecodedInput_2 <= `BSV_ASSIGNMENT_DELAY
	      cycler_displayer_bcdDecodedInput_2$D_IN;
	if (cycler_displayer_bcdDecodedInput_3$EN)
	  cycler_displayer_bcdDecodedInput_3 <= `BSV_ASSIGNMENT_DELAY
	      cycler_displayer_bcdDecodedInput_3$D_IN;
	if (cycler_displayer_clockDiv_ctr$EN)
	  cycler_displayer_clockDiv_ctr <= `BSV_ASSIGNMENT_DELAY
	      cycler_displayer_clockDiv_ctr$D_IN;
	if (cycler_displayer_currentDigitIndex$EN)
	  cycler_displayer_currentDigitIndex <= `BSV_ASSIGNMENT_DELAY
	      cycler_displayer_currentDigitIndex$D_IN;
	if (cycler_displayer_isNegative$EN)
	  cycler_displayer_isNegative <= `BSV_ASSIGNMENT_DELAY
	      cycler_displayer_isNegative$D_IN;
	if (cycler_displayer_readyToDisplay$EN)
	  cycler_displayer_readyToDisplay <= `BSV_ASSIGNMENT_DELAY
	      cycler_displayer_readyToDisplay$D_IN;
	if (displayModule_bcdDecodedInput_0$EN)
	  displayModule_bcdDecodedInput_0 <= `BSV_ASSIGNMENT_DELAY
	      displayModule_bcdDecodedInput_0$D_IN;
	if (displayModule_bcdDecodedInput_1$EN)
	  displayModule_bcdDecodedInput_1 <= `BSV_ASSIGNMENT_DELAY
	      displayModule_bcdDecodedInput_1$D_IN;
	if (displayModule_bcdDecodedInput_2$EN)
	  displayModule_bcdDecodedInput_2 <= `BSV_ASSIGNMENT_DELAY
	      displayModule_bcdDecodedInput_2$D_IN;
	if (displayModule_bcdDecodedInput_3$EN)
	  displayModule_bcdDecodedInput_3 <= `BSV_ASSIGNMENT_DELAY
	      displayModule_bcdDecodedInput_3$D_IN;
	if (displayModule_clockDiv_ctr$EN)
	  displayModule_clockDiv_ctr <= `BSV_ASSIGNMENT_DELAY
	      displayModule_clockDiv_ctr$D_IN;
	if (displayModule_currentDigitIndex$EN)
	  displayModule_currentDigitIndex <= `BSV_ASSIGNMENT_DELAY
	      displayModule_currentDigitIndex$D_IN;
	if (displayModule_isNegative$EN)
	  displayModule_isNegative <= `BSV_ASSIGNMENT_DELAY
	      displayModule_isNegative$D_IN;
	if (displayModule_readyToDisplay$EN)
	  displayModule_readyToDisplay <= `BSV_ASSIGNMENT_DELAY
	      displayModule_readyToDisplay$D_IN;
	if (ledStatus$EN) ledStatus <= `BSV_ASSIGNMENT_DELAY ledStatus$D_IN;
	if (leftInt_holdsNewValue$EN)
	  leftInt_holdsNewValue <= `BSV_ASSIGNMENT_DELAY
	      leftInt_holdsNewValue$D_IN;
	if (leftInt_valueHolder$EN)
	  leftInt_valueHolder <= `BSV_ASSIGNMENT_DELAY
	      leftInt_valueHolder$D_IN;
	if (rightInt_holdsNewValue$EN)
	  rightInt_holdsNewValue <= `BSV_ASSIGNMENT_DELAY
	      rightInt_holdsNewValue$D_IN;
	if (rightInt_valueHolder$EN)
	  rightInt_valueHolder <= `BSV_ASSIGNMENT_DELAY
	      rightInt_valueHolder$D_IN;
	if (toCompute_holdsNewValue$EN)
	  toCompute_holdsNewValue <= `BSV_ASSIGNMENT_DELAY
	      toCompute_holdsNewValue$D_IN;
	if (toCompute_valueHolder$EN)
	  toCompute_valueHolder <= `BSV_ASSIGNMENT_DELAY
	      toCompute_valueHolder$D_IN;
      end
    if (alu_leftOp$EN) alu_leftOp <= `BSV_ASSIGNMENT_DELAY alu_leftOp$D_IN;
    if (alu_powerModule_currentBase$EN)
      alu_powerModule_currentBase <= `BSV_ASSIGNMENT_DELAY
	  alu_powerModule_currentBase$D_IN;
    if (alu_powerModule_currentExponent$EN)
      alu_powerModule_currentExponent <= `BSV_ASSIGNMENT_DELAY
	  alu_powerModule_currentExponent$D_IN;
    if (alu_powerModule_result$EN)
      alu_powerModule_result <= `BSV_ASSIGNMENT_DELAY
	  alu_powerModule_result$D_IN;
    if (alu_result$EN) alu_result <= `BSV_ASSIGNMENT_DELAY alu_result$D_IN;
    if (alu_rightOp$EN) alu_rightOp <= `BSV_ASSIGNMENT_DELAY alu_rightOp$D_IN;
    if (computeBuf$EN) computeBuf <= `BSV_ASSIGNMENT_DELAY computeBuf$D_IN;
    if (cycler_displayer_doubleDabbleCtr$EN)
      cycler_displayer_doubleDabbleCtr <= `BSV_ASSIGNMENT_DELAY
	  cycler_displayer_doubleDabbleCtr$D_IN;
    if (cycler_displayer_toDisplay$EN)
      cycler_displayer_toDisplay <= `BSV_ASSIGNMENT_DELAY
	  cycler_displayer_toDisplay$D_IN;
    if (displayModule_doubleDabbleCtr$EN)
      displayModule_doubleDabbleCtr <= `BSV_ASSIGNMENT_DELAY
	  displayModule_doubleDabbleCtr$D_IN;
    if (displayModule_toDisplay$EN)
      displayModule_toDisplay <= `BSV_ASSIGNMENT_DELAY
	  displayModule_toDisplay$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    alu_isDone = 1'h0;
    alu_isQueued = 1'h0;
    alu_leftOp = 33'h0AAAAAAAA;
    alu_op = 4'hA;
    alu_powerModule_currentBase = 33'h0AAAAAAAA;
    alu_powerModule_currentExponent = 32'hAAAAAAAA;
    alu_powerModule_result = 33'h0AAAAAAAA;
    alu_result = 33'h0AAAAAAAA;
    alu_rightOp = 33'h0AAAAAAAA;
    buttonStatus_0 = 1'h0;
    buttonStatus_1 = 1'h0;
    buttonStatus_2 = 1'h0;
    buttonStatus_3 = 1'h0;
    buttonStatus_4 = 1'h0;
    clockDiv_ctr = 28'hAAAAAAA;
    computeBuf = 33'h0AAAAAAAA;
    currentDigitIndex = 2'h2;
    currentIsSigned = 1'h0;
    currentNumberS = 11'h2AA;
    currentNumberU = 4'hA;
    cyclerFeeder_start_reg = 1'h0;
    cyclerFeeder_start_reg_1 = 1'h0;
    cyclerFeeder_state_can_overlap = 1'h0;
    cyclerFeeder_state_fired = 1'h0;
    cyclerFeeder_state_mkFSMstate = 4'hA;
    cycler_clockDiv_ctr = 32'hAAAAAAAA;
    cycler_cyclingFIFO_rCache = 26'h2AAAAAA;
    cycler_cyclingFIFO_rRdPtr = 9'h0AA;
    cycler_cyclingFIFO_rWrPtr = 9'h0AA;
    cycler_displayer_bcdDecodedInput_0 = 4'hA;
    cycler_displayer_bcdDecodedInput_1 = 4'hA;
    cycler_displayer_bcdDecodedInput_2 = 4'hA;
    cycler_displayer_bcdDecodedInput_3 = 4'hA;
    cycler_displayer_clockDiv_ctr = 19'h2AAAA;
    cycler_displayer_currentDigitIndex = 2'h2;
    cycler_displayer_doubleDabbleCtr = 4'hA;
    cycler_displayer_isNegative = 1'h0;
    cycler_displayer_readyToDisplay = 1'h0;
    cycler_displayer_toDisplay = 14'h2AAA;
    displayModule_bcdDecodedInput_0 = 4'hA;
    displayModule_bcdDecodedInput_1 = 4'hA;
    displayModule_bcdDecodedInput_2 = 4'hA;
    displayModule_bcdDecodedInput_3 = 4'hA;
    displayModule_clockDiv_ctr = 19'h2AAAA;
    displayModule_currentDigitIndex = 2'h2;
    displayModule_doubleDabbleCtr = 4'hA;
    displayModule_isNegative = 1'h0;
    displayModule_readyToDisplay = 1'h0;
    displayModule_toDisplay = 14'h2AAA;
    ledStatus = 16'hAAAA;
    leftInt_holdsNewValue = 1'h0;
    leftInt_valueHolder = 32'hAAAAAAAA;
    rightInt_holdsNewValue = 1'h0;
    rightInt_valueHolder = 32'hAAAAAAAA;
    toCompute_holdsNewValue = 1'h0;
    toCompute_valueHolder = 3'h2;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (displayModule_readyToDisplay && displayModule_clockDiv_ctr == 19'd0)
	$display("displayed digit: ",
		 $unsigned(SEL_ARR_displayModule_bcdDecodedInput_0_0_disp_ETC___d15));
    if (RST_N != `BSV_RESET_VALUE)
      if (cycler_displayer_readyToDisplay &&
	  cycler_displayer_clockDiv_ctr == 19'd0)
	$display("displayed digit: ",
		 $unsigned(SEL_ARR_cycler_displayer_bcdDecodedInput_0_54__ETC___d159));
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cycler_cycle)
	$display("displaying ",
		 { CASE_cycler_cyclingFIFO_wDataOutwget_BITS_15__ETC__q4,
		   cycler_cyclingFIFO_wDataOut$wget[13:0] },
		 " now");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l120c16)
	$display("enqued ", 16'd43690);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l121c18)
	$display("enqued ", { 2'd0, leftInt_valueHolder[13:0] });
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l122c18)
	$display("enqued ", { 2'd0, rightInt_valueHolder[13:0] });
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l127c9 && computeBuf[32] &&
	  IF_computeBuf_68_BIT_31_70_THEN_NEG_computeBuf_ETC___d474)
	$display("enqued ", { 2'd1, computeBuf[13:0] });
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l127c9 && computeBuf[32] &&
	  !IF_computeBuf_68_BIT_31_70_THEN_NEG_computeBuf_ETC___d474)
	$display("enqued ", 16'd43689);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l127c9 && !computeBuf[32] &&
	  computeBuf_68_BITS_31_TO_0_71_ULE_9999___d479)
	$display("enqued ", { 2'd0, computeBuf[13:0] });
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l127c9 && !computeBuf[32] &&
	  !computeBuf_68_BITS_31_TO_0_71_ULE_9999___d479)
	$display("enqued ", 16'd43689);
    if (RST_N != `BSV_RESET_VALUE)
      if (cyclerFeeder_state_mkFSMstate == 4'd1 &&
	  (WILL_FIRE_RL_cyclerFeeder_action_l120c16 ||
	   WILL_FIRE_RL_cyclerFeeder_action_l121c18 ||
	   WILL_FIRE_RL_cyclerFeeder_action_l122c18 ||
	   WILL_FIRE_RL_cyclerFeeder_action_l123c9 ||
	   WILL_FIRE_RL_cyclerFeeder_action_l127c9))
	$display("Error: \"TopModule.bsv\", line 117, column 9: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_cyclerFeeder_action_l117c9]\n  and [RL_cyclerFeeder_action_l120c16, RL_cyclerFeeder_action_l121c18,\n  RL_cyclerFeeder_action_l122c18, RL_cyclerFeeder_action_l123c9,\n  RL_cyclerFeeder_action_l127c9] ) fired in the same clock cycle.\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l120c16 &&
	  (WILL_FIRE_RL_cyclerFeeder_action_l121c18 ||
	   WILL_FIRE_RL_cyclerFeeder_action_l122c18 ||
	   WILL_FIRE_RL_cyclerFeeder_action_l123c9 ||
	   WILL_FIRE_RL_cyclerFeeder_action_l127c9))
	$display("Error: \"TopModule.bsv\", line 120, column 16: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_cyclerFeeder_action_l120c16]\n  and [RL_cyclerFeeder_action_l121c18, RL_cyclerFeeder_action_l122c18,\n  RL_cyclerFeeder_action_l123c9, RL_cyclerFeeder_action_l127c9] ) fired in the\n  same clock cycle.\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l121c18 &&
	  (WILL_FIRE_RL_cyclerFeeder_action_l122c18 ||
	   WILL_FIRE_RL_cyclerFeeder_action_l123c9 ||
	   WILL_FIRE_RL_cyclerFeeder_action_l127c9))
	$display("Error: \"TopModule.bsv\", line 121, column 18: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_cyclerFeeder_action_l121c18]\n  and [RL_cyclerFeeder_action_l122c18, RL_cyclerFeeder_action_l123c9,\n  RL_cyclerFeeder_action_l127c9] ) fired in the same clock cycle.\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l122c18 &&
	  (WILL_FIRE_RL_cyclerFeeder_action_l123c9 ||
	   WILL_FIRE_RL_cyclerFeeder_action_l127c9))
	$display("Error: \"TopModule.bsv\", line 122, column 18: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_cyclerFeeder_action_l122c18]\n  and [RL_cyclerFeeder_action_l123c9, RL_cyclerFeeder_action_l127c9] ) fired\n  in the same clock cycle.\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l123c9 &&
	  WILL_FIRE_RL_cyclerFeeder_action_l127c9)
	$display("Error: \"TopModule.bsv\", line 123, column 9: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_cyclerFeeder_action_l123c9]\n  and [RL_cyclerFeeder_action_l127c9] ) fired in the same clock cycle.\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l111c9)
	$display(toCompute_valueHolder);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l111c9)
	$display({ 1'd0, leftInt_valueHolder });
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l111c9)
	$display({ 1'd0, rightInt_valueHolder });
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l111c9) $display(alu_isDone);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_cyclerFeeder_action_l111c9 &&
	  (cyclerFeeder_state_mkFSMstate == 4'd1 ||
	   WILL_FIRE_RL_cyclerFeeder_action_l120c16 ||
	   WILL_FIRE_RL_cyclerFeeder_action_l121c18 ||
	   WILL_FIRE_RL_cyclerFeeder_action_l122c18 ||
	   WILL_FIRE_RL_cyclerFeeder_action_l123c9 ||
	   WILL_FIRE_RL_cyclerFeeder_action_l127c9))
	$display("Error: \"TopModule.bsv\", line 111, column 9: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_cyclerFeeder_action_l111c9]\n  and [RL_cyclerFeeder_action_l117c9, RL_cyclerFeeder_action_l120c16,\n  RL_cyclerFeeder_action_l121c18, RL_cyclerFeeder_action_l122c18,\n  RL_cyclerFeeder_action_l123c9, RL_cyclerFeeder_action_l127c9] ) fired in the\n  same clock cycle.\n");
  end
  // synopsys translate_on
endmodule  // mkTopModule